const fpga2 = 1;
const fpga1 = 2;
const dut   = 2;
const ni0   = 3;
const ni1   = 4;
const ni2   = 5;
const ni3   = 6;
// base address of the JTAG master
const jtg_up  = 0x4100;
const jtg_dn  = 0x4200;
const jtg_dut = 0x4300;
// offset relative to the base address of the JTAG master
const tms_wr  = 0x00A0;
const jtg_sm  = 0x0080;
const jtg_cnf = 0x00C0; // speed(1..0) enable(3..2)
// conf reg scsn switch
const scsn_sw = 0x4400;
const tst_pads = 0x4490;
const dig_pot =  0x50C0;
const pwr_ena =  0x5080;

// scsn ring fpga2+fpga1
write fpga2, scsn_sw, 1;
reset;
wait 0;
nop;
expect fpga2, tst_pads, 1001b;
write fpga1, pwr_ena, 01b;
wait 0;
write fpga1, pwr_ena, 10b;
wait 0;
write fpga1, pwr_ena, 11b;
wait 0;
expect fpga2, tst_pads, 1001b;

// serial ADC configuration
write 0x5404, 0x0460;
//write 0x5404, 0x1000;
nop
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;

wait 0
expect fpga2, tst_pads, 1001b;
write fpga1, dig_pot, 0x00000000;
wait 0
expect fpga2, tst_pads, 1001b;
write fpga1, dig_pot, (09 << 24) | (09 << 16) | (09 << 8) | 09;
wait 0
// current limits
write 0x5406, 0x00100100;
write 0x5407, 0x00100100;
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
write fpga1, dig_pot, (19 << 24) | (19 << 16) | (19 << 8) | 19;
wait 0
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
write fpga1, dig_pot, (29 << 24) | (29 << 16) | (29 << 8) | 29;
wait 0
write fpga1, pwr_ena, 11b;
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
write fpga1, dig_pot, (39 << 24) | (39 << 16) | (39 << 8) | 39;
wait 0
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
write fpga1, dig_pot, (49 << 24) | (49 << 16) | (49 << 8) | 49;
wait 0
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
write fpga1, dig_pot, (59 << 24) | (59 << 16) | (59 << 8) | 59;
wait 0
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
write fpga1, dig_pot, (69 << 24) | (69 << 16) | (69 << 8) | 69;
wait 0
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
write fpga1, dig_pot, (79 << 24) | (79 << 16) | (79 << 8) | 79;
wait 0
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
write fpga1, dig_pot, (89 << 24) | (89 << 16) | (89 << 8) | 89;
wait 0
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
write fpga1, dig_pot, (99 << 24) | (99 << 16) | (99 << 8) | 99;
wait 0
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;