const fpga2 = 1;
const fpga1 = 2;
const dut   = 2;
const ni0   = 3;
const ni1   = 4;
const ni2   = 5;
const ni3   = 6;
// base address of the JTAG master
const jtg_up  = 0x4100;
const jtg_dn  = 0x4200;
const jtg_dut = 0x4300;
// offset relative to the base address of the JTAG master
const tms_wr  = 0x00A0;
const jtg_sm  = 0x0080;
const jtg_cnf = 0x00C0; // speed(1..0) enable(3..2)
// conf reg scsn switch
const scsn_sw = 0x4400;
const tst_pads = 0x4490;
const dig_pot =  0x50C0;
const pwr_ena =  0x5080;

// scsn ring fpga2+fpga1
write fpga2, scsn_sw, 1;
reset;
//wait 0;
nop;
//write fpga1, pwr_ena, 11b;

// serial ADC configuration
//write 0x5404, 0x0460;
contin       = 0;
internal_ref = 0; // 1 for internal, 0 for external
ref_sel      = 1; // 0 for 4V, 1 for 2V
long_sampl   = 0; // short
conv_clock   = 0; // internal osc
conv_mode    = 3; // repeat sweep
sweep_sq     = 0; //
eoc          = 0; //
fifo_lev     = 0; 
write 0x5404, (contin << 12) | (internal_ref << 11) | (ref_sel << 10) | (long_sampl << 9) | (conv_clock << 7) | (conv_mode <<5) | (sweep_sq << 3) | (eoc << 2) | fifo_lev;
//write 0x5404, 0x1000;
nop
V18D = 30;
V18A = 30;
V33D = 15;
V33A = 15;
write fpga1, dig_pot, (V18D << 24) | (V33D << 16) | (V18A << 8) | V33A;
// current limits
write 0x5406, 0x00FFFFFF;
write 0x5407, 0x00FFFFFF;
// measure 0
write 0x5400, 0x1000;
nop
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
//wait 0
write fpga1, pwr_ena, 11b;
//wait 0
// measure on
write 0x5400, 0x1000;
nop
read fpga1, 0x5400;
read fpga1, 0x5401;
read fpga1, 0x5402;
read fpga1, 0x5403;
//wait 0
// off
//write fpga1, pwr_ena, 00b;