// scsn config fpga1 + fpga2
write 0x4400, 1

// power on only analog part
write 2, 0x50C0, (59 << 24) | (59 << 16) | (59 << 8) | 59;
write 2, 0x5080, 1

amplitude = 2000;
timedelta =   50;
pt_delay0 =   24;
pt_delay1 =   48;

// configure dacs
write 2, 0x5520, (pt_delay0             << 20) | (0 << 16) |   amplitude
// next time bin
write 2, 0x5521, (pt_delay1             << 20) | (1 << 16) |   amplitude

restrict 0
// go back to pulse amplitude 0, later
write 2, 0x5522, (509 << 20) | (0 << 16) | 0
write 2, 0x5523, (511 << 20) | (1 << 16) | 0
write 2, 0x5524, (0                     << 20) | (0 << 16) |   0
restrict 1

// configure dacs
write 2, 0x5522, (pt_delay0+  timedelta << 20) | (0 << 16) | 2*amplitude
// next time bin
write 2, 0x5523, (pt_delay1+  timedelta << 20) | (1 << 16) | 2*amplitude

// configure dacs
write 2, 0x5524, (pt_delay0+2*timedelta << 20) | (0 << 16) | 3*amplitude
// next time bin
write 2, 0x5525, (pt_delay1+2*timedelta << 20) | (1 << 16) | 3*amplitude

// configure dacs
write 2, 0x5526, (pt_delay0+3*timedelta << 20) | (0 << 16) | 4*amplitude
// next time bin
write 2, 0x5527, (pt_delay1+3*timedelta << 20) | (1 << 16) | 4*amplitude

// configure dacs
write 2, 0x5528, (pt_delay0+4*timedelta << 20) | (0 << 16) | 5*amplitude
// next time bin
write 2, 0x5529, (pt_delay1+4*timedelta << 20) | (1 << 16) | 5*amplitude

// configure dacs
write 2, 0x552A, (pt_delay0+5*timedelta << 20) | (0 << 16) | 6*amplitude
// next time bin
write 2, 0x552B, (pt_delay1+5*timedelta << 20) | (1 << 16) | 6*amplitude

// go back to pulse amplitude 0, later
write 2, 0x552C, (509 << 20) | (0 << 16) | 0
write 2, 0x552D, (511 << 20) | (1 << 16) | 0

// end marker (time 0)
write 2, 0x552E, (0 << 20) | (0 << 16) | 0

// configure for start by pretrigger
restrict 1
write 2, 0x5500, 4+1

pretrigger 1