const fpga2 = 1;
const fpga1 = 2;

const scsn_sw = 0x4400;

// scsn ring fpga2+fpga1
write fpga2, scsn_sw, 1;
reset;
nop;
//wait 0;
nop;
nop;
nop;
// pasa adc start
write fpga1, 0x5C00, 1011100b;

// THE MINIMUM CONFIGURATION necessary for proper serial interface!!!
// DDS reset
write fpga1, 0x5204, 1001b;
expect fpga1, 0x5204, 1001b;
// DDS auto ud clock and refclk disable
write fpga1, 0x5204, 1000b;
expect fpga1, 0x5204, 1000b;
// wait 0;
// config register in DDS
//write fpga1, 0x5200, 0x10640021;
write fpga1, 0x5200, 0x10640021;
// send the instruction and bits 32..47
write fpga1, 0x5201, (00000111b << 16);
// DDS auto ud clock and refclk enable
//wait 0;
write fpga1, 0x5204, 1010b;
expect fpga1, 0x5200, 0x10640021;
// END OF THE MINIMUM CONFIGURATION necessary for proper serial interface!!!
//
//
// NOW WRITING !!!
//
//
// write reg 0, 14 bits
write fpga1, 0x5200, 0x230;
// send the instruction and bits 32..47
write fpga1, 0x5201, (00000000b << 16);
// write reg 1, 14 bits
write fpga1, 0x5200, 0x361;
// send the instruction and bits 32..47
write fpga1, 0x5201, (00000001b << 16);
// write reg 2, 48 bits
//wait 0;
write fpga1, 0x5200, 0x00000000;
write fpga1, 0x5201, 0x00020400;

write fpga1, 0x5C00, 00010000b;
write fpga1, 0x5C00, 10010000b;

//wait 0;
// write reg 3, 48 bits
write fpga1, 0x5200, 0x87654323;
write fpga1, 0x5201, 0x0003FEDC;
// write reg 4, 48 bits
write fpga1, 0x5200, 0xDEADFAC4;
write fpga1, 0x5201, 0x0004AFFE;
// write reg 5, 32 bits
write fpga1, 0x5200, 0xDEADAFF5;
write fpga1, 0x5201, 0x00050000;
// write reg 6, 20 bits
write fpga1, 0x5200, 0x000BAFF6;
write fpga1, 0x5201, 0x00060000;
// DON'T TRY to test reg 7, it is the config register!!!
// write reg 8, 12 bits
write fpga1, 0x5200, 0x00000BE8;
write fpga1, 0x5201, 0x00080000;
// write reg 9, 12 bits
write fpga1, 0x5200, 0x00000929;
write fpga1, 0x5201, 0x00090000;
// write reg 10, 8 bits
write fpga1, 0x5200, 0x000000BA;
write fpga1, 0x5201, 0x000A0000;
// write reg 11, 12 bits
write fpga1, 0x5200, 0x00000C3B;
write fpga1, 0x5201, 0x000B0000;
//
// NOW READING !!!
//
// DDS init reset
//write fpga1, 0x5204, 1001b;
//write fpga1, 0x5204, 1000b;
//write fpga1, 0x5200, 0x10640021;
//write fpga1, 0x5201, (00000111b << 16);
//write fpga1, 0x5204, 1010b;
//
// read reg 0
write fpga1, 0x5201, (10000000b << 16);
expect fpga1, 0x5202, 0x230;
expect fpga1, 0x5203, 0x00000000;
// read reg 1
write fpga1, 0x5201, (10000001b << 16);
expect fpga1, 0x5202, 0x361;
expect fpga1, 0x5203, 0x00000000;
// read reg 2
write fpga1, 0x5201, (10000010b << 16);
expect fpga1, 0x5202, 0x00000000;
expect fpga1, 0x5203, 0x00000400;
// read reg 3
write fpga1, 0x5201, (10000011b << 16);
expect fpga1, 0x5202, 0x87654323;
expect fpga1, 0x5203, 0x0000FEDC;
// read reg 4
write fpga1, 0x5201, (10000100b << 16);
expect fpga1, 0x5202, 0xDEADFAC4;
expect fpga1, 0x5203, 0x0000AFFE;
// read reg 5
write fpga1, 0x5201, (10000101b << 16);
expect fpga1, 0x5202, 0xDEADAFF5;
expect fpga1, 0x5203, 0x00000000;
// read reg 6
write fpga1, 0x5201, (10000110b << 16);
expect fpga1, 0x5202, 0x000BAFF6;
expect fpga1, 0x5203, 0x00000000;
// read reg 8
write fpga1, 0x5201, (10001000b << 16);
expect fpga1, 0x5202, 0x00000BE8;
expect fpga1, 0x5203, 0x00000000;
// read reg 9
write fpga1, 0x5201, (10001001b << 16);
expect fpga1, 0x5202, 0x00000929;
expect fpga1, 0x5203, 0x00000000;
// read reg 10
write fpga1, 0x5201, (10001010b << 16);
expect fpga1, 0x5202, 0x000000BA;
expect fpga1, 0x5203, 0x00000000;
// read reg 11
write fpga1, 0x5201, (10001011b << 16);
// bits 15..12 are don't care and come as 0100.
expect fpga1, 0x5202, 0x00004C3B;
expect fpga1, 0x5203, 0x00000000;