/**************************************/ /* ALICE TRD */ /* Read-out board */ /* SCSN Configuration File */ /* */ /* 2004-03-08 */ /* Jan de Cuveland, Venelin Angelov */ /**************************************/ // Readout tree (logical view) // // 00 01 -0> 02 <3- 03 // `--------1/ \----------, // | // 04 05 -0> 06 <3- 07 2 // `--------1/ \--------0,| // || // 16 --> // 08 09 -0> 10 <3- 11 || // `--------1/ \--------1´| // | // 12 13 -0> 14 <3- 15 3 // `--------1/ \----------´ const padrow_range = 0; // 0..3 const irq_ni = 8; const irq_tm = 6; const irq_clr = 0; // Note irq_clr is 4 in trap2! const irq_acq = 2; const irq_raw = 4; const nsig_tr = 0xAAAA; const nsig_rr = 0x0000; // -------------------------------- // Assembler program parameters // -------------------------------- // Event Counter, con12 write 0x0C04, 10 // set to 0x00 for ADC readout or to 0x1E for test data readout write EBAQA, 0x00 write TPCBY, 0 const nsamples=30; // Event Header con9, cpu0 write 0x0C01, 0x07AB // nsamples*64+0x2B // Number of Samples, c13 write 0x0C05, nsamples // Tracklet & Raw Data End Marker write 0x0C06, nsig_tr; // c14 write 0x0C07, nsig_rr; // c15 // set end signature (rr: 0x----0000, tr: 0x----1000) write NES, nsig_tr | (nsig_rr << 16); // -------------------------------- // NI transmission delay // -------------------------------- // for 50:50 here the number of 32 bit words send by each CPU. // delay between ni_ctrl and end marker, this is c8 of cpu3 const delay_ni = 504; // 504; // 8*nsamples/3+1; write 0x0C1B, delay_ni; // const11 write IA3+irq_ni+2, 0x0500; // start address irq_ni for fifo empty write NBND, 0xF001; // thresholds fifo write IA3+irq_tm, 0x0600; // start address counter/timer // ------------------------ // set constant registers // ------------------------ // c12 - z-pos 4 bit, here test pattern // hamming correction for all memories! write MEMCOR, 0x01FF; // arbiter timing write ARBTIM, 1101b; // ------------------------- // set int entry addresses // ------------------------- include WRK/cpu0_labels.tcs include WRK/cpu1_labels.tcs include WRK/cpu2_labels.tcs include WRK/cpu3_labels.tcs write IA0+irq_clr, lbl_CLR_cpu0; // set int_clr start addr for cpu0 write IA1+irq_clr, lbl_CLR_cpu1; // set int_clr start addr for cpu1 write IA2+irq_clr, lbl_CLR_cpu2; // set int_clr start addr for cpu2 write IA3+irq_clr, lbl_CLR_cpu3; // set int_clr start addr for cpu3 write IA0+irq_acq, lbl_ACQ_cpu0; // set int_acq start addr for cpu0 write IA1+irq_acq, lbl_ACQ_cpu1; // set int_acq start addr for cpu1 write IA2+irq_acq, lbl_ACQ_cpu2; // set int_acq start addr for cpu2 write IA3+irq_acq, lbl_ACQ_cpu3; // set int_acq start addr for cpu3 write IA0+irq_raw, lbl_RAW_cpu0; // set int_raw start addr for cpu0 write IA1+irq_raw, lbl_RAW_cpu1; // set int_raw start addr for cpu1 write IA2+irq_raw, lbl_RAW_cpu2; // set int_raw start addr for cpu2 write IA3+irq_raw, lbl_RAW_cpu3; // set int_raw start addr for cpu3 // --------------- // set int masks // --------------- const irq_msk = (1 << irq_acq) | (1 << irq_clr) | (1 << irq_raw); write IRQHW0, irq_msk; // set irq_hw mask for cpu0 write IRQHL0, irq_msk; // set irq_hl mask cor cpu0 write IRQHW1, irq_msk; // set irq_hw mask for cpu1 write IRQHL1, irq_msk; // set irq_hl mask cor cpu1 write IRQHW2, irq_msk; // set irq_hw mask for cpu2 write IRQHL2, irq_msk; // set irq_hl mask cor cpu2 write IRQHW3, irq_msk; // set irq_hw mask for cpu3 write IRQHL3, irq_msk; // set irq_hl mask cor cpu3 // ------------------------------ // enable/disable LVDS clock and pretrigger fanout LVDS cells // ------------------------------ // switching the unused pre & clk & ni ports off // normal chips write chip0 , SMMODE, 0xE2 write chip1 , SMMODE, 0xE2 write chip3 , SMMODE, 0xE2 write chip4 , SMMODE, 0xE2 write chip5 , SMMODE, 0xE2 write chip7 , SMMODE, 0xE2 write chip8 , SMMODE, 0xE2 write chip9 , SMMODE, 0xE2 write chip11, SMMODE, 0xE2 write chip12, SMMODE, 0xE2 write chip13, SMMODE, 0xE2 write chip15, SMMODE, 0xE2 // column merger chips write chip2 , SMMODE, 0xB0E2 write chip6 , SMMODE, 0xB0E2 write chip10, SMMODE, 0xB0E2 write chip14, SMMODE, 0xB0E2 write chip_bm, SMMODE, 1111011101110100b; // full-time merger (no CPU) // ------------------------- // configure clock control // ------------------------- write CPU0CLK, 0x3F; write CPU1CLK, 0x3F; write CPU2CLK, 0x3F; write CPU3CLK, 0x3F; // these chips don't use the CPUs write chip_bm, CPU0CLK, 0x00; write chip_bm, CPU1CLK, 0x00; write chip_bm, CPU2CLK, 0x00; write chip_bm, CPU3CLK, 0x00; // these chips don't use the filter and preprocessor //write chip_bm, SMCMD, 0x0112; // go to acq mode to switch filter/preprocessor clocks on //write chip_bm, FILCLK, 0; // now filter preprocessor can be switched off, //write chip_bm, PRECLK, 0; // ... but we need some clocks!!! //write chip_bm, SMCMD, 0x0012; // low power mode // ----------------------------- // configure network interface // ----------------------------- // NI output excludes and ctrl delay: chip_rm is root in optical link mode //write NDLY, 0x12492492; // all data bits delay 2 write NDLY, (t_data_delay0) | (t_data_delay1 << 3) | (t_data_delay2 << 6) | (t_data_delay3 << 9) | (t_data_delay4 << 12) | (t_data_delay5 << 15) | (t_data_delay6 << 18) | (t_data_delay7 << 21) | (t_data_delay8 << 24) | (t_data_delay9 << 27); write chip_bm, NDLY, (m_data_delay0) | (m_data_delay1 << 3) | (m_data_delay2 << 6) | (m_data_delay3 << 9) | (m_data_delay4 << 12) | (m_data_delay5 << 15) | (m_data_delay6 << 18) | (m_data_delay7 << 21) | (m_data_delay8 << 24) | (m_data_delay9 << 27); const NPw = (t_parit_bit << 7) | (t_false_bit << 3) | 4; write NP0, NPw; write NP1, NPw; write NP2, NPw; write NP3, NPw; // all chips, all input ports, exclude bits // write NP0, 0x03CC; // excluce bit 7 // write NP1, 0x03CC; // excluce bit 7 // write NP2, 0x03CC; // excluce bit 7 // write NP3, 0x03CC; // excluce bit 7 //write NED, 0x1E40; // incl bm, bm0,1 now write NED , (root_all << 14) | (0 << 15) | (t_parit_bit << 10) | (t_false_bit << 6) | (t_ctrl_delay << 3) | t_strb_delay; write chip_bm, NED , (root_bm << 14) | (0 << 15) | (m_parit_bit << 10) | (m_false_bit << 6) | (m_ctrl_delay << 3) | m_strb_delay; //Old: //write chip_bm, NED, (root_bm << 14) | 0x1E40; // readout order configuration constants const niro_normal = 0x0003FFFC; // 1 -> 0 -> own -> 3 const niro_cm = 0x1FE21; // for all const niro_bm_t = 0x00039e13; // 3 -> 1 -> 0 -> 2 //const niro_bm_t = 0x0003f1da; // 2 0 3 const niro_bm_r = 0x0003f0ca; // 2 0 1 3 - Alice numbering scheme //const niro_bm_r = 0x0003f1da; // 2 0 3 - Alice numbering scheme // const niro_noo = 0x0003fe19; // set NI trigger readout order write NTRO, niro_normal; restrict 0 write chip2, NTRO, niro_cm; write chip6, NTRO, niro_cm; write chip10, NTRO, niro_cm; write chip14, NTRO, niro_cm; write chip_bm, NTRO, niro_bm_t; restrict 1 // set NI raw data readout order write NRRO, niro_normal; restrict 0 write chip2, NRRO, niro_cm; write chip6, NRRO, niro_cm; write chip10, NRRO, niro_cm; write chip14, NRRO, niro_cm; write chip_bm, NRRO, niro_bm_r; restrict 1 // timers for NI signals write NITM0, 0x01D0; // 0x153; // NI timer 0 (clock) write chip_bm, NITM0, 0x01D6; // 0x159; // NI timer 0 (clock) write NITM1, 0x01E2; // 0x165; // NI timer 1 (IO data) write chip_bm, NITM2, 0x022F+24+100; // NI timer 2 (clock) write NIP4D, 0x0F; // delays // only if chip_bm is not connected to OASE merger write chip_bm, NIP4D, 0xFF; // delays // configuration of the NI clock write NICLK, 0x3F; write chip_bm, NICLK, 11011b; // configuration of the NI output data port write NIODE, 11011b; write chip_bm, NIODE, 11111b; // configuration of the NI output control port write NIOCE, 0x3F; write chip_bm, NIOCE, 0x01; // was 3 // was 7 write NIOCE, 0x01; // can be optimized later // configuration of the NI input data ports write NIIDE, 0x3F; write chip_bm, NIIDE, 0x07; // configuration of the NI input control ports write NIICE, 0x3F; write chip_bm, NIICE, 0x07; // --------------------- // misc. configuration // --------------------- // ADC off write chip_bm, ADCEN, 0; // -------------------------------- // configure global state machine // -------------------------------- write SML0, 0x00004050; // consider L0 & L0_time = 0x050 (80) write SML1, 0x00004230+24+100; // consider L1 & L1_time = 0x200 (512) write SML2, 0x000042BC+100; // consider L2 & L2_time = 0x2BC (700) //*************************** //* ADCs * //*************************** // ADC parameters, IRQ, sampling phase, en inp buffer, autozero, power const power_backgr = 5; // 0..7 const power_pretr = 5; // 0..7 const irq_phase = 6; // 0..11 const smp_phase = 2; // 0..11 const enibf_backgr = 0; // 0 or 1 const enibf_pretr = 0; // 0 or 1 const az_backgr = 0; // 0 or 1 const az_pretr = 0; // 0 or 1 write ADCPAR, power_backgr | (az_backgr << 3) | (enibf_backgr << 4) | (power_pretr << 5) | (az_pretr << 8) | (enibf_pretr << 9) | (smp_phase << 10) | (irq_phase << 14) // invert bits write ADCINB, 10b; // ADC DAC 5-bit write ADCDAC, 11111b;