#inc ; ------------------------------------------------------------------ ; -- -- ; -- Test program for the readout board -- ; -- For the ALICE TR-Detector at LHC -- ; -- Kirchhoff Institut für Physik -- ; -- Univesity of Heidelberg -- ; -- Germany -- ; -- -- ; -- 03.09.2004 VA -- ; ------------------------------------------------------------------ ; ; number of words to send #def nsamples =c12 ; the configuration reg of the psr_counter #def psr_mode =c14 ; start value for the data generation #def psrg_ini =c8; #def endsig_rr= c15 ; end signature for raw data readout #ifdef cpu0 #def clk_onoff = CPU0SS; #def psr_ini_gio = 0x0C00; #endif #ifdef cpu1 #def clk_onoff = CPU1SS; #def psr_ini_gio = 0x0C08; #endif #ifdef cpu2 #def clk_onoff = CPU2SS; #def psr_ini_gio = 0x0C10; #endif #ifdef cpu3 #def clk_onoff = CPU3SS; #def psr_ini_gio = 0x0C18; #endif ORG 0x0; jmpr cc_uncond, 0 nop ; IRQ clr ;ORG 0x100; clr: nop #ifdef cpu0 mov cmd_ext_clr, r0 ; sgio r0, SMCMD ; clear ready #endif #ifdef cpu2 mov b1111_0101_0000, r1 jmpr cc_busy, 0 sgio r1, SMOFF ; switch off all NI LVDS cells, clk_prepr, clk_ni #endif jmpr cc_uncond, 0 nop ;ORG 0x200; acq: nop shl 8, c5, r8 add r8, c13, r8 ; -- some delay mov 32, r0 delay: sub r0, c1, r0 jmp cc_nzero, delay mov 0x00, r0 or r0, r8, r0 ; start address in GIO of the DBANK iext 0xF000 mov 0xF000, r14 add r14, c5, r14 ; start address in DMEM shl 2, c5, r15 send: spio r0 NODP ; then send to the NI sgio+ r0 ; store to DBANK sra+ r0 ; store to DMEM jmpr cc_uncond 0 nop ;ORG 0x400 raw: nop ; IRQ raw data read #ifdef cpu0 mov cmd_CPU_done r0 sgio r0 SMCMD; #endif ; start address in GIO of DBANK mov nsamples, r1 mul32 r1, c5, r1 iext 0xF004 mov 0xF004, r14 add r14, r1, r14 ; start address in DMEM mov 16, r15 shl 2, r1, r1 add r1, r15, r15 mov 0, r4; number of words mov nsamples, r9 ; configure the psr_counter mov psr_mode, r1 spio r1, 0x201; mov psrg_ini, r1 andt r1, r1 jmp cc_zero, smp_test spio r1, 0x200; initial data iext 0xFFFF; mov 0xFFFF, r3; mask wfull: lpio 0x202, r1; read from PSRG shl 8, r1, r1; shift to 16..31 shl 8, r1, r1 lpio 0x202, r2; read from PSRG and r2, r3, r2; take only bits 0..15 or r2, r1, r2; merge with bits 16..31 spio r2, NODP; store to NI sgio+ r2; store to DBANK sra+ r2; store to DMEM add r4, c1, r4; inc the number of words ; !!! In some TRAPs we have timing problems with the compare !!! ; Therefore here is double cmp r4, nsamples; check if ready cmp r4, r9 ; check if ready cmp r4, r9 ; check if ready jmp cc_ltu, wfull ; store the next word as start for the next pretrigger lpio 0x202, r2 jmpr cc_busy, 0 sgio r2, psr_ini_gio jmp cc_uncond, sendem smp_test: shl -1, r9, r10; the half of the data words to be send shl -1, r9, r8; the half of the data words to be send iext 0x5555 mov 0x5555, r2 swp r2, r1 or r2, r1, r1 wfulls: spio r1, NODP; store to NI sgio+ r1; store to DBANK sra+ r1; store to DMEM add r4, c1, r4; inc the number of words cmp r4, r8 cmp r4, r10 jmpr cc_nzero, +2 not r1, r1 cmp r4, r9 cmp r4, r9 jmp cc_ltu, wfulls ; send end mark sendem: mov endsig_rr, r0 spio r0, NODP #ifdef cpu3 ; only cpu3 to get the end marker at the end! jmpr cc_busy, 0 ; sgio+ r0; store to DBANK sra+ r0; store to DMEM #endif jmpr cc_busy, 0 ; switch power off coff: mov 0, r0 sgio r0 clk_onoff ; each cpu stops its clock jmpr cc_uncond 0 nop