include src/chip_def.tcs

expect ni0,     NED,(root_ni << 14) | (0 << 15) | (t_parit_bit << 10) | (t_false_bit << 6) | (t_ctrl_delay << 3) | t0_strb_delay;
expect ni1,     NED,(root_ni << 14) | (0 << 15) | (t_parit_bit << 10) | (t_false_bit << 6) | (t_ctrl_delay << 3) | t1_strb_delay;
expect ni2,     NED,(root_ni << 14) | (0 << 15) | (t_parit_bit << 10) | (t_false_bit << 6) | (t_ctrl_delay << 3) | t2_strb_delay;
expect ni3,     NED,(root_ni << 14) | (0 << 15) | (t_parit_bit << 10) | (t_false_bit << 6) | (t_ctrl_delay << 3) | t3_strb_delay;
expect ni0,     NDLY, (t0_data_delay0) | (t0_data_delay1 << 3) | (t0_data_delay2 << 6) | (t0_data_delay3 << 9) | (t0_data_delay4 << 12) | (t0_data_delay5 << 15) | (t0_data_delay6 << 18) | (t0_data_delay7 << 21) | (t0_data_delay8 << 24) | (t0_data_delay9 << 27);
expect ni1,     NDLY, (t1_data_delay0) | (t1_data_delay1 << 3) | (t1_data_delay2 << 6) | (t1_data_delay3 << 9) | (t1_data_delay4 << 12) | (t1_data_delay5 << 15) | (t1_data_delay6 << 18) | (t1_data_delay7 << 21) | (t1_data_delay8 << 24) | (t1_data_delay9 << 27);
expect ni2,     NDLY, (t2_data_delay0) | (t2_data_delay1 << 3) | (t2_data_delay2 << 6) | (t2_data_delay3 << 9) | (t2_data_delay4 << 12) | (t2_data_delay5 << 15) | (t2_data_delay6 << 18) | (t2_data_delay7 << 21) | (t2_data_delay8 << 24) | (t2_data_delay9 << 27);
expect ni3,     NDLY, (t3_data_delay0) | (t3_data_delay1 << 3) | (t3_data_delay2 << 6) | (t3_data_delay3 << 9) | (t3_data_delay4 << 12) | (t3_data_delay5 << 15) | (t3_data_delay6 << 18) | (t3_data_delay7 << 21) | (t3_data_delay8 << 24) | (t3_data_delay9 << 27);
expect dut, NED,(root_flag << 14) | (oase_mode << 15) | (f_parit_bit << 10) | (f_false_bit << 6) | (f_ctrl_delay << 3) | f_strb_delay;
expect dut, NDLY, (f_data_delay0) | (f_data_delay1 << 3) | (f_data_delay2 << 6) | (f_data_delay3 << 9) | (f_data_delay4 << 12) | (f_data_delay5 << 15) | (f_data_delay6 << 18) | (f_data_delay7 << 21) | (f_data_delay8 << 24) | (f_data_delay9 << 27);