const fpga2 = 1;
const dut   = 2;
const ni0   = 3;
const ni1   = 4;
const ni2   = 5;
const ni3   = 6;

const nchips = 1;  // 1 for single chip, 4 (3+1) for column merger, 5 (4+1) for board merger

restrict (nchips>1)
const nwords =  48;
restrict (nchips==1)
const nwords =  63;
restrict 1

const cnt_mode = 1;
//const simple_test_n  = 0xFFFF; // or 0
const simple_test_n  = 0; // or 0

// oase mode not used anyway!
const oase_mode  = 0; // 1 or 0

const root_flag  = 0; // 1 or 0 for DUT
const root_ni    = 0; // 1 or 0 for the 4 NI chips
//const pasa_merger= 0; // 1 or 0

// all delays can be from 0 to 7

// configuration for DUT -> FPGA readout
// all delays:    min .best. max
const f_ctrl_delay = 4;  // 2 .3. 4 stable, oase mode not used anyway!

const f_data_delay = 3;  // 2..5 stable when strobe delay=2

const f_data_delay0 = f_data_delay; //
const f_data_delay1 = f_data_delay; //
const f_data_delay2 = f_data_delay; //
const f_data_delay3 = f_data_delay; //
const f_data_delay4 = f_data_delay; //  3..6
const f_data_delay5 = f_data_delay; //
const f_data_delay6 = f_data_delay; //
const f_data_delay7 = f_data_delay; //
const f_data_delay8 = f_data_delay; //
const f_data_delay9 = f_data_delay; //

const f_strb_delay = 2; //
const f_false_bit  = 9; // 0..9
const f_parit_bit  = 8; // 0..9

// configuration for 4 TRAPs -> DUT readout
const t_ctrl_delay = 0; // 0..7 egal

t0_data_delay = 3; // 0..5 OK

const t0_data_delay0 = t0_data_delay; // 0 .2. 4
const t0_data_delay1 = t0_data_delay; // 1 .2. 4
const t0_data_delay2 = t0_data_delay; // 0 .2. 4
const t0_data_delay3 = t0_data_delay; // 0 .2. 4
const t0_data_delay4 = t0_data_delay; // 0 .2. 4
const t0_data_delay5 = t0_data_delay; // 0 .2. 4
const t0_data_delay6 = t0_data_delay; // 0 .2. 4
const t0_data_delay7 = t0_data_delay; // 0 .2. 4
const t0_data_delay8 = t0_data_delay; // 0 .2. 4
const t0_data_delay9 = t0_data_delay; // 0 .2. 4

t1_data_delay = 1; // 0..3 OK
const t1_data_delay0 = t1_data_delay; // 0 .1. 1
const t1_data_delay1 = t1_data_delay; // 0 .1. 1
const t1_data_delay2 = t1_data_delay; // 0 .1. 1
const t1_data_delay3 = t1_data_delay; // 0 .1. 1
const t1_data_delay4 = t1_data_delay; // 0 .1. 1
const t1_data_delay5 = t1_data_delay; // 0 .1. 1
const t1_data_delay6 = t1_data_delay; // 0 .1. 1
const t1_data_delay7 = t1_data_delay; // 0 .1. 1
const t1_data_delay8 = t1_data_delay; // 0 .1. 1
const t1_data_delay9 = t1_data_delay; // 0 .1. 1

t2_data_delay = 3; // 0..4 OK
const t2_data_delay0 = t2_data_delay; // 0 .1. 3
const t2_data_delay1 = t2_data_delay; // 0 .1. 3
const t2_data_delay2 = t2_data_delay; // 0 .1. 3
const t2_data_delay3 = t2_data_delay; // 0 .1. 3
const t2_data_delay4 = t2_data_delay; // 0 .1. 3
const t2_data_delay5 = t2_data_delay; // 0 .1. 3
const t2_data_delay6 = t2_data_delay; // 0 .1. 3
const t2_data_delay7 = t2_data_delay; // 0 .1. 3
const t2_data_delay8 = t2_data_delay; // 0 .1. 2
const t2_data_delay9 = t2_data_delay; // 0 .1. 3

t3_data_delay = 1; // 0..4 OK
const t3_data_delay0 = t3_data_delay; // 0 .1. 3
const t3_data_delay1 = t3_data_delay; // 0 .1. 3
const t3_data_delay2 = t3_data_delay; // 1 .1. 2, err(0) < err(3)
const t3_data_delay3 = t3_data_delay; // 0 .1. 2
const t3_data_delay4 = t3_data_delay; // 0 .1. 2
const t3_data_delay5 = t3_data_delay; // 0 .1. 2
const t3_data_delay6 = t3_data_delay; // 0 .1. 2
const t3_data_delay7 = t3_data_delay; // 0 .1. 2
const t3_data_delay8 = t3_data_delay; // 0 .1. 2
const t3_data_delay9 = t3_data_delay; // 0 .1. 2

const t0_strb_delay = 0; // 0
const t1_strb_delay = 0; // 0
const t2_strb_delay = 0; // 0
const t3_strb_delay = 0; // 0

const t0_false_bit  = 1; // 0..9
const t0_parit_bit  = 9; // 0..9

const t1_false_bit  = 6; // 0..9
const t1_parit_bit  = 9; // 0..9

const t2_false_bit  = 0; // 0..9
const t2_parit_bit  = 2; // 0..9

const t3_false_bit  = 4; // 0..9
const t3_parit_bit  = 7; // 0..9