// switch and reset test of DUT
//
//  0       only the local scsn slave
//  1       the local and the other fpga slave
//  2       the local, the other fpga slave and the 4 traps for ni test
//  3       the local and the DUT
//  4       the local, the DUT and the 4 traps for ni test
//  5       the local and the WT
//  6       the local and the 4 traps for ni test
//  7       the local, the other fpga and the WT
//             In cases without DUT in the chain, bit3 of the switch determines
//             the static value to SCSN0 input of DUT (useful for JTAG tests)

include ../scsn_ids.tcs
include src/chip_def.tcs

// reset
write fpga2, scsn_sw, 0;
write fpga2, scsn_sw, 0;
reset
write fpga2, 0x4420
write fpga2, 0x4430

write fpga2, scsn_sw, 1; // fpga2 + fpga1


// Program the DACs for PAS pulses
amplitude = 2000;
timedelta =   50;
pt_delay0 =   24;
pt_delay1 =   48;

// configure dacs
write fpga1, 0x5520, (pt_delay0             << 20) | (0 << 16) |   amplitude
// next time bin
write fpga1, 0x5521, (pt_delay1             << 20) | (1 << 16) |   amplitude

// configure dacs
write fpga1, 0x5522, (pt_delay0+  timedelta << 20) | (0 << 16) | 2*amplitude
// next time bin
write fpga1, 0x5523, (pt_delay1+  timedelta << 20) | (1 << 16) | 2*amplitude

// configure dacs
write fpga1, 0x5524, (pt_delay0+2*timedelta << 20) | (0 << 16) | 3*amplitude
// next time bin
write fpga1, 0x5525, (pt_delay1+2*timedelta << 20) | (1 << 16) | 3*amplitude

// configure dacs
write fpga1, 0x5526, (pt_delay0+3*timedelta << 20) | (0 << 16) | 4*amplitude
// next time bin
write fpga1, 0x5527, (pt_delay1+3*timedelta << 20) | (1 << 16) | 4*amplitude

// configure dacs
write fpga1, 0x5528, (pt_delay0+4*timedelta << 20) | (0 << 16) | 5*amplitude
// next time bin
write fpga1, 0x5529, (pt_delay1+4*timedelta << 20) | (1 << 16) | 5*amplitude

// configure dacs
write fpga1, 0x552A, (pt_delay0+5*timedelta << 20) | (0 << 16) | 6*amplitude
// next time bin
write fpga1, 0x552B, (pt_delay1+5*timedelta << 20) | (1 << 16) | 6*amplitude

// go back to pulse amplitude 0, later
write fpga1, 0x552C, (509 << 20) | (0 << 16) | 0
write fpga1, 0x552D, (511 << 20) | (1 << 16) | 0

// end marker (time 0)
write fpga1, 0x552E, (0 << 20) | (0 << 16) | 0

// configure for start by pretrigger
write fpga1, 0x5500, 4


// Configure the fast ADC

const fastADCcnf = 0x5800+0x0400;
channelADC = 1; // PASA channel 18
channelADC = 2; // PASA channel 17
channelADC = 3; // PASA channel 1
write fpga1, fastADCcnf, 11010000b | channelADC;
expect fpga1, fastADCcnf, 01010000b | channelADC;

// not practical for simulation!
write scsn_sw, 4; // fpga2+dut + 4 TRAPs
reset
nop
nop
// reset test DUT
write  dut,   0x0A00, 0x0BCD
expect dut,   0x0A00, 0x0BCD
write  fpga2, 0x4430, 0; // hardware reset
expect dut,   0x0A00, 0x4050
write  dut,   0x0A00, 0x0BCD
expect dut,   0x0A00, 0x0BCD
reset dut; // scsn reset
expect dut,   0xA00,  0x4050
// reset dut
wait 20;
nop;
// switching the unused pre & clk & ni ports off
write dut, SMMODE, 0xE2

write           CPU0CLK, 0;
write           CPU1CLK, 0;
write           CPU2CLK, 0;
write           CPU3CLK, 0;

write scsn_sw, 3; // fpga2+dut only
//
nop;