;############################################################################## ;# ;# Rudimentary Readout Program for TRAP3 chip ;# ;# Marcus Gutfleisch, V.Angelov ;# Universitaet Heidelberg, Kirchhoff-Institut fuer Physik ;# ;# Heidelberg, 15.10.2004 ;# Heidelberg, 08.12.2004 ;# ;# Stores in DMEM and in NI ;# ;# 0: tracklet cpu0 ;# 1: tracklet cpu1 ;# 2: tracklet cpu2 ;# 3: tracklet cpu3 ;# 4: endmark tracklet ;# 5: endmark tracklet ;# 6: adc[ch=0,timebin=2] & adc[ch=0,timebin=1] & adc[ch=0,timebin=0] & 11 ;# 7: adc[ch=0,timebin=5] & adc[ch=0,timebin=4] & adc[ch=0,timebin=3] & 11 ;# ... ;# n: adc[ch=1,timebin=2] & adc[ch=1,timebin=1] & adc[ch=1,timebin=0] & 10 ;# ... ;# ;# Stores only in DMEM ;# ;# 0x200..0x207: fit register 0..7 of ch=0 ;# 0x208..0x20F: fit register 0..7 of ch=1 ;# ... ;# 0x2A0..0x2A7: fit register 0..7 of ch=20 ;# ;# 0x300..0x303: the automatically selected channels for cpu0..3 ;# f0 & f8 (as 8-bit numbers) for cpu0 ;# f0 & f8 (as 8-bit numbers) for cpu1 ;# f0 & f8 (as 8-bit numbers) for cpu2 ;# f0 & f8 (as 8-bit numbers) for cpu3 ;# ;# Note: the addresses are word addresses (with the appropriate offset can be ;# used to read the data using the scsn. ;# ;############################################################################## #inc ;############################################################################## ;# ;# defines ;# ;############################################################################## #def endsig_tr = c14 ; end signature for tracklet readout #def endsig_rr = c15 ; end signature for raw data readout #def nsamples = c11 ; number of ADC samples per pad #def EventCounter = c12 ; event counter #def ReadoutFlag = c13 ; bit1: NI readout enable ; bit0: SCSN readout enable #def scsn_start = c8 ; start address for storing the data for scsn readout #def EvtCtrGIOAdr = 0xC0C ; Address of Event Counter in GIO #def rstack = r8 ; program counter stack (depth=1) #def rio = r14 ; local I/O auto incrementer register #ifdef cpu0 #def clk_onoff = CPU0SS ; own clock #def clk_onoff_next = CPU1SS ; for delayed start of partner CPU #def LSBdata = 0x03 ; LSBs for data transfer words #def TPCIn = TPCI0 ; Tracklet Test Index Address #def TPPCH_s = 0 ; Tracklet Channel Number for Readout #def TPPCH_e = 3 ; Tracklet Channel Number for Readout #endif #ifdef cpu1 #def clk_onoff = CPU1SS ; own clock #def clk_onoff_next = CPU2SS ; for delayed start of partner CPU #def LSBdata = 0x02 ; LSBs for data transfer words #def TPCIn = TPCI1 ; Tracklet Test Index Address #def TPPCH_s = 4 ; Tracklet Channel Number for Readout #def TPPCH_e = 8 ; Tracklet Channel Number for Readout #endif #ifdef cpu2 #def clk_onoff = CPU2SS ; own clock #def clk_onoff_next = CPU3SS ; for delayed start of partner CPU #def LSBdata = 0x03 ; LSBs for data transfer words #def TPCIn = TPCI2 ; Tracklet Test Index Address #def TPPCH_s = 9 ; Tracklet Channel Number for Readout #def TPPCH_e = 13 ; Tracklet Channel Number for Readout #endif #ifdef cpu3 #def clk_onoff = CPU3SS ; own clock #def LSBdata = 0x02 ; LSBs for data transfer words #def TPCIn = TPCI3 ; Tracklet Test Index Address #def TPPCH_s = 14 ; Tracklet Channel Number for Readout #def TPPCH_e = 20 ; Tracklet Channel Number for Readout #endif ;############################################################################## ;# ;# 0x000: Infinite Loop at Instruction Memory Reset Address ;# ;############################################################################## ORG 0x0; jmpr cc_uncond, 0 nop ;############################################################################## ;# ;# 0x100: Interrupt Clear Jump Address ;# ;############################################################################## ORG 0x100; clr: nop #ifdef cpu0 iext b1111_0101_0000_0000_0010_0000; mov b1111_0101_0000_0000_0010_0000, r1 jmpr cc_busy, 0 sgio r1, SMOFFON ; switch off all NI LVDS cells, clk_prepr, clk_ni (VA), clk_fil ON #endif #ifdef cpu1 mov cmd_ext_clr, r0 jmpr cc_busy, 0 sgio r0, SMCMD ; clear ready (VA) nop #endif #ifdef cpu2 iext TPCBY mov TPCBY, r0 mov 1, r1 sgio r1, r0 #endif jmpr cc_uncond, 0 nop ;############################################################################## ;# ;# 0x200: Interrupt Tracklet Processing Jump Address ;# ;############################################################################## ORG 0x200; acq: nop #ifdef cpu0 mov b0000_0010_0000, r1 jmpr cc_busy, 0 sgio r1, SMOFF ; switch off clk_fil #endif ; store the automatically selected channel in GRF #ifdef cpu0 mov f0, g0 shl 8, g0, g0 or f8, g0, g0 #endif #ifdef cpu1 mov f0, g1 shl 8, g1, g1 or f8, g1, g1 #endif #ifdef cpu2 mov f0, g2 shl 8, g2, g2 or f8, g2, g2 #endif #ifdef cpu3 mov f0, g3 shl 8, g3, g3 or f8, g3, g3 #endif mov 30, r0 delay: ; wait a while to make sure that GSM and sub r0, c1, r0 ; NI are ready for transmission and state jmp cc_nzero, delay ; transition. ; mov endsig_tr r0 ; load Tracklet End Signature mov scsn_start r0 ; load start addres for scsn readout ; store in DMEM the same #ifdef cpu0 sra r0, 0 #endif #ifdef cpu1 sra r0, 4 #endif #ifdef cpu2 sra r0, 8 mov 0, r1 iext TPCBY sgio r1,TPCBY ; switch to bypass the selection logic #endif #ifdef cpu3 sra r0, 12 mov endsig_tr r2 ; load Tracklet End Signature swp r2, r2 mov endsig_tr r1 ; load Tracklet End Signature or r2, r1, r2 sra r2 16 nop sra r2 20 #endif spio r0 NODP ; Send Tracklet data via NI jmpr cc_uncond 0 nop ;############################################################################## ;# ;# 0x400: Interrupt Raw Data Transmission Jump Address ;# ;############################################################################## ORG 0x400 raw: nop #ifdef cpu0 mov cmd_CPU_done r0 ; CPU0 indicates upcoming data transmission sgio r0 SMCMD; jmp cc_uncond, continue ; CPU0 fills FIFO immediately #endif mov 0, r0 ; switch off own clock because sgio r0, clk_onoff; ; CPU2 and CPU3 are filling their FIFOs delayed. jmpr cc_busy, 0 ; They will be started by CPU0 and CPU 1 later. nop nop nop nop nop continue: ;############################################## ;# Store Start addresses for SCSN transfer via DMEM ;############################################## mov scsn_start, r15 ;############################################## ;# NI transfer event header (CPU0 only) ;############################################## mov LSBdata, r7 ; pass the two LSBs for data transmission iext 0xFFFF ; high word mask for Channel switching mov 0xFFFF, r11 swp r11, r11 run_tmsn: ;############################################## ;# NI&SCSN transfer 1st channel ;############################################## mov EBR0, rio ; address in LIO of the event buffer mov nsamples,r1 ; number of samples to read (done above) mvpcr +2, rstack jmp cc_uncond, ChTML; ;############################################## ;# NI&SCSN transfer 2nd channel ;############################################## mov EBR1, rio ; address in LIO of the event buffer mov nsamples,r1 ; number of samples to read mvpcr +2, rstack jmp cc_uncond, ChTML; ;############################################## ;# NI&SCSN transfer 3rd channel ;############################################## mov EBR2, rio ; address in LIO of the event buffer mov nsamples,r1 ; number of samples to read mvpcr +2, rstack jmp cc_uncond, ChTML; ;############################################## ;# NI&SCSN transfer 4th channel ;############################################## mov EBR3, rio ; address in LIO of the event buffer mov nsamples,r1 ; number of samples to read mvpcr +2, rstack jmp cc_uncond, ChTML; ;############################################## ;# NI&SCSN transfer 5th channel ;############################################## mov EBR4, rio ; address in LIO of the event buffer mov nsamples,r1 ; number of samples to read mvpcr +2, rstack jmp cc_uncond, ChTML; ;############################################## ;# NI&SCSN transfer 6th channel (CPU3 only) ;############################################## #ifdef cpu3 mov EBR5, rio ; address in LIO of the event buffer mov nsamples,r1 ; number of samples to read mvpcr +2, rstack jmp cc_uncond, ChTML; mov endsig_rr r0 sra+ r0 nop sra+ r0 #endif; complete_ni_tmsn: ; read the fit register and store in DMEM mov TPPCH_s, r0 ; Set Preprocessor Channel to readout iext TPCIn sgio r0, TPCIn shl 5, r0, r15 ; start addres = channel * 8 (fit registers) * 4 (byte address) mov 0x800, r1 add r1, r15, r15 read_frf: jmpr cc_busy, 0 nop nop nop mov f8, r1 sra+ r1 mov f9, r1 sra+ r1 mov f10,r1 sra+ r1 mov f11,r1 sra+ r1 mov f12,r1 sra+ r1 mov f13,r1 sra+ r1 mov f14,r1 sra+ r1 mov f15,r1 sra+ r1 add r0, c1, r0 iext TPCIn sgio r0, TPCIn cmp r0, TPPCH_e jmp cc_leu, read_frf mov 0xC00, r15 shl 2, c5, r1 add r1, r15, r15 #ifdef cpu0 mov g0, r0 #endif #ifdef cpu1 mov g1, r0 #endif #ifdef cpu2 mov g2, r0 #endif #ifdef cpu3 mov g3, r0 #endif sra+ r0 ;############################################## ;# CPU0, CPU1: start CPU2 and CPU3 for delayed transfer ;############################################## mov 1, r1 jmpr cc_busy, 0 #ifdef cpu3 nop #else sgio r1 clk_onoff_next #endif ;############################################## ;# CPU3: Increment Event Counter ;############################################## #ifdef cpu3 mov EventCounter, r0 add r0, c1, r0 iext 0x1FFFFF mov 0x1FFFFF, r1 and r1, r0, r0 jmp cc_nzero, EvtCtrOK mov 10, r0 EvtCtrOK: jmpr cc_busy, 0 sgio r0 EvtCtrGIOAdr #endif ;############################################## ;# NI&SCSN transfer end marker ;############################################## mov endsig_rr r0 spio r0 NODP ;############################################## ;# switch off own clock after transfer ;############################################## coff: mov 0, r0 jmpr cc_busy, 0 sgio r0 clk_onoff jmpr cc_busy, 0 nop nop nop nop nop nop nop jmp cc_uncond, coff nop ;############################################################################## ;# ;# NI transmission of one channel ;# ;############################################################################## ;# ;# Interface: ;# ;# Input: r14 start address of event buffer in LIO ;# r1 number of time bins to read (>0, multiple of three) ;# r7 OR mask for the 32 bit word ;# ;# Output: sends data to the NI output port ;# Modifies: r3, r4, r5, r14, r1 (0) ;# ;############################################################################## ;############################################## ;# BEGIN data transfer loop ChTML: ;############################################## lpio+ r3 ; initial read has to be done twice due to lpio+ r3 ; memory delay (synchronous read) lpio+ r4 lpio rio, r5 shl 10, r5, r5 ; combine three 10 bit data words or r5, r4, r5 ; to one (32=10+10+10+2) bit data word shl 10, r5, r5 or r5, r3, r5 shl 2, r5, r5 or r5, r7, r5 ; set the two LSBs spio r5, NODP ; write to NI sra+ r5 ; write to DMEM for SCSN reading sub r1, c3, r1 ; decrease number of words to read jmp cc_gtu, ChTML ; loop xor r7, c1, r7 jmp cc_uncond, rstack ; return from subroutine ;############################################## ;# END data transfer loop ;############################################## nop