include src/chip_def_rob.tcs

const CPUGCONST=0x0C04; // all cpus
const C12CPUA=CPUGCONST+0; // c15
const C15CPUA=CPUGCONST+3; // c15

const irq_tst = 1;
const irq_msk = (1 << irq_tst);
// start address IRQ1 - tst

write CPU0CLK, 0
write CPU1CLK, 0
write CPU2CLK, 0
write CPU3CLK, 0
write cdev, CPU3CLK, 2

write IA3+irq_tst, 0;
// enable hardw IRQ tst
write IRQHW0, 0
write IRQHW1, 0
write IRQHW2, 0
write IRQHW3, 0
write cdev, IRQHW3, irq_msk
// set high level IRQ tst
write IRQHL0, 0
write IRQHL1, 0
write IRQHL2, 0
write IRQHL3, 0
write cdev, IRQHL3, irq_msk

write NICLK, 2
write NIICE, 1;
write NIOCE, 1;

//write cdev, SMMODE, 0xF0E2

write C15CPUA, nloops
write C12CPUA, 0