// switch off cpu1,2,3
//write CPU0CLK, 0x1
write CPU1CLK, 0x0
write CPU2CLK, 0x0
write CPU3CLK, 0x0
// cpu0,1,2,3
const irq_tst = 1;
const irq_msk = (1 << irq_tst);
// start address IRQ1 - tst
write IA0+irq_tst, 0;
write IA1+irq_tst, 0;
write IA2+irq_tst, 0;
write IA3+irq_tst, 0;
// enable hardw IRQ tst
write IRQHW0, irq_msk
write IRQHW1, irq_msk
write IRQHW2, irq_msk
write IRQHW3, irq_msk
// set high level IRQ tst
write IRQHL0, irq_msk
write IRQHL1, irq_msk
write IRQHL2, irq_msk
write IRQHL3, irq_msk
// overwrite, the CONSTANTS representing the errors encountered
write 0xF000, 0xABCD
write 0xF001, 0xABCD
write 0xF002, 0xABCD
write 0xF003, 0xABCD
write 0xF004, 0xABCD
write 0xF005, 0xABCD
write 0xF006, 0xABCD
write 0xF007, 0xABCD
write 0xF008, 0xABCD
write 0xF009, 0xABCD
write 0xF00A, 0xABCD
write 0xF00B, 0xABCD
write 0xF00C, 0xABCD
write 0xF00D, 0xABCD
write 0xF00E, 0xABCD
write 0xF00F, 0xABCD
write 0xF020, 0xABCD
write 0xF021, 0xABCD
write 0xF022, 0xABCD
write 0xF023, 0xABCD
write 0xF024, 0xABCD
write 0xF025, 0xABCD
write 0xF026, 0xABCD
write 0xF027, 0xABCD
write 0xF028, 0xABCD
write 0xF029, 0xABCD
write 0xF02A, 0xABCD
write 0xF02B, 0xABCD
write 0xF02C, 0xABCD
write 0xF02D, 0xABCD
write 0xF02E, 0xABCD
write 0xF02F, 0xABCD
write 0xF040, 0xABCD
write 0xF041, 0xABCD
write 0xF042, 0xABCD
write 0xF043, 0xABCD
write 0xF044, 0xABCD
write 0xF045, 0xABCD
write 0xF046, 0xABCD
write 0xF047, 0xABCD
write 0xF048, 0xABCD
write 0xF049, 0xABCD
write 0xF04A, 0xABCD
write 0xF04B, 0xABCD
write 0xF04C, 0xABCD
write 0xF04D, 0xABCD
write 0xF04E, 0xABCD
write 0xF04F, 0xABCD
write 0xF060, 0xABCD
write 0xF061, 0xABCD
write 0xF062, 0xABCD
write 0xF063, 0xABCD
write 0xF064, 0xABCD
write 0xF065, 0xABCD
write 0xF066, 0xABCD
write 0xF067, 0xABCD
write 0xF068, 0xABCD
write 0xF069, 0xABCD
write 0xF06A, 0xABCD
write 0xF06B, 0xABCD
write 0xF06C, 0xABCD
write 0xF06D, 0xABCD
write 0xF06E, 0xABCD
write 0xF06F, 0xABCD