; IMEM testing routine. Performs full test of IMEMn by cpu(n-1). ; The number of the errors, counted by cpu(n) is stored in the location 0xF00n of the D-bank ; DEFINITIONS, USED IN THE PROGRAM CODE: #def work=PRF[1] ; register for current operations (CO) #def rdata=PRF[2] ; data red by test_programs and CO #def tdata=PRF[3] ; test_vector to be writen #def errnum=PRF[4] ; contains the number of err_ors #def return1=PRF[5] ; return address (at first level) #def return2=PRF[6] ; return address (at second level) #def return3=PRF[7] ; return address (at third level) #def tdgen=PRF[8] ; test data generator code label #def itdgen=PRF[9] ; init tdgen code label #def psrmask=PRF[10] ; mask for test_vector #def bitnum=PRF[12] ; =32 minus the number of bits of the tested area ; prf11 and prf13 are used inside the testing routine #def ioaddr=PRF[14] ; contains the autoincrementing address of I/O operations through GIO #def errstore=PRF[15] ; autoincrement address for RAM-access #def firstaddress=grf[1] ; first address of the tested area #def lastaddress=grf[2] ; last address of the tested area #def MEMRW=0xD000 ; the address of the register, controling R/W operations of IMEM/DMEMs #def IAFIRST=0xE000 ; first address of IMEM #def IADEND =0xEFFF ; last address of IMEM ;#def DAFRSTG=0xE000 ; first address of DMEM via GIO ;#def DADENDG=0xE3FF ; last address of DMEM via GIO ;#def DAFIRST=0x0000 ; first address of DMEM as RAM ;#def DADEND =0x0FFC ; last address of DMEM as RAM #def DBFST=0xF000 ; first address of DBANK (trap3) #def DBEND=0xF0FF ; last address of DBANK (trap3) ; masks of certain length #def BITMASK24=0x0FFFFFF #def BITMASK32=0xFFFFFFFF #def BITMASK12=0x00000FFF #def BITMASK13=0x00001FFF #def IMMTST0=b0010_01_1 #def IMMTRS0=b0010_11_1 #def ITSCLK0=0xA20 #def NXTCLK0=0xA22 #def IMMTST1=b0100_10_1 #def IMMTRS1=b0100_00_1 #def ITSCLK1=0xA22 #def NXTCLK1=0xA24 #def IMMTST2=b1000_11_1 #def IMMTRS2=b1000_01_1 #def ITSCLK2=0xA24 #def NXTCLK2=0xA26 #def IMMTST3=b0001_00_1 #def IMMTRS3=b0001_10_1 #def ITSCLK3=0xA26 #def NXTCLK3=0xA20 nop iext 0xF000 mov 0xF000 r14 add r14 c5 r14 iext 0xA5A5A5A5 mov 0xA5A5A5A5 r0 jmpr cc_busy 0 sgio+ r0 mov c0 errnum ; clear the err_or_counter ; in readout board, only some chips start test ... mov c5 work ; in 0x3055 is the configuration bit, if cpu0 will run or not cmp work c0 cmp work c0 jmp cc_neq cp1 ; branch to cp1, if acting is not CPU0 ; cpu0 task here iext 0x3055 ; following code is option mov 0x3055 r14 ; to make test routine not to run lgio 0 r14 ; if in configuring .tcs file jmpr cc_busy 0 ; in 0x3055 we have 1, the test lpio 0x300 r0 ; will run jmpr cc_busy 0 ; otherwise - not ; this option may be usefull in ROB and r0 c1 r0 ; if we want this test running cmp r0 c1 ; in some chips only cmp r0 c1 jmp cc_zero go ; mov c1 r1 ; jmpr cc_busy 0 ; sgio r1 r14 jmpr cc_busy 0 mov c0 r0 sgio r0 ITSCLK0 mov 0x12 r0 sgio r0 0xA04 jmpr cc_uncond 0 go: mov c0 r1 ; when running, the 0x3055 is cleared jmpr cc_busy 0 ; next pretrigger will make the chip not to run the test sgio r1 r14 mov IMMTST0 work ; initiate for R/W test of IMEM1 jmpr cc_busy 0 iext MEMRW sgio work MEMRW iext IAFIRST ; initialyzing the IMEM1 mov IAFIRST r14 iext IADEND mov IADEND r0 mov c0 r1 sgio+ r1 jmpr cc_busy 0 cmp r14 r0 jmpr cc_ltu -3 iext 0xD011 sgio r1 0xD011 ; clear HCNTL1 mvpcr +2 return1 ; call inittesting routine - iintst jmp cc_uncond iintst mvpcr +2 return1 ; call testing routine - cltst jmp cc_uncond cltst iext 0xF000 mov 0xF000 work add work c5 work sgio errnum work ; subroutine transfering previos IMEM into next IMEM mov IMMTRS0 work mvpcr +2 return1 jmp cc_uncond trsf ; end copying the IMEM ; turn_on next cpu clock mov c1 work jmpr cc_busy 0 sgio work NXTCLK0 jmpr cc_busy 0 mov c0 work sgio work ITSCLK0 jmpr cc_uncond 0 ; ... and stops itself cp1: mov c5 work cmp work c1 cmp work c1 jmp cc_nzero cp2 mov IMMTST1 work ; initiate for R/W test of IMEM2 jmpr cc_busy 0 iext MEMRW sgio work MEMRW iext IAFIRST ; initialyzing the IMEM2 mov IAFIRST r14 iext IADEND mov IADEND r0 mov c0 r1 sgio+ r1 jmpr cc_busy 0 cmp r14 r0 jmpr cc_ltu -3 iext 0xD012 sgio r1 0xD012 ; clear HCNTL2 mvpcr +2 return1 ; call inittesting routine - iintst jmp cc_uncond iintst mvpcr +2 return1 ; call testing routine - cltst jmp cc_uncond cltst iext 0xF000 mov 0xF000 work add work c5 work sgio errnum work ; subroutine transfering previos IMEM into next IMEM mov IMMTRS1 work mvpcr +2 return1 jmp cc_uncond trsf ; end copying the IMEM ; turn_on next cpu clock mov c1 work jmpr cc_busy 0 sgio work NXTCLK1 jmpr cc_busy 0 mov c0 work sgio work ITSCLK1 jmpr cc_uncond 0 ; ... and stops itself cp2: mov c5 work cmp work c2 cmp work c2 jmp cc_nzero cp3 mov IMMTST2 work ; initiate for R/W test of IMEM3 jmpr cc_busy 0 iext MEMRW sgio work MEMRW iext IAFIRST ; initialyzing the IMEM3 mov IAFIRST r14 iext IADEND mov IADEND r0 mov c0 r1 sgio+ r1 jmpr cc_busy 0 cmp r14 r0 jmpr cc_ltu -3 iext 0xD013 sgio r1 0xD013 ; clear HCNTL3 mvpcr +2 return1 ; call inittesting routine - iintst jmp cc_uncond iintst mvpcr +2 return1 ; call testing routine - cltst jmp cc_uncond cltst iext 0xF000 mov 0xF000 work add work c5 work sgio errnum work ; subroutine transfering previos IMEM into next IMEM mov IMMTRS2 work mvpcr +2 return1 jmp cc_uncond trsf ; end copying the IMEM ; turn_on next cpu clock mov c1 work jmpr cc_busy 0 sgio work NXTCLK2 jmpr cc_busy 0 mov c0 work sgio work ITSCLK2 jmpr cc_uncond 0 ; ... and stops itself cp3: mov IMMTST3 work ; initiate for R/W test of IMEM0 jmpr cc_busy 0 iext MEMRW sgio work MEMRW iext IAFIRST ; initialyzing the IMEM0 mov IAFIRST r14 iext IADEND mov IADEND r0 mov c0 r1 sgio+ r1 jmpr cc_busy 0 cmp r14 r0 jmpr cc_ltu -3 iext 0xD010 sgio r1 0xD010 ; clear HCNTL0 mvpcr +2 return1 ; call inittesting routine - iintst jmp cc_uncond iintst mvpcr +2 return1 ; call testing routine - cltst jmp cc_uncond cltst iext 0xF000 mov 0xF000 work add work c5 work sgio errnum work ; subroutine transfering previos IMEM into next IMEM mov IMMTRS3 work mvpcr +2 return1 jmp cc_uncond trsf ; end copying the IMEM lp: jmpr cc_busy 0 ; ... transition into ... ; mov c0 work ; sgio work 0xA21 ; jmpr cc_busy 0 ; mov 0x7 work ; sgio work NXTCLK3 jmpr cc_busy 0 mov c0 work sgio work ITSCLK3 mov 0x012 work sgio work 0xA04 ; ... low power mode end: jmp cc_uncond end ; END OF THE ENTIRE PROGRAM ; SUBROUTINES BELOW ; ROUTINE, TRANSFERING IMEM_(n+3)_mod_4 INTO IMEM_(n+1)_mod_4 trsf: jmpr cc_busy 0 iext MEMRW sgio work MEMRW iext IAFIRST mov IAFIRST ioaddr ; init ioaddr mov length work add work ioaddr work ; work = end program address+1 add work c1 work wk: jmpr cc_busy 0 ; writing in IMEM cycle lgio 0 ioaddr jmpr cc_busy 0 lpio 0x300 rdata sgio+ rdata cmp ioaddr work cmp ioaddr work jmp cc_nzero wk ; end writing et iext IADEND ; the end address of IMEM - 0xEFFF mov IADEND ioaddr sub ioaddr c1 ioaddr jmpr cc_busy 0 lgio 0 ioaddr jmpr cc_busy 0 lpio 0x300 rdata sgio rdata ioaddr ; also should be copied onto IMEM. jmp cc_uncond return1 ; END THE ROUTINE, TRANSFERING IMEM_(n+3)_mod_4 INTO IMEM_(n+1)_mod_4 . ; INITIALIZATION OF THE IMEM TESTING ROUTINE iintst: iext BITMASK24 ; this parameter depends on the size of test_vector mov BITMASK24 psrmask mov 8 bitnum iext IAFIRST mov IAFIRST firstaddress iext IADEND mov IADEND lastaddress jmp cc_uncond return1 ; END INITIALIZATION ; BEGIN THE TESTING ROUTINE (uses testing subroutine) cltst: mov 1 r11 mov 1 r13 nt: mov wlk0 tdgen ; call walking 0 test_routine mov iwlk0 itdgen mvpcr +2 return2 jmp cc_uncond tstgio mov wlk1 tdgen ; call walking 1 test_routine mov iwlk1 itdgen ; mvpcr +2 return2 jmp cc_uncond tstgio mov psr tdgen ; call pseudo random vector test_routine mov ipsr itdgen mvpcr +2 return2 jmp cc_uncond tstgio add r13 c3 r13 ; next initial vectors for all shl 1 r11 r11 ; testing routines jmp cc_carry return1 mov bitnum work mov 15 rdata mov r11 r0 cmp rdata bitnum cmp rdata bitnum jmpr cc_ncarry 3 shl 15 r0 r0 sub work rdata work shlt work r0 ; if MSB of the current register tested is set - stop! jmp cc_ncarry nt jmp cc_uncond return1 ; END OF THE TESTING ROUTINE ; BEGIN OF THE SUBROUTINE (used by testing routine above) ; rolls all addresses and tests by w/r through GIO tstgio: mvpcr +2 return3 jmp cc_uncond itdgen ; go to init the test data gen ; BEGIN WRITING THE TEST PATTERN mov firstaddress ioaddr wd: jmpr cc_busy 0 sgio+ tdata ; writing the test data in current address mvpcr +2 return3 ; runs the generator returning test vector jmp cc_uncond tdgen cmp ioaddr lastaddress ;IADEND ; is the last address reached? cmp ioaddr lastaddress ;IADEND ; is the last address reached? jmp cc_carry wd ; if yes: ; BEGIN COMPARING PART OF CODE mov firstaddress ioaddr mvpcr +2 return3 jmp cc_uncond itdgen ; and go to init for testing wc: jmpr cc_busy 0 ; here is the body of the cycle lgio+ 0 ; reading each address and jmpr cc_busy 0 ; comparing the result with lpio 0x300 rdata ; data stored befor cmp rdata tdata ; cmp rdata tdata ; jmp cc_zero noerr ; if err_or detected add errnum c1 errnum ; errnum is incremented cmp errnum 0x40 ; first 63 errors detected by each cpu jmp cc_geu noerr ; lead to store the corresponding IMEM address in DBANK. mov 0x3F work ; F004-F042 - test of IMEM1 mul32 work c5 work ; F043-F081 - test of IMEM2 iext 0xF003 ; F082-F0C0 - test of IMEM3 mov 0xF003 g4 ; F0C1-F0FF - test of IMEM0 add work g4 work add work errnum work sgio ioaddr work noerr: mvpcr +2 return3 jmp cc_uncond tdgen ; get next test_data to compare with cmp ioaddr lastaddress ; is tne last address tested? cmp ioaddr lastaddress ; is tne last address tested? jmp cc_carry wc ; if not go to wc jmp cc_uncond return2 ; prepares the next data - walking 1 wlk1: shl 1 tdata tdata and tdata psrmask tdata jmp cc_nzero return3 mov c1 tdata jmp cc_uncond return3 ; end of walking 1 ; prepares the next data - walking 0 wlk0: com tdata tdata shl 1 tdata tdata and tdata psrmask tdata jmpr cc_nzero +2 mov 1 tdata com tdata tdata and tdata psrmask tdata jmp cc_uncond return3 ; end of walking 0 ; prepares the next data by pseudo random generator psr: lpio 0x202 tdata and tdata psrmask tdata jmp cc_uncond return3 ; end random generator ; init walking 1 iwlk1: mov r11 tdata jmp cc_uncond return3 ; init walking 0 iwlk0: com r11 tdata and tdata psrmask tdata jmp cc_uncond return3 ; init psr ;#ifdef trap3 ipsr: mov b1_0_0_00_01_10111 tdata ;#else ;ipsr: mov b1_0_0_00_01_1111 tdata ;#endif mov 31 r0 sub r0 bitnum r0 ;#ifdef trap3 ;#else ; cmp r0 16 ; jmpr cc_carry 2 ; mov 15 r0 ;#endif or tdata r0 tdata spio tdata 0x201 mov r13 tdata spio tdata 0x200 nop nop lpio 0x202 tdata jmp cc_uncond return3 length: nop;