// cpu0,1,2,3
const irq_tst = 1;
const irq_msk = (1 << irq_tst);
// start address IRQ1 - tst
write NICLK      , 0
write FILCLK     , 0
write PRECLK     , 0
write ADCEN      , 0
write NIODE      , 0
write NIIDE      , 0
write NIICE      , 0
write NIOCE      , 0
write IA0+irq_tst, 0x100;
write IA1+irq_tst, 0x100;
write IA2+irq_tst, 0x100;
write IA3+irq_tst, 0x100;
// enable hardw IRQ tst
write IRQHW0, irq_msk
write IRQHW1, irq_msk
write IRQHW2, irq_msk
write IRQHW3, irq_msk
// set high level IRQ tst
write IRQHL0, irq_msk
write IRQHL1, irq_msk
write IRQHL2, irq_msk
write IRQHL3, irq_msk

// overwrite, the DBANK memory
write 0xF000, 0xC0
write 0xF001, 0xC1
write 0xF002, 0xC2
write 0xF003, 0xC3