// switch off cpu1,2,3
//write CPU0CLK, 0x1
write CPU1CLK, 0x0
write CPU2CLK, 0x0
write CPU3CLK, 0x0
// cpu0,1,2,3
const irq_tst = 1
const irq_msk = (1 << irq_tst)
// start address IRQ1 - tst
write IA0+irq_tst, 0
write IA1+irq_tst, 0
write IA2+irq_tst, 0
write IA3+irq_tst, 0
// enable hardw IRQ tst
write IRQHW0, irq_msk
write IRQHW1, irq_msk
write IRQHW2, irq_msk
write IRQHW3, irq_msk
// set high level IRQ tst
write IRQHL0, irq_msk
write IRQHL1, irq_msk
write IRQHL2, irq_msk
write IRQHL3, irq_msk
// overwrite, the CONSTANTS representing the errors encountered
write 0xF000, 0xABCD
write 0xF001, 0xABCD
write 0xF002, 0xABCD
write 0xF003, 0xABCD
write 0xF004, 0xABCD
write 0xF005, 0xABCD
write 0xF006, 0xABCD
write 0xF007, 0xABCD
write 0xF008, 0xABCD
write 0xF009, 0xABCD
write 0xF00A, 0xABCD
write 0xF00B, 0xABCD
write 0xF00C, 0xABCD
write 0xF00D, 0xABCD
write 0xF00E, 0xABCD
write 0xF00F, 0xABCD
write 0xF010, 0xABCD
write 0xF011, 0xABCD
write 0xF012, 0xABCD
write 0xF013, 0xABCD
write 0xF014, 0xABCD
write 0xF015, 0xABCD
write 0xF016, 0xABCD
write 0xF017, 0xABCD
write 0xF018, 0xABCD
write 0xF019, 0xABCD
write 0xF01A, 0xABCD
write 0xF01B, 0xABCD
write 0xF01C, 0xABCD
write 0xF01D, 0xABCD
write 0xF01E, 0xABCD
write 0xF01F, 0xABCD