// Interrupt numbers
const IRQ_NI  = 8;
const IRQ_TM  = 6;
const IRQ_CLR = 0;
const IRQ_ACQ = 2;
const IRQ_RAW = 4;
const IRQ_TST = 1;

// Base addresses of the programmable constants
const CPU0CONST=0x0C00; // cpu0
const CPU1CONST=0x0C08; // cpu1
const CPU2CONST=0x0C10; // cpu2
const CPU3CONST=0x0C18; // cpu3
const CPUGCONST=0x0C04; // all cpus

// Addresses of all programmable constants in the GIO space
const C08CPU0=CPU0CONST+0; // c8  of cpu0
const C09CPU0=CPU0CONST+1; // c9  of cpu0
const C10CPU0=CPU0CONST+2; // c10 of cpu0
const C11CPU0=CPU0CONST+3; // c11 of cpu0

const C08CPU1=CPU1CONST+0; // c8  of cpu1
const C09CPU1=CPU1CONST+1; // c9  of cpu1
const C10CPU1=CPU1CONST+2; // c10 of cpu1
const C11CPU1=CPU1CONST+3; // c11 of cpu1

const C08CPU2=CPU2CONST+0; // c8  of cpu2
const C09CPU2=CPU2CONST+1; // c9  of cpu2
const C10CPU2=CPU2CONST+2; // c10 of cpu2
const C11CPU2=CPU2CONST+3; // c11 of cpu2

const C08CPU3=CPU3CONST+0; // c8  of cpu3
const C09CPU3=CPU3CONST+1; // c9  of cpu3
const C10CPU3=CPU3CONST+2; // c10 of cpu3
const C11CPU3=CPU3CONST+3; // c11 of cpu3

const C12CPUA=CPUGCONST+0; // c12
const C13CPUA=CPUGCONST+1; // c13
const C14CPUA=CPUGCONST+2; // c14
const C15CPUA=CPUGCONST+3; // c15

// switch off cpu1,2,3
write CPU1CLK, 0x0
write CPU2CLK, 0x0
write CPU3CLK, 0x0
//write NIOCE, 0
const irq_msk = (1 << IRQ_TST);
// start address IRQ1 - tst
write IA0+IRQ_TST, 0;
// enable hardw IRQ tst
write IRQHW0, irq_msk
// set high level IRQ tst
write IRQHL0, irq_msk


saddr = 0xF000;
write C11CPU0, saddr;
addr    = 0xF020;       // start address to expand the block
nwords  = 3;            // number of words
widthM1 = 31;           // 32 bit words
se      = 0;            // no sign extension (not implemented)
stepM1  = 0;            // step 1
write saddr  , (0 << 31) | (addr << 15) | (nwords << 7) | (widthM1 << 2) | (se << 1) | stepM1;
write saddr+1,  0x010ABC
write saddr+2,  0x020ABC
write saddr+3,  0x030ABC


// test 16 bit case
addr = addr + nwords
widthM1 = 15;           // 32 bit words
write saddr+4, (0 << 31) | (addr << 15) | (nwords << 7) | (widthM1 << 2) | (se << 1) | stepM1;
write saddr+5,  0x010A | (0x020A << 16)
write saddr+6,  0x030A

// test 8 bit case
addr = addr + nwords
nwords = 5
widthM1 = 7;           // 32 bit words
write saddr+7, (0 << 31) | (addr << 15) | (nwords << 7) | (widthM1 << 2) | (se << 1) | stepM1;
write saddr+8,  0x10 | (0x20 << 8) | (0x30 << 16) | (0x40 << 24)
write saddr+9,  0x50

// test single case
addr = 0xA00
write saddr+10, (1 << 31) | (addr << 17) | 0xACE;
addr = 0xA01
write saddr+11, (1 << 31) | (addr << 17) | 0xAFE;

write saddr+12,  0;      // end

addr = 0xF020
restrict 0
// 32 bit
write addr  , 0xDEADAFFE
write addr+1, 0xDEADFACE
write addr+2, 0xFACEAFFE
// 16 bit
write addr+3, 0xDEAD
write addr+4, 0x20b
write addr+5, 0xAFFE
// 8 bit
write addr+6, 0xDE
write addr+7, 0x20
write addr+8, 0x30
write addr+9, 0x40
write addr+10, 0x16
restrict 1
write 0xA00, 0xACE
write 0xA01, 0xAFE
write addr+11, 0xDEAD