%
% Responsible: Ken, StefanS, Joerg, Tobias, Rainer, Jochen 
%

\chapter{Pre-Trigger System}

\newcommand{\cbb}{CB-B\xspace}

\begin{figure}[bth]
\begin{center}
\includegraphics*[width=12cm]{figs/oyama/PreTrigger-Concept.pdf}
\end{center}
\caption{\label{fig:pretrigger-concept}
Conceptual design of the pre-trigger system.
}
\end{figure}

The main functions of the pre-trigger system is to produce very early trigger inside the L3 magnet and 
to distribute trigger and clock to all 540 TRD supermodules.
Since pre-trigger wakes pre-processor part of TRAPs up, it should arrive before the Level-0 trigger.

As shown in the conceptual drawing in \autoref{fig:pretrigger-concept},
the pre-trigger is produced using signals from various detectors such as V0, T0, TOF, and ACORDE which
are main beam interaction or cosmic trigger detectors contributing to Level-0 trigger decisions by \acf{CTP}.
The pre-trigger system should receive TTC signal from the \ac{CTP}
then pre-trigger signals are combined with the TTC signal and sent to all TRD chambers.
TTC signal includes also higher level trigger information such as Level-0, Level-1, and Level-2.
Also TRD specific fast control commands are sent by pre-trigger to the chambers for example
to command align ADC phase and comman to put all TRAP chips into a same state at the same time.

Since all contributing detectors to pre-trigger are distributed in large volume in the L3 magnet,
the pre-trigger system also consists of distributed boxes.
Some of the boxes are placed at the vicinity of detectors and there are also boxes centrally 
control distributed boxes.

In this chapter, first overview of how pre-trigger system is designed is given.
Then detailed descriptions of individual components, powering scheme, and test results are presented.


\section{Overview of Pre-trigger System}

\begin{figure}[h]
\begin{center}
\includegraphics*[width=23cm,angle=90]{figs/oyama/SBarrange-11.pdf}
\end{center}
\caption{\label{fig:pretrigger-sbarrange}
Comprehensive schematic view of pre-trigger system.
}
\end{figure}

~\autoref{fig:pretrigger-sbarrange} shows schematic overview of the pre-trigger system together
with subsystems of ALICE connected to the pre-trigger system.
The view of the schematic is subdivided into 3 areas which are ``outside magnet'' on top,
A (RB24) area in the left, and C (RB26) area in the right. A nad C area are inside L3 magnet
in this case (not ALICE general).
All sub-components in A side is given suffix ``-A'', and same for C-side with suffix ``-C''
except for few components which function is not specially for A or C side.

In ~\autoref{fig:pretrigger-sbarrange}, the contributing detectors for pre-trigger are T0-A and V0-A (left side),
T0-C and V0-C (right side), and TOF in the center.
Detector signals of T0 and V0 detectors (phototube signals) are injected into satellite pre-trigger
boxes which is called \acf{FEB}.
Inside \ac{FEB} there are pre-amplifiers suitable for the T0 and V0 detectors, and also FPGA utilized for
pre-trigger system.
On the other hand, T0 and V0 detectors have their own front-end electronics outside the magnet (``V0-A FEE'', ``T0-A FEE'', etc).
Therefore \ac{FEB} has output to thos FEE's, and also output for the pre-trigger.
There are in total 10 \ac{FEB}s to accept all T0 and V0 detector signals.

ALICE TOF detector has implemnted the pre-trigger element output for TRD.
There are 18 TOF super-modules and individual super-module is subdividened to 4 quadrants.
From each quadrant there are 2 CAT-6 cables are routed to pre-trigger system.
Total number of cables from TOF is therefore 144.

Pre-trigger signals from 10 FEBs are collected to \acf{CB}s.
CB-A is sitting close to 5 FEB boxes in A-side, and CB-C is for C-side.
In each CB-A and CB-C boxes, sub-decision of the pre-trigger is performed.
Also CB-A and CB-C are responsible for clock distribution for FEBs and configuration of FEBs
such as FPGA design download and setting discriminator threshold, etc.

CB-A and CB-C sends trigger contribution to CB-B which is sitting actually
{\bf B}elow the back-frame.
CB-B collects information from CB-A, CB-C, and TOF, then make final pre-trigger decision.
Then pre-trigger signal is sent to TRD using optical fibers and \ac{CTP}.

CB-A, CB-C, and CB-B boxes use standard TRD \acf{DCS} boards, they need infrastructure
of Ethernet.
Also \ac{TTC}⇧ signal (clock and trigger) is given from \ac{CTP}.

Since CTP interface is all using LVDS however pre-trigger interface for outside magnet
is all optical except for Ethernet, there is a custom module called \acf{PIM} to bridge those.
For additional debugging and trigger study, all CB-A, CB-B, and CB-C can send trigger output to PIM.

It is not presented in ~\autoref{fig:pretrigger-sbarrange} however also pre-trigger from ACORDE and also Beam Monitoring Detector
are foreseen.


\section{Front-end Boxes}

The \acf{FEB} is used to accept phototube signals of T0 and V0, generate sub-trigger of the pre-trigger, and send to the \ac{CB}s.
It houses T0 and V0 pre-amplifiers therefore FEBs are put very close to those detectors.
The FEBs are designed so that it can have maximum 12 pre-amplifiers.
Since each side (A and C) of T0 has 12 phototubes, there are one box placed for each side of T0.
However for V0 detector, there are 32 channels in each side.
Therefore 4 FEBs are placed for each side and each FEB contains 8 channels of pre-amplifiers.



\section{TOF Pre-trigger}

  \input{pretrigger-tof.tex}

\section{Control Boxes}

In the pre-trigger system, three \acf{CB} are installed and those are labeled CB-A, CB-C, and CB-B.
The suffixes of the name represent both function and location.
CB-A is located very close to A-side of the forward detectors, CB-C is also very close to C-side of the
forward detectors. However CB-B is located {\bf B}elow the backframe.
Functions of CB-A and CB-C are the same, however CB-B is different.
Those functions and feature of \acf{CB}s are  summarized in \autoref{tab:cb-functions}

\begin{table}[tbh]
\begin{center}
\begin{tabular}{|l|c|c|}
  \hline
  Function / Feature             & CB-A and CB-C   & CB-B  \\ \hline
  TTC receiving (TTCrx)          & yes             & yes   \\ \hline
  TTC forwarding (TTCex/TTCtx)   & -               & yes   \\ \hline
  FEB control and trigger accept & yes             & -     \\ \hline
  TOF trigger accept and logic   & -               & yes   \\ \hline
  Sub pre-trigger logic          & yes             & yes   \\ \hline
  Main pre-trigger logic         & -               & yes   \\ \hline
  Interface to PIM               & yes             & yes   \\ \hline
  Ethernet                       & yes             & yes   \\ \hline
  Backup system                  & yes             & yes   \\ \hline
  Form factor                    & small VME 6U    & full VME 6U \\ \hline
  Location                       & Close to FEBs   & below back frame \\ \hline
\end{tabular}
\caption{\label{tab:cb-functions}
Functions of \ac{CB}s in the pre-trigger system.
}
\end{center}
\end{table}

\subsection{Ethernet and IP network for CBs}

\autoref{tab:cb-network-param} shows the list of parameters of Ethernet and TCP/IP network for \ac{CB}s in ALICE cavern.

\begin{table}[tbh]
\begin{center}
\begin{tabular}{|l|c|c|}
  \hline
  Box   & main  &  backup \\ \hline
  CB-A  &       &         \\ \hline
  CB-C  &       &         \\ \hline
  CB-B  &       &         \\ \hline
\end{tabular}
\caption{\label{tab:cb-network-param}
Network parameters of \ac{CB}s in the ALICE cavern.
}
\end{center}
\end{table}

\subsection{CB-B}

The Control Box mounted below the backframe (CB-B) builds the
interface of the pretrigger system to the CTP and the TRD SMs. Its
functions comprise:
\begin{itemize}
\item trigger from CTP (L0, L1, L2)
\item processing of pretrigger inputs
\item trigger contribution to CTP L0 (TIN)
\item trigger generation to SM (FEE expects pretrigger and
  confirmation with L0 and L1)
\item pretrigger emulator
\item BC trigger
\item LUT
\end{itemize}
An overview of the \cbb components is shown in
Fig.~\ref{fig:cbb-ov}. The individual components will be discussed
subsequently. 

\begin{figure}[h]
\begin{center}
\includegraphics[width=0.95\textwidth]{figs/ptrg/cbb-ov}
\end{center}
\caption{CB-B overview}
\label{fig:cbb-ov}
\end{figure}

\subsubsection{Trigger generation}

The trigger output to the SMs and the CTP is generated by a state
machine which is intentionally kept simple. It ensures that only a
valid sequence of trigger pulses can be sent to the SM. All additional
features, s.a. pretrigger emulation from L0, is implemented in
separate entities. Fig.~\ref{fig:trg_sm} shows the state diagram of
the state machine used for the trigger generation. 

\begin{figure}[h]
\begin{center}
\includegraphics[width=0.95\textwidth]{figs/ptrg/trg_sm}
\end{center}
\caption{State diagram of the state machine used for the trigger
  signal generation.}
\label{fig:trg_sm}
\end{figure}

\section{Pre-trigger Interface Module}

Pre-trigger Interface Module (PIM) converts optical signals from control boxes to LVDS signals to be feed trigger signals into ALICE \ac{CTP}.
Also it has capability to convert LVDS signals to optical signals to send for example BUSY signal from GTU to PreTrigger system.

\section{Location of the pre-trigger modules}

\section{Powering Scheme}

All pre-trigger boxes need regulated electrical power of $\pm$6.5~V.
CB-B needs in addition $\pm$12~V to operate TTCex and TTCtx.
Wiener power supplies which are the same as TRD chambers are used.
The power supplies are located in O and I rack positions.
The precise scheme how the power is supplied is shown in \autoref{fig:pretrigger-power}.

\begin{figure}[hbt]
\begin{center}
\includegraphics*[width=22cm,angle=90]{figs/oyama/20081018-PreTrigger-PowerScheme.pdf}
\end{center}
\caption{\label{fig:pretrigger-power}
Powering scheme of the pretrigger system.
}
\end{figure}



\section{Pre-trigger Cables}

\subsection{Low Voltage}

\subsection{Optical Fibers}

\subsubsection{Optical Fibers from CBB to Sectors}

The optical fibers to connect from pre-trigger CBB to all sectors for TTC distribution was first placed by CERN fiber group.
However the first installation was found to be not optimal. For example the cable length for each sector were different (always
shortest length).

Thus, on around Sep., 2007, new installation has performed by Florian.Imre.Bordenave@cern.ch.
Detail discussion was done between Florian and Ken.
The all installed fibers from TTCex on CBB to sectors have 15 m length, single mode, ST on CBB side and to E2000 on super-module side.
2 fibers were prepared for each sector (primary and backup pretrigger system).
There is no patch panel on the way.

\subsection{Ethernet}

\subsection{JTAG}


\section{Trigger and Data Latency}


\section{Pre-trigger Command Format}


\section{SCSN Register Table}

\subsection{CB-B}

The \cbb configuration settings are accessible for write and read
access via SCSN in the 16-bit address space 0x0000..0xffff. It is
divided into sub-ranges for different components as shown in
table~\ref{tab:cbb-scsn_ranges}. The individual sub-ranges will be
discussed in the following sub-sections.

\begin{table}[h]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
{\bf range} & {\bf component} & {\bf used address space}\\
\hline 
0x0??? & general purpose registers & \\ \hline
0x1??? & timing analyzer & 9 bits \\ \hline
0x2??? & RAM counter & 6 bits \\ \hline
0x3??? & LUT & 9 bits \\ \hline
0x4??? & BC trigger & 9 bits \\ \hline
\end{tabular}
\end{center}
\caption{Usage of SCSN address space.}
\label{tab:cbb-scsn_ranges}
\end{table}

\subsubsection{General purpose registers} 

In the following all general purpose registers are listed. The values
shown are the reset values as set after power-up\footnote{NB: This can
  be different from what is set by the default configuration.}. Not
shown upper bits are not used; writing to them has no effect and you
will always read back 0. Bits shown but not labelled are accessible
but currently unused. Registers marked with ``ro'' are
read-only. Writing to the corresponding addresses has no effect. 

\begin{description}
\item[CTRL] \hfill 0x001
\begin{center}
\regfield{TLMU enable}{1}{0}{0}
\end{center}

\item[BLDINFO0/1] \hfill 0x002..0x003
\begin{center}
\regfield{clean}{1}{24}{.}%
\regfield{date}{24}{0}{.}%
\reglabel{0x0002}

\regfield{time}{16}{16}{.}%
\regfield{revision}{16}{0}{.}%
\reglabel{0x0003}
\end{center}

\item[TRGL0A] \hfill 0x010
\begin{center}
\regfield{pt to L0}{12}{0}{{43}}
\end{center}

\item[TRGL0S] \hfill 0x011
\begin{center}
\regfield{pt to L0}{12}{0}{{47}}
\end{center}

\item[TRGL1A] \hfill 0x012
\begin{center}
\regfield{pt to L0}{12}{0}{{308}}
\end{center}

\item[TRGL1S] \hfill 0x013
\begin{center}
\regfield{pt to L0}{12}{0}{{311}}
\end{center}

\item[TRGDEADPT] \hfill 0x014
\begin{center}
\regfield{pt to L0}{12}{0}{{200}}
\end{center}

\item[TRGDEADL0] \hfill 0x015
\begin{center}
\regfield{pt to L0}{12}{0}{{350}}
\end{center}

\item[TRGDEADL1] \hfill 0x016
\begin{center}
\regfield{pt to L0}{12}{0}{{500}}
\end{center}

\item[TRGDLYL0] \hfill 0x017
\begin{center}
\regfield{pt to L0}{12}{0}{{46}}
\end{center}

\item[TRGCTRL] \hfill 0x020
\begin{center}
\regfield{SM trg to CTP}{1}{9}{0}%
\regfield{trg emu}{1}{8}{0}%
\regfield{.}{4}{4}{.}%
\regfield{B-channel value}{1}{3}{0}%
\regfield{B-channel overwrite}{1}{2}{0}%
\regfield{A-channel value}{1}{1}{0}%
\regfield{A-channel overwrite}{1}{0}{0}%
\reglabel{0x0001}
\end{center}

\item[TRGACHDIS] \hfill 0x021
\begin{center}
\regfield{disable}{1}{0}{0}
\end{center}

\item[TRGTIN0/1/2] \hfill 0x022, 0x023, 0x024
\begin{center}
\regfield{option code}{2}{0}{00}
\hspace{2cm}
\begin{tabular}{|l|l|}
\hline
{\bf code} & {\bf function} \\ \hline
00 & normal triggering \\ \hline
01 & toggling \\ \hline
10 & Signature \\ \hline
11 & Random trigger \\ \hline
\end{tabular}
\end{center}

\item[PTCBASAMPL, PTCBCSAMPL] \hfill 0x030 (CB-A), 0x031 (CB-C)
\begin{center}
\regfield{sampling mode}{2}{0}{0}
\hspace{2cm}
\begin{tabular}{|l|l|}
\hline
{\bf mode} & {\bf bits} \\ \hline
00 & 5, 3 \\ \hline
01 & 3, 1 \\ \hline
10 & 4, 2 \\ \hline
11 & 2, 0 \\ \hline
\end{tabular}
\end{center}

\item[PTALIGN0/1] \hfill 0x032..0x033
\begin{center}
\regfield{stretch CB-A(1)}{1}{31}{0}%
\regfield{delay CB-A(1)}{3}{28}{000}
\regfield{stretch CB-A(0)}{1}{27}{0}%
\regfield{delay CB-A(0)}{3}{24}{000}
\regfield{stretch CB-C(1)}{1}{23}{0}%
\regfield{delay CB-C(1)}{3}{20}{000}
\regfield{stretch CB-C(0)}{1}{19}{0}%
\regfield{delay CB-C(0)}{3}{16}{000}
\regfield{stretch rnd}{1}{15}{0}%
\regfield{delay rnd}{3}{12}{000}
\regfield{stretch BC}{1}{11}{0}%
\regfield{delay BC}{3}{8}{000}
\regfield{stretch TLMU(7)}{1}{7}{0}%
\regfield{delay TLMU(7)}{3}{4}{000}
\regfield{stretch TLMU(6)}{1}{3}{0}%
\regfield{delay TLMU(6)}{3}{0}{000}
\reglabel{0x200b}

\regfield{stretch TLMU(5)}{1}{31}{0}%
\regfield{delay TLMU(5)}{3}{28}{000}
\regfield{stretch TLMU(4)}{1}{27}{0}%
\regfield{delay TLMU(4)}{3}{24}{000}
\regfield{stretch TLMU(3)}{1}{23}{0}%
\regfield{delay TLMU(3)}{3}{20}{000}
\regfield{stretch TLMU(2)}{1}{19}{0}%
\regfield{delay TLMU(2)}{3}{16}{000}
\regfield{stretch TLMU(1)}{1}{15}{0}%
\regfield{delay TLMU(1)}{3}{12}{000}
\regfield{stretch TLMU(0)}{1}{11}{0}%
\regfield{delay TLMU(0)}{3}{8}{000}
\regfield{stretch LUT trg(1)}{1}{7}{0}%
\regfield{delay LUT trg(1)}{3}{4}{000}
\regfield{stretch LUT trg(0)}{1}{3}{0}%
\regfield{delay LUT trg(0)}{3}{0}{000}
\reglabel{0x200a}
\end{center}

\item[BUSYCTRL] \hfill 0x034
\begin{center}
\regfield{}{3}{1}{0}%
\regfield{DDR sample}{1}{0}{0}
\end{center}

\item[RNDTHR] \hfill 0x040
\begin{center}
\regfield{threshold}{32}{0}{0}
\end{center}

\item[BCOFFSET] \hfill 0x050
\begin{center}
\regfield{BC(internal) - BC(L2a)}{12}{0}{0}
\end{center}
 
\item[BCL0] \hfill 0x051
\begin{center}
\regfield{BC(internal)}{12}{0}{0}
\end{center}

\item[BCL2] \hfill 0x052
\begin{center}
\regfield{BC(L2a)}{12}{0}{0}
\end{center}

\item[BCRESVAL] \hfill 0x053
\begin{center}
\regfield{reset value}{12}{0}{0}
\end{center}

\item[PTMASK] \hfill 0x060\\
enables for pretrigger sources
\begin{center}
\regfield{CB-A LUT}{2}{14}{00}%
\regfield{CB-C LUT}{2}{12}{00}%
\regfield{Random trigger}{1}{11}{0}%
\regfield{BC trigger}{1}{10}{0}%
\regfield{TLMU trigger}{8}{2}{00000000}%
\regfield{LUT trigger}{2}{0}{00}
\end{center}

\item[PTCBAPATT, PTCBCPATT] \hfill 0x061 (CB-A), 0x062 (CB-C)
\begin{center}
\regfield{pattern}{2}{0}{0}
\end{center}

\item[PTTLMUPATT] \hfill 0x063
\begin{center}
\regfield{pattern}{5}{0}{0}
\end{center}

\item[CNTCTRL] \hfill 0x070
\begin{center}
\regfield{reset}{1}{0}{0}
\end{center}

\item[CNT0, CNT1] \hfill 0x071..0x072
\begin{center}
\regfield{Counter L1}{16}{16}{0}%
\regfield{Counter L0}{16}{0}{0}%
\reglabel{0x1001}

\regfield{Counter L2r}{16}{16}{0}%
\regfield{Counter L2a}{16}{0}{0}%
\reglabel{0x1002}
\end{center}


\end{description}

\subsubsection{Timing analyzer}

The timing analyzer has the following control registers: 

\begin{description}
\item[TAMASK] \hfill 0x080
\begin{center}
\regfield{triggered}{1}{31}{.}
\regfield{GTU busy}{1}{30}{0}%
\regfield{CB-A}{2}{28}{00}%
\regfield{CB-C}{2}{26}{00}%
\regfield{A-channel out}{1}{25}{0}%
\regfield{L1 emu}{1}{24}{0}%
\regfield{L0 emu}{1}{23}{0}%
\regfield{PT CTP}{1}{22}{0}%
\regfield{PT emu}{1}{21}{0}%
\regfield{LUT trigger}{2}{19}{00}%
\regfield{TLMU}{8}{11}{00000000}%
\regfield{Random trigger}{1}{10}{0}%
\regfield{BC trigger}{1}{9}{0}%
\regfield{PT request}{1}{8}{0}%
\regfield{L1 to SM}{1}{7}{0}%
\regfield{L0 to SM}{1}{6}{0}%
\regfield{PT to SM}{1}{5}{0}%
\regfield{L0 contrib}{1}{4}{0}%
\regfield{TIN out}{1}{3}{0}%
\regfield{L0 to CTP}{1}{2}{0}%
\regfield{L1 TTCrx}{1}{1}{0}%
\regfield{L0 TTCrx}{1}{0}{1}
\end{center}

\item[TAARM] \hfill 0x081

\item[TAPOSTCNT] \hfill 0x082

\item[TASTATUS] \hfill 0x083
\begin{center}
\regfield{post counts}{4}{4}{{150}}%
\regfield{trigger}{1}{3}{.}%
\regfield{triggered}{1}{2}{.}%
\regfield{armed}{1}{1}{.}%
\regfield{running}{1}{0}{.}
\end{center}

\end{description}

The recorded data can be read from the address range
0x1000..0x11ff. Each 32-bit word contains the bits as shown in the
trigger condition. In addition bit 31 shows whether the trigger
condition was fulfilled in this sample.

\subsubsection{Trigger LUT} 

The trigger LUT is contained in the address range 0x3000..0x31ff. 

\subsubsection{RAM counter}

The 64~RAM counters can be read from the addresses 0x2000..0x2040.

\subsubsection{BC trigger}

The BC trigger is controlled by a bitmap which resides in the memory
range 0x4000..0x41ff. Only the first 3564 bits are used. For each bit
equal to one a pretrigger contribution is issued. The mapping is as
follows:

\begin{tabular}{cl}
word 0 bit 0 & bunch 0 \\
word 0 bit 1 & bunch 1 \\
\vdots \\
word 1 bit 0 & bunch 32 \\
\vdots
\end{tabular}

\section{Pre-trigger Control Software}



\subsection{Pre-trigger FSM and PVSS Interface}

According to ALICE TRD standard, pre-trigger system is controlled as a part of \acf{FSM} hierarchy.
\autoref{fig:pretrigger-fsm-diagram} shows finite state machine diagram of the pre-trigger system
implemented as a daemon software running on one of trhe Linux worker node.

\begin{figure}[hbt]
\begin{center}
\includegraphics*[width=10cm]{figs/oyama/FSM-Diagram}
\end{center}
\caption{\label{fig:pretrigger-fsm-diagram}
Finite State Machine diagram of the pre-trigger system interfacing to PVSS.
}
\end{figure}


\subsection{Pre-trigger Slim Server}


\subsection{Pre-trigger Data Points}

\subsection{Pre-trigger FXS}




% EOF
