--***************************************************************** --***************************************************************** --MUENSTER TRIGGER DESIGN --***************************************************************** --***************************************************************** LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_misc.all; -- Use OR_REDUCE function USE work.v1495pkg.all; ENTITY coin_reference IS PORT( nLBRES : IN std_logic; -- Async Reset (active low) LCLK : IN std_logic; -- Local Bus Clock C0 : IN std_logic; --TTC_CLK*5 = 200MHz ILA_DATA : OUT std_logic_vector (15 downto 0); ILA_RDADDRESS : OUT std_logic_vector (9 downto 0); ILA_WRADDRESS : OUT std_logic_vector (9 downto 0); ILA_WREN : OUT std_logic; ILA_Q : IN std_logic_vector (15 downto 0); --************************************************* -- REGISTER INTERFACE --************************************************* REG_WREN : IN std_logic; -- Write pulse (active high) REG_RDEN : IN std_logic; -- Read pulse (active high) REG_ADDR : IN std_logic_vector (15 DOWNTO 0); -- Register address REG_DIN : IN std_logic_vector (15 DOWNTO 0); -- Data from CAEN Local Bus REG_DOUT : OUT std_logic_vector (15 DOWNTO 0); -- Data to CAEN Local Bus USR_ACCESS : IN std_logic; -- Current register access is -- at user address space(Active high) --************************************************* -- V1495 Front Panel Ports (PORT A,B,C,G) --************************************************* A_DIN : IN std_logic_vector (31 DOWNTO 0); -- In A (32 x LVDS/ECL) B_DIN : IN std_logic_vector (31 DOWNTO 0); -- In B (32 x LVDS/ECL) C_DOUT : OUT std_logic_vector (31 DOWNTO 0); -- Out C (32 x LVDS) G_LEV : OUT std_logic; -- Output Level Select (NIM/TTL) G_DIR : OUT std_logic; -- Output Enable G_DOUT : OUT std_logic_vector (1 DOWNTO 0); -- Out G - LEMO (2 x NIM/TTL) G_DIN : IN std_logic_vector (1 DOWNTO 0); -- In G - LEMO (2 x NIM/TTL) --************************************************* -- A395x MEZZANINES INTERFACES (PORT D,E,F) --************************************************* -- Expansion Mezzanine Identifier: -- x_IDCODE : -- 000 : A395A (32 x IN LVDS/ECL) -- 001 : A395B (32 x OUT LVDS) -- 010 : A395C (32 x OUT ECL) -- 011 : A395D (8 x IN/OUT NIM/TTL) -- Expansion Mezzanine Port Signal Standard Select -- x_LEV : -- 0=>TTL,1=>NIM -- Expansion Mezzanine Port Direction -- x_DIR : -- 0=>OUT,1=>IN -- In/Out D (I/O Expansion) D_IDCODE : IN std_logic_vector ( 2 DOWNTO 0); -- D slot mezzanine Identifier D_LEV : OUT std_logic; -- D slot Port Signal Level Select D_DIR : OUT std_logic; -- D slot Port Direction D_DIN : IN std_logic_vector (31 DOWNTO 0); -- D slot Data In Bus D_DOUT : OUT std_logic_vector (31 DOWNTO 0); -- D slot Data Out Bus -- In/Out E (I/O Expansion) E_IDCODE : IN std_logic_vector ( 2 DOWNTO 0); -- E slot mezzanine Identifier E_LEV : OUT std_logic; -- E slot Port Signal Level Select E_DIR : OUT std_logic; -- E slot Port Direction E_DIN : IN std_logic_vector (31 DOWNTO 0); -- E slot Data In Bus E_DOUT : OUT std_logic_vector (31 DOWNTO 0); -- E slot Data Out Bus -- In/Out F (I/O Expansion) F_IDCODE : IN std_logic_vector ( 2 DOWNTO 0); -- F slot mezzanine Identifier F_LEV : OUT std_logic; -- F slot Port Signal Level Select F_DIR : OUT std_logic; -- F slot Port Direction F_DIN : IN std_logic_vector (31 DOWNTO 0); -- F slot Data In Bus F_DOUT : OUT std_logic_vector (31 DOWNTO 0); -- F slot Data Out Bus --************************************************* -- DELAY LINES --************************************************* -- PDL = Programmable Delay Lines (Step = 0.25ns / FSR = 64ns) -- DLO = Delay Line Oscillator (Half Period ~ 10 ns) -- 3D3428 PDL (PROGRAMMABLE DELAY LINE) CONFIGURATION PDL_WR : OUT std_logic; -- Write Enable PDL_SEL : OUT std_logic; -- PDL Selection (0=>PDL0, 1=>PDL1) PDL_READ : IN std_logic_vector ( 7 DOWNTO 0); -- Read Data PDL_WRITE : OUT std_logic_vector ( 7 DOWNTO 0); -- Write Data PDL_DIR : OUT std_logic; -- Direction (0=>Write, 1=>Read) -- DELAY I/O PDL0_OUT : IN std_logic; -- Signal from PDL0 Output PDL1_OUT : IN std_logic; -- Signal from PDL1 Output DLO0_OUT : IN std_logic; -- Signal from DLO0 Output DLO1_OUT : IN std_logic; -- Signal from DLO1 Output PDL0_IN : OUT std_logic; -- Signal to PDL0 Input PDL1_IN : OUT std_logic; -- Signal to PDL1 Input DLO0_GATE : OUT std_logic; -- DLO0 Gate (active high) DLO1_GATE : OUT std_logic; -- DLO1 Gate (active high) --************************************************* -- SPARE PORTS --************************************************* SPARE_OUT : OUT std_logic_vector(11 downto 0); -- SPARE Data Out SPARE_IN : IN std_logic_vector(11 downto 0); -- SPARE Data In SPARE_DIR : OUT std_logic_vector(11 downto 0); -- SPARE Direction (0 => OUT, 1 => IN) --************************************************* -- LED --************************************************* RED_PULSE : OUT std_logic; -- RED Led Pulse (active high) GREEN_PULSE : OUT std_logic -- GREEN Led Pulse (active high) ); -- Declarations END coin_reference ; ARCHITECTURE rtl OF coin_reference IS --*************************** --SIGNALS --*************************** signal TTC_CLK : std_logic; signal COINC_CLK : std_logic; signal L1_CTB_IN : std_logic; signal L1_CTB_IN_R : std_logic; signal L1_CTB_IN_RR : std_logic; signal L1_CTB_SYNC : std_logic; signal GTU_BUSY : std_logic; signal GTU_BUSY_IN : std_logic; signal GTU_BUSY_IN_R : std_logic; signal GTU_BUSY_IN_RR : std_logic; signal GTU_BUSY_RE : std_logic; signal GTU_BUSY_FE : std_logic; signal GTU_BUSY_SYNC : std_logic; signal MODE : std_logic_vector (15 downto 0); --signal ENABLE_PDL_COINC : std_logic; signal PT_SELECT : std_logic_vector (3 downto 0); signal GTU_BUSY_DISABLE : std_logic; signal DISABLE_L0 : std_logic :='0'; signal DISABLE_L1 : std_logic :='0'; signal L1_OVR_EXT : std_logic :='0'; signal READ_DELAY : std_logic :='0'; signal MASK : std_logic_vector (15 downto 0); signal SM_OUT : std_logic := '0'; signal SM_OUT_R : std_logic := '0'; signal SM_OUT_PDL : std_logic := '0'; signal GTU_OUT : std_logic := '0'; signal GTU_OUT_PDL : std_logic := '0'; --******************************** --VAR. FREQ. STANDARD 200 kHz --> STRESSTEST --******************************** signal KHZ : std_logic; signal CNT_VF : std_logic_vector (31 downto 0); signal CNT_VF_LIMIT : std_logic_vector (31 downto 0); --1KHz fot NOISE signal NOISE : std_logic; signal CNT_NOISE : std_logic_vector (15 downto 0); --******************************* --SINGLE PRETRIGGER --******************************* signal SNG_PT_REG : std_logic; signal SNG_PT_NEW : std_logic; signal SNG_PT_OLD : std_logic; signal SNG_PT : std_logic; signal SINGLE_PT : std_logic; signal SNG_PT_START : std_logic; signal SNG_PT_STOP : std_logic; signal SNG_PT_CNT : std_logic_vector (15 downto 0); signal SNG_PT_SENT : std_logic_vector (15 downto 0); signal SNG_PT_TIMES : std_logic_vector (15 downto 0); signal SNG_PT_CNT_LIMIT : std_logic_vector (15 downto 0); --**************************** --PDL --**************************** signal PDL_CONTROL: std_logic_vector(15 downto 0); -- W signal PDL_DATA : std_logic_vector(15 downto 0); -- R/W ------------------------- --COUNTER SCINTILLATORS, COINCIDENCE AND TRIGGERS ------------------------- --reset signal CNT_RST : std_logic_vector (15 downto 0); signal CNT_RST_T1 : std_logic; signal CNT_RST_T2 : std_logic; signal CNT_RST_T3 : std_logic; signal CNT_RST_T4 : std_logic; signal CNT_RST_B1 : std_logic; signal CNT_RST_B2 : std_logic; signal CNT_RST_B3 : std_logic; signal CNT_RST_B4 : std_logic; signal CNT_RST_B5 : std_logic; signal CNT_RST_TOP_RED : std_logic; signal CNT_RST_BTM_RED : std_logic; signal CNT_RST_COINC : std_logic; signal CNT_RST_TRG : std_logic; --enable signal CNT_ENA : std_logic_vector (15 downto 0); signal CNT_ENA_T1 : std_logic; signal CNT_ENA_T2 : std_logic; signal CNT_ENA_T3 : std_logic; signal CNT_ENA_T4 : std_logic; signal CNT_ENA_B1 : std_logic; signal CNT_ENA_B2 : std_logic; signal CNT_ENA_B3 : std_logic; signal CNT_ENA_B4 : std_logic; signal CNT_ENA_B5 : std_logic; signal CNT_ENA_TOP_RED : std_logic; signal CNT_ENA_BTM_RED : std_logic; signal CNT_ENA_COINC : std_logic; signal CNT_ENA_TRG : std_logic; --counter signal CNT_T1 : std_logic_vector (31 downto 0); signal CNT_T2 : std_logic_vector (31 downto 0); signal CNT_T3 : std_logic_vector (31 downto 0); signal CNT_T4 : std_logic_vector (31 downto 0); signal CNT_B1 : std_logic_vector (31 downto 0); signal CNT_B2 : std_logic_vector (31 downto 0); signal CNT_B3 : std_logic_vector (31 downto 0); signal CNT_B4 : std_logic_vector (31 downto 0); signal CNT_B5 : std_logic_vector (31 downto 0); signal CNT_TOP_RED : std_logic_vector (31 downto 0); signal CNT_BTM_RED : std_logic_vector (31 downto 0); signal CNT_COINC : std_logic_vector (31 downto 0); signal CNT_PRE : std_logic_vector (31 downto 0); signal CNT_L0 : std_logic_vector (31 downto 0); signal CNT_L1 : std_logic_vector (31 downto 0); signal CNT_L1_OVR : std_logic_vector (31 downto 0); signal CNT_L1_COINC : std_logic_vector (31 downto 0); --control register for PT,L0,L1 signal CNT_TRG_CTRL : std_logic_vector (15 downto 0); ------------------------- --SCINTILLATORS ------------------------- --incoming signals signal T1_IN : std_logic; signal T2_IN : std_logic; signal T3_IN : std_logic; signal T4_IN : std_logic; signal B1_IN : std_logic; signal B2_IN : std_logic; signal B3_IN : std_logic; signal B4_IN : std_logic; signal B5_IN : std_logic; --for sync signal T1_NOW : std_logic; signal T2_NOW : std_logic; signal T3_NOW : std_logic; signal T4_NOW : std_logic; signal B1_NOW : std_logic; signal B2_NOW : std_logic; signal B3_NOW : std_logic; signal B4_NOW : std_logic; signal B5_NOW : std_logic; signal T1_LAST : std_logic; signal T2_LAST : std_logic; signal T3_LAST : std_logic; signal T4_LAST : std_logic; signal B1_LAST : std_logic; signal B2_LAST : std_logic; signal B3_LAST : std_logic; signal B4_LAST : std_logic; signal B5_LAST : std_logic; --synced signals with ttc clk signal SZ_T1 : std_logic; signal SZ_T2 : std_logic; signal SZ_T3 : std_logic; signal SZ_T4 : std_logic; signal SZ_B1 : std_logic; signal SZ_B2 : std_logic; signal SZ_B3 : std_logic; signal SZ_B4 : std_logic; signal SZ_B5 : std_logic; signal SZ_TOP : std_logic_vector (3 downto 0); signal SZ_BTM : std_logic_vector (4 downto 0); signal SZ_TOP_RED : std_logic; signal SZ_BTM_RED : std_logic; --signal SZ_BTM_RED_NOT_SYNCED : std_logic; --for sync with coinc clk signal T1_NOW_FAST : std_logic; signal T2_NOW_FAST : std_logic; signal T3_NOW_FAST : std_logic; signal T4_NOW_FAST : std_logic; signal B1_NOW_FAST : std_logic; signal B2_NOW_FAST : std_logic; signal B3_NOW_FAST : std_logic; signal B4_NOW_FAST : std_logic; signal B5_NOW_FAST : std_logic; signal T1_LAST_FAST : std_logic; signal T2_LAST_FAST : std_logic; signal T3_LAST_FAST : std_logic; signal T4_LAST_FAST : std_logic; signal B1_LAST_FAST : std_logic; signal B2_LAST_FAST : std_logic; signal B3_LAST_FAST : std_logic; signal B4_LAST_FAST : std_logic; signal B5_LAST_FAST : std_logic; --synced signals with coinc clk signal SZ_T1_FAST : std_logic; signal SZ_T2_FAST : std_logic; signal SZ_T3_FAST : std_logic; signal SZ_T4_FAST : std_logic; signal SZ_B1_FAST : std_logic; signal SZ_B2_FAST : std_logic; signal SZ_B3_FAST : std_logic; signal SZ_B4_FAST : std_logic; signal SZ_B5_FAST : std_logic; signal SZ_TOP_FAST : std_logic_vector (3 downto 0); signal SZ_BTM_FAST : std_logic_vector (4 downto 0); signal SZ_TOP_RED_FAST : std_logic; signal SZ_BTM_RED_FAST : std_logic; --signals to stretch top and btm to 50ns to be compared for coincidence type FSM_SZ is (SZ_LOW, SZ_HIGH); signal BTM_FSM : FSM_SZ; signal TOP_FSM : FSM_SZ; signal COINC_FSM : FSM_SZ; signal TOP_FAST : std_logic; signal BTM_FAST : std_logic; signal COINC_FAST : std_logic; signal TOP_SZ_CNT : std_logic_vector (15 downto 0); signal BTM_SZ_CNT : std_logic_vector (15 downto 0); signal COINC_SZ_CNT : std_logic_vector (15 downto 0); signal SZ_FAST_CNT_LIMIT : std_logic_vector (15 downto 0); signal TOP_FAST_PDL : std_logic; signal BTM_FAST_PDL : std_logic; signal COINC_FAST_SHORT : std_logic; signal COINC2 : std_logic; signal COINC_FAST_NEW : std_logic; signal COINC_FAST_OLD : std_logic; --SINGLE SHOT - ANY TRIGGER signal SINGLE_SHOT_ACTIVE : std_logic; signal VETO_SINGLE_SM : std_logic; --*********************** --STATE MACHINE FOR TRIGGER SEQUENCE --*********************** type FSM_SEQ is (IDLE, SEND_PT, WAIT_L0, SEND_L0, WAIT_L1, SEND_L1, READOUT, CLEAR); signal CS_SEQ : FSM_SEQ; signal NS_SEQ : FSM_SEQ; signal CS_SEQ_N : std_logic_vector (2 downto 0); signal NS_SEQ_N : std_logic_vector (2 downto 0); signal CS_SEQ_VEC_I : std_logic_vector (2 downto 0); signal CS_SEQ_VEC : std_logic_vector (2 downto 0); signal ISSUE_PT : std_logic; signal ISSUE_L0 : std_logic; signal ISSUE_L1 : std_logic; signal ISSUE_L1_R : std_logic; signal ISSUE_PT_I : std_logic; signal ISSUE_L0_I : std_logic; signal ISSUE_L1_I : std_logic; signal CNT_L0_DELAY : std_logic_vector (15 downto 0); signal CNT_L1_DELAY : std_logic_vector (15 downto 0); signal CNT_CLEAR_DELAY : std_logic_vector (15 downto 0); signal CNT_READ_DELAY : std_logic_vector (15 downto 0); signal CNT_READ_DELAY2 : std_logic_vector (15 downto 0); signal CNT_L0_DELAY_I : std_logic_vector (15 downto 0); signal CNT_L1_DELAY_I : std_logic_vector (15 downto 0); signal CNT_CLEAR_DELAY_I : std_logic_vector (15 downto 0); signal CNT_READ_DELAY_I : std_logic_vector (15 downto 0); signal CNT_READ_DELAY2_I : std_logic_vector (15 downto 0); signal CNT_L0_LIMIT : std_logic_vector (15 downto 0); signal CNT_L1_LIMIT : std_logic_vector (15 downto 0); signal CNT_CLEAR_LIMIT : std_logic_vector (15 downto 0); signal CNT_READ_LIMIT : std_logic_vector (15 downto 0); signal L1_TRG : std_logic; signal L1_TRG_CTB : std_logic; signal L1_TRG_OVR : std_logic; signal TRG_CLEAR : std_logic; signal TRG_CLEAR_I : std_logic; --signals for coinc + btm_gtu --> l1 override for coinc-events signal L1_OVR : std_logic; signal L1_OVR_I : std_logic; signal L1_OVR_R : std_logic; signal L1_OVR_RR : std_logic; signal SZ_BTM_RED_R : std_logic; signal SZ_BTM_RED_RR : std_logic; signal L1_COINC_I : std_logic; --l1 without l1ctb from gtu signal L1_COINC : std_logic; --stresstest: random numbers and ratios for triggers signal LFSR : std_logic_vector (31 downto 0); signal STRESS_L0 : std_logic_vector (31 downto 0); signal STRESS_L1 : std_logic_vector (31 downto 0); signal STRESS_PT : std_logic_vector (31 downto 0); --noise: exclude cosmics from noise events signal NOISE_VETO : std_logic; signal SZ_ACTIVE : std_logic; signal NOISE_VETO_CNT : std_logic_vector (16 downto 0); signal NOISE_STOPPED : std_logic; signal NOISE_STOPPED_I : std_logic; --internal logic analyzer signal ILA_DATA_I : std_logic_vector ( 15 downto 0); signal ILA_RDADDRESS_I : std_logic_vector ( 9 downto 0); signal ILA_WRADDRESS_I : std_logic_vector (9 downto 0); signal ILA_WREN_I : std_logic; signal ILA_Q_I : std_logic_vector (15 downto 0); type ILA_FSM is (IDLE, ARM, ARMED, TRIGGERED, COMPLETE); signal ILA_CS : ILA_FSM; signal ILA_NS : ILA_FSM; signal ILA_TRG_MASK : std_logic_vector (15 downto 0); signal ILA_TRG : std_logic_vector (15 downto 0); signal ILA_CNT : std_logic_vector (15 downto 0); signal ILA_CNT_I : std_logic_vector (15 downto 0); signal ILA_ARM_REG : std_logic; signal ILA_ARM_R : std_logic; signal ILA_ARM_RR : std_logic; signal ILA_ARM : std_logic; signal ILA_VME_DONE_REG : std_logic; signal ILA_VME_DONE_R : std_logic; signal ILA_VME_DONE_RR : std_logic; signal ILA_VME_DONE : std_logic; signal ILA_MODE : std_logic; signal ILA_CNT_LIMIT : std_logic_vector (15 downto 0); signal ILA_WREN_I_I : std_logic; signal ILA_COMPLETE : std_logic; signal ILA_COMPLETE_I : std_logic; signal ILA_TRG_REG : std_logic; signal ILA_TRG_REG_R : std_logic; signal ILA_TRG_REG_RR : std_logic; signal ILA_TRG_MANUAL : std_logic; signal ILA_ARM_CNT : std_logic_vector (15 downto 0); signal ILA_ARM_CNT_I : std_logic_vector (15 downto 0); signal GTU_SM_OUT_OF_SYNC : std_logic; signal CLEAR_COUNTER : std_logic_vector (15 downto 0); signal CLEAR_TOO_LONG : std_logic; signal CLEAR_TOO_LONG_R : std_logic; --*********************** --TREFI Calibration --*********************** signal TREFI0 : std_logic; signal TREFI1 : std_logic; signal TREFI2 : std_logic; signal TREFI3 : std_logic; signal TREFI4 : std_logic; signal TREFI5 : std_logic; signal TREFI6 : std_logic; signal TREFI7 : std_logic; signal TREFI8 : std_logic; signal TREFI9 : std_logic; signal TREFI_ALL : std_logic; signal TREFI0_NOW : std_logic; signal TREFI1_NOW : std_logic; signal TREFI2_NOW : std_logic; signal TREFI3_NOW : std_logic; signal TREFI4_NOW : std_logic; signal TREFI5_NOW : std_logic; signal TREFI6_NOW : std_logic; signal TREFI7_NOW : std_logic; signal TREFI8_NOW : std_logic; signal TREFI9_NOW : std_logic; signal TREFI0_LAST : std_logic; signal TREFI1_LAST : std_logic; signal TREFI2_LAST : std_logic; signal TREFI3_LAST : std_logic; signal TREFI4_LAST : std_logic; signal TREFI5_LAST : std_logic; signal TREFI6_LAST : std_logic; signal TREFI7_LAST : std_logic; signal TREFI8_LAST : std_logic; signal TREFI9_LAST : std_logic; signal CNT_TREFI0 : std_logic_vector (15 downto 0); signal CNT_TREFI1 : std_logic_vector (15 downto 0); signal CNT_TREFI2 : std_logic_vector (15 downto 0); signal CNT_TREFI3 : std_logic_vector (15 downto 0); signal CNT_TREFI4 : std_logic_vector (15 downto 0); signal CNT_TREFI5 : std_logic_vector (15 downto 0); signal CNT_TREFI6 : std_logic_vector (15 downto 0); signal CNT_TREFI7 : std_logic_vector (15 downto 0); signal CNT_TREFI8 : std_logic_vector (15 downto 0); signal CNT_TREFI9 : std_logic_vector (15 downto 0); signal CNT_TREFI_ALL : std_logic_vector (15 downto 0); signal TREFI_BTM_TOP_SELECT : std_logic; signal CNT_RST_TREFI : std_logic; signal CNT_ENA_TREFI : std_logic; signal CNT_TREFI_CTRL : std_logic_vector (15 downto 0); BEGIN --************************** --SCINTILLATORS --************************** -- incoming signals with mask T1_IN <= (not(B_DIN (0))); T2_IN <= (not(B_DIN (1))); T3_IN <= (not(B_DIN (2))); T4_IN <= (not(B_DIN (3))); B1_IN <= (not(B_DIN (4))); B2_IN <= (not(B_DIN (5))); B3_IN <= (not(B_DIN (6))); B4_IN <= (not(B_DIN (7))); B5_IN <= (not(B_DIN (8))); --SZ_BTM_RED_NOT_SYNCED <= B1_IN or B2_IN or B3_IN or B4_IN or B5_IN; --SYNCED with TTC CLK SZ_T1 <= T1_NOW and (not T1_LAST) and MASK(0); SZ_T2 <= T2_NOW and (not T2_LAST) and MASK(1); SZ_T3 <= T3_NOW and (not T3_LAST) and MASK(2); SZ_T4 <= T4_NOW and (not T4_LAST) and MASK(3); SZ_B1 <= B1_NOW and (not B1_LAST) and MASK(4); SZ_B2 <= B2_NOW and (not B2_LAST) and MASK(5); SZ_B3 <= B3_NOW and (not B3_LAST) and MASK(6); SZ_B4 <= B4_NOW and (not B4_LAST) and MASK(7); SZ_B5 <= B5_NOW and (not B5_LAST) and MASK(8); --TOP and BTM vectors 40MHz SZ_TOP (0) <= SZ_T1; SZ_TOP (1) <= SZ_T2; SZ_TOP (2) <= SZ_T3; SZ_TOP (3) <= SZ_T4; SZ_BTM (0) <= SZ_B1; SZ_BTM (1) <= SZ_B2; SZ_BTM (2) <= SZ_B3; SZ_BTM (3) <= SZ_B4; SZ_BTM (4) <= SZ_B5; --TOP and BTM REDUCED 40MHz SZ_TOP_RED <= OR_REDUCE(SZ_TOP); SZ_BTM_RED <= OR_REDUCE(SZ_BTM); ------------------------------- -- PDL DELAY LINES CONTROL ------------------------------- PDL_WR <= PDL_CONTROL(0); --write enable PDL_DIR <= PDL_CONTROL(1); --richtung: lesen oder schreiben PDL_SEL <= PDL_CONTROL(2); -- auswahl ob pdl0 oder pdl1 PDL_WRITE <= PDL_DATA(7 downto 0); --wert der geschrieben wird ------------------------------ --COUNTER CONTROL SIGNALS ------------------------------ --Reset signals for scintillaotr counters CNT_RST_T1 <= CNT_RST(0); CNT_RST_T2 <= CNT_RST(1); CNT_RST_T3 <= CNT_RST(2); CNT_RST_T4 <= CNT_RST(3); CNT_RST_B1 <= CNT_RST(4); CNT_RST_B2 <= CNT_RST(5); CNT_RST_B3 <= CNT_RST(6); CNT_RST_B4 <= CNT_RST(7); CNT_RST_B5 <= CNT_RST(8); CNT_RST_TOP_RED <= CNT_RST(9); CNT_RST_BTM_RED <= CNT_RST(10); CNT_RST_COINC <= CNT_RST(11); --Enable signals for scintillator counters CNT_ENA_T1 <= CNT_ENA(0); CNT_ENA_T2 <= CNT_ENA(1); CNT_ENA_T3 <= CNT_ENA(2); CNT_ENA_T4 <= CNT_ENA(3); CNT_ENA_B1 <= CNT_ENA(4); CNT_ENA_B2 <= CNT_ENA(5); CNT_ENA_B3 <= CNT_ENA(6); CNT_ENA_B4 <= CNT_ENA(7); CNT_ENA_B5 <= CNT_ENA(8); CNT_ENA_TOP_RED <= CNT_ENA(9); CNT_ENA_BTM_RED <= CNT_ENA(10); CNT_ENA_COINC <= CNT_ENA (11); --CNT_ENA_TRG <= CNT_ENA(12); --CNT_RST_TRG <= CNT_RST(12); CNT_ENA_TRG <= CNT_TRG_CTRL(0); CNT_RST_TRG <= CNT_TRG_CTRL(1); --**************************** --SYNC OF INCOMING SIGNALS --**************************** ---------------- --TTC_CLK ---------------- process (TTC_CLK, nLBRES) begin if nLBRES='0' then T1_NOW <= '0'; T2_NOW <= '0'; T3_NOW <= '0'; T4_NOW <= '0'; B1_NOW <= '0'; B2_NOW <= '0'; B3_NOW <= '0'; B4_NOW <= '0'; B5_NOW <= '0'; T1_LAST <= '0'; T2_LAST <= '0'; T3_LAST <= '0'; T4_LAST <= '0'; B1_LAST <= '0'; B2_LAST <= '0'; B3_LAST <= '0'; B4_LAST <= '0'; B5_LAST <= '0'; SNG_PT_NEW <= '0'; SNG_PT_OLD <= '0'; L1_CTB_IN <= '0'; L1_CTB_IN_R <= '0'; L1_CTB_IN_RR <= '0'; SZ_BTM_RED_R <= '0'; SZ_BTM_RED_RR <= '0'; COINC_FAST_OLD <= '0'; COINC_FAST_NEW <= '0'; ILA_ARM_R <= '0'; ILA_ARM_RR <= '0'; ILA_VME_DONE_R <= '0'; ILA_VME_DONE_RR <= '0'; ILA_TRG_REG_R <= '0'; ILA_TRG_REG_RR <= '0'; SM_OUT_R <= '0'; CLEAR_TOO_LONG_R <= '0'; elsif rising_edge (TTC_CLK) then T1_NOW <= T1_IN; T2_NOW <= T2_IN; T3_NOW <= T3_IN; T4_NOW <= T4_IN; B1_NOW <= B1_IN; B2_NOW <= B2_IN; B3_NOW <= B3_IN; B4_NOW <= B4_IN; B5_NOW <= B5_IN; T1_LAST <= T1_NOW; T2_LAST <= T2_NOW; T3_LAST <= T3_NOW; T4_LAST <= T4_NOW; B1_LAST <= B1_NOW; B2_LAST <= B2_NOW; B3_LAST <= B3_NOW; B4_LAST <= B4_NOW; B5_LAST <= B5_NOW; SNG_PT_NEW <= SNG_PT_REG; SNG_PT_OLD <= SNG_PT_NEW; L1_CTB_IN <= not (B_DIN(9)); L1_CTB_IN_R <= L1_CTB_IN; L1_CTB_IN_RR <= L1_CTB_IN_R; GTU_BUSY_IN <= not (B_DIN(10)); GTU_BUSY_IN_R <= GTU_BUSY_IN; GTU_BUSY_IN_RR <= GTU_BUSY_IN_R; SZ_BTM_RED_R <= SZ_BTM_RED; SZ_BTM_RED_RR <= SZ_BTM_RED_R; COINC_FAST_NEW <= COINC_FAST; COINC_FAST_OLD <= COINC_FAST_NEW; ILA_ARM_R <= ILA_ARM_REG; ILA_ARM_RR <= ILA_ARM_R; ILA_VME_DONE_R <= ILA_VME_DONE_REG; ILA_VME_DONE_RR <= ILA_VME_DONE_R; ILA_TRG_REG_R <= ILA_TRG_REG; ILA_TRG_REG_RR <= ILA_TRG_REG_R; SM_OUT_R <= SM_OUT; CLEAR_TOO_LONG_R <= CLEAR_TOO_LONG; end if; end process; ----------------------------- --COINC_CLK ----------------------------- process (COINC_CLK, nLBRES) begin if nLBRES='0' then T1_NOW_FAST <= '0'; T2_NOW_FAST <= '0'; T3_NOW_FAST <= '0'; T4_NOW_FAST <= '0'; B1_NOW_FAST <= '0'; B2_NOW_FAST <= '0'; B3_NOW_FAST <= '0'; B4_NOW_FAST <= '0'; B5_NOW_FAST <= '0'; T1_LAST_FAST <= '0'; T2_LAST_FAST <= '0'; T3_LAST_FAST <= '0'; T4_LAST_FAST <= '0'; B1_LAST_FAST <= '0'; B2_LAST_FAST <= '0'; B3_LAST_FAST <= '0'; B4_LAST_FAST <= '0'; B5_LAST_FAST <= '0'; elsif rising_edge (COINC_CLK) then T1_NOW_FAST <= T1_IN; T2_NOW_FAST <= T2_IN; T3_NOW_FAST <= T3_IN; T4_NOW_FAST <= T4_IN; B1_NOW_FAST <= B1_IN; B2_NOW_FAST <= B2_IN; B3_NOW_FAST <= B3_IN; B4_NOW_FAST <= B4_IN; B5_NOW_FAST <= B5_IN; T1_LAST_FAST <= T1_NOW_FAST; T2_LAST_FAST <= T2_NOW_FAST; T3_LAST_FAST <= T3_NOW_FAST; T4_LAST_FAST <= T4_NOW_FAST; B1_LAST_FAST <= B1_NOW_FAST; B2_LAST_FAST <= B2_NOW_FAST; B3_LAST_FAST <= B3_NOW_FAST; B4_LAST_FAST <= B4_NOW_FAST; B5_LAST_FAST <= B5_NOW_FAST; end if; end process; ---------------------------- --MODE BITS ---------------------------- PT_SELECT <= MODE (3 downto 0); GTU_BUSY_DISABLE <= MODE (4); --16 SINGLE_SHOT_ACTIVE <= MODE (5); --32 DISABLE_L0 <= MODE (6); --64 DISABLE_L1 <= MODE (7); --128 L1_OVR_EXT <= MODE (8); --256 READ_DELAY <= MODE (9); --512 ---------------------------------------------- --Direction and Level of D and G Ports ---------------------------------------------- G_LEV <= '1'; --LEVEL: 0 => TTL, 1 => NIM G_DIR <= '1'; --DIRECTION 0=>OUT, 1=>IN D_LEV <= '1'; D_DIR <= '0'; ----------------------------- --CLOCKS ----------------------------- TTC_CLK <= G_DIN(0); COINC_CLK <= C0; --************************************** --OUTPUTS --************************************** ----------------------------- --Supermodule and GTU Output ----------------------------- SM_OUT <= ISSUE_PT or ISSUE_L0 or ISSUE_L1; GTU_OUT <= ISSUE_L0 or ISSUE_L1 or ISSUE_L1_R; --Delayed over PDLs for Sync with TTCex --not used, sync over cable length --PDL0_IN <= SM_OUT; --PDL1_IN <= GTU_OUT; --SM_OUT_PDL <= PDL0_OUT; --GTU_OUT_PDL <= PDL1_OUT; -- TRIGGER OUTPUT SM C_DOUT(30) <= not SM_OUT_PDL; C_DOUT(14) <= not SM_OUT_PDL; C_DOUT(12) <= not SM_OUT; D_DOUT(1) <= SM_OUT_PDL; RED_PULSE <= SM_OUT; --TRIGGER OUTPUT GTU C_DOUT(13) <= not GTU_OUT_PDL; C_DOUT(11) <= not GTU_OUT; D_DOUT(2) <= GTU_OUT_PDL; GREEN_PULSE <= GTU_OUT; --signals for scope control - C OUT HAVE TO BE INVERTED C_DOUT(0) <= not SM_OUT_PDL; C_DOUT(1) <= not GTU_OUT_PDL; C_DOUT(2) <= not COINC2; C_DOUT(3) <= not SZ_BTM_RED; C_DOUT(4) <= not SZ_BTM_RED_RR; C_DOUT(5) <= not GTU_BUSY; C_DOUT(6) <= not L1_OVR_I; C_DOUT(7) <= not L1_OVR; D_DOUT(3) <= SM_OUT_PDL; D_DOUT(4) <= SM_OUT;--ISSUE_PT or ISSUE_PT_R or ISSUE_L0 or ISSUE_L0_R or ISSUE_L1 or ISSUE_L1_R; D_DOUT(5) <= GTU_OUT; D_DOUT(6) <= GTU_BUSY; D_DOUT(7) <= SM_OUT_PDL; --**************************************************************** --STATE MACHINE FOR TRIGGERS --**************************************************************** L1_CTB_SYNC <= L1_CTB_IN_R and (not L1_CTB_IN_RR); --L1 --> high if L1ctb arrives or L1_ovr active process (TTC_CLK, nLBRES, TRG_CLEAR) begin if rising_edge (TTC_CLK) then if nLBRES = '0' or TRG_CLEAR = '1' then L1_TRG_CTB <= '0'; L1_TRG_OVR <= '0'; else if L1_CTB_SYNC = '1' then --or L1_OVR_RR = '1' or L1_OVR_R = '1' then L1_TRG_CTB <= '1'; end if; if L1_OVR_RR = '1' then L1_TRG_OVR <= '1'; end if; end if; end if; end process; L1_TRG <= L1_TRG_CTB or L1_TRG_OVR; --current_state process (TTC_CLK, nLBRES) begin if rising_edge (TTC_CLK) then if nLBRES ='0' then CS_SEQ <= IDLE ; CS_SEQ_N <= "000"; ISSUE_PT <= '0'; ISSUE_L0 <= '0'; ISSUE_L1 <= '0'; CNT_L0_DELAY <= (others => '0'); CNT_L1_DELAY <= (others => '0'); CNT_CLEAR_DELAY <= (others => '0'); CNT_READ_DELAY <= (others => '0'); CNT_READ_DELAY2 <= (others => '0'); TRG_CLEAR <= '0'; CS_SEQ_VEC <= "000"; NOISE_STOPPED <= '0'; L1_COINC <= '0'; else CS_SEQ <= NS_SEQ; CS_SEQ_N <= NS_SEQ_N; ISSUE_PT <= ISSUE_PT_I; ISSUE_L0 <= ISSUE_L0_I and (not DISABLE_L0); ISSUE_L1 <= ISSUE_L1_I and (not DISABLE_L1); CNT_L0_DELAY <= CNT_L0_DELAY_I; CNT_L1_DELAY <= CNT_L1_DELAY_I; CNT_CLEAR_DELAY <= CNT_CLEAR_DELAY_I; CNT_READ_DELAY <= CNT_READ_DELAY_I; CNT_READ_DELAY2 <= CNT_READ_DELAY2_I; ISSUE_L1_R <= ISSUE_L1; TRG_CLEAR <= TRG_CLEAR_I; L1_OVR <= L1_OVR_I; L1_OVR_R <= L1_OVR; L1_OVR_RR <= L1_OVR_R; CS_SEQ_VEC <= CS_SEQ_VEC_I; NOISE_STOPPED <= NOISE_STOPPED_I; L1_COINC <= L1_COINC_I; end if; end if; end process; --next state process (CS_SEQ, CS_SEQ_N, CNT_L0_DELAY, CNT_L1_DELAY, CNT_CLEAR_DELAY, CNT_READ_DELAY, CNT_READ_DELAY2, GTU_BUSY, L1_TRG, CNT_L0_LIMIT, CNT_L1_LIMIT, CNT_CLEAR_LIMIT, CNT_READ_LIMIT, COINC2, PT_SELECT, SZ_BTM_RED_RR, KHZ, NOISE, SZ_BTM_RED, LFSR, STRESS_L0, STRESS_L1, STRESS_PT, SZ_ACTIVE, NOISE_VETO, L1_OVR_EXT, VETO_SINGLE_SM, SINGLE_SHOT_ACTIVE, SINGLE_PT, GTU_BUSY_DISABLE, READ_DELAY, L1_TRG_CTB, L1_TRG_OVR, TTC_CLK) begin NS_SEQ <= CS_SEQ; NS_SEQ_N <= CS_SEQ_N; ISSUE_PT_I <= '0'; ISSUE_L0_I <= '0'; ISSUE_L1_I <= '0'; CNT_L0_DELAY_I <= CNT_L0_DELAY; CNT_L1_DELAY_I <= CNT_L1_DELAY; CNT_CLEAR_DELAY_I <= CNT_CLEAR_DELAY; CNT_READ_DELAY_I <= CNT_READ_DELAY; CNT_READ_DELAY2_I <= CNT_READ_DELAY2; TRG_CLEAR_I <= '0'; L1_OVR_I <= '0'; CS_SEQ_VEC_I <= "000"; NOISE_STOPPED_I <= '0'; L1_COINC_I <= '0'; --case CS_SEQ is case CS_SEQ_N is --when IDLE => when "000" => CNT_L0_DELAY_I <= (others => '0'); CNT_L1_DELAY_I <= (others => '0'); CNT_READ_DELAY_I <= (others => '0'); CNT_READ_DELAY2_I <= (others => '0'); CNT_CLEAR_DELAY_I <= (others => '0'); TRG_CLEAR_I <= '1'; CS_SEQ_VEC_I <= "000"; if PT_SELECT = "1001" then --coinc + btm if COINC2 = '1' and GTU_BUSY = '0' then NS_SEQ <= SEND_PT; L1_OVR_I <= '1'; elsif SZ_BTM_RED_RR = '1' and GTU_BUSY = '0' then NS_SEQ <= SEND_PT; L1_OVR_I <= '0'; else null; end if; elsif PT_SELECT = "0000" then --coinc if COINC2 = '1' and GTU_BUSY = '0' then NS_SEQ <= SEND_PT; L1_OVR_I <= '1'; end if; elsif PT_SELECT = "0001" and GTU_BUSY = '0' then -- noise if NOISE = '1' and NOISE_VETO = '0' and SZ_ACTIVE = '0' then NS_SEQ <= SEND_PT; L1_OVR_I <= '1'; end if; elsif PT_SELECT = "0010" and GTU_BUSY = '0' then --bottom if SZ_BTM_RED_RR = '1' then NS_SEQ <= SEND_PT; end if; elsif PT_SELECT = "0101" and GTU_BUSY = '0' then --stresstest if LFSR < STRESS_PT and KHZ = '1' then NS_SEQ <= SEND_PT; NS_SEQ_N <= "001"; end if; -- if KHZ = '1' then -- NS_SEQ <= SEND_PT; -- end if; elsif PT_SELECT = "0110" and GTU_BUSY = '0' then --fastnoise if NOISE = '1' then NS_SEQ <= SEND_PT; L1_OVR_I <= '1'; end if; elsif PT_SELECT = "0100" then ISSUE_PT_I <= SINGLE_PT; else null; -- end if; --when SEND_PT => when "001" => if PT_SELECT = "0001" and SZ_ACTIVE = '1' then NS_SEQ <= READOUT; NOISE_STOPPED_I <= '1'; elsif SINGLE_SHOT_ACTIVE = '1' and VETO_SINGLE_SM = '1' then NS_SEQ <= CLEAR; else ISSUE_PT_I <= '1'; NS_SEQ <= WAIT_L0; NS_SEQ_N <= "010"; CNT_L0_DELAY_I <= CNT_L0_DELAY + '1'; CNT_L1_DELAY_I <= CNT_L1_DELAY + '1'; CNT_READ_DELAY_I <= CNT_READ_DELAY + '1' ; end if; CS_SEQ_VEC_I <= "001"; --when WAIT_L0 => when "010" => if PT_SELECT = "0001" and (SZ_ACTIVE = '1')then NS_SEQ <= READOUT; NOISE_STOPPED_I <= '1'; elsif CNT_L0_DELAY = (CNT_L0_LIMIT) then NS_SEQ <= SEND_L0; NS_SEQ_N <= "011"; else CNT_L0_DELAY_I <= CNT_L0_DELAY + '1'; end if; CNT_L1_DELAY_I <= CNT_L1_DELAY + '1'; CNT_READ_DELAY_I <= CNT_READ_DELAY + '1' ; CS_SEQ_VEC_I <= "010"; --when SEND_L0 => when "011" => if PT_SELECT = "0001" and (SZ_ACTIVE = '1')then NS_SEQ <= READOUT; NOISE_STOPPED_I <= '1'; elsif PT_SELECT = "0101" then if LFSR < STRESS_L0 and GTU_BUSY = '0' then ISSUE_L0_I <= '1'; NS_SEQ <= WAIT_L1; NS_SEQ_N <= "100"; CNT_L1_DELAY_I <= CNT_L1_DELAY + '1'; else NS_SEQ <= CLEAR; NS_SEQ_N <= "111"; end if; elsif GTU_BUSY = '0' then ISSUE_L0_I <= '1'; NS_SEQ <= WAIT_L1; CNT_L1_DELAY_I <= CNT_L1_DELAY + '1'; else NS_SEQ <= CLEAR; end if; CNT_READ_DELAY_I <= CNT_READ_DELAY + '1' ; CS_SEQ_VEC_I <= "011"; --when WAIT_L1 => when "100" => if PT_SELECT = "0001" and (SZ_ACTIVE = '1')then NS_SEQ <= READOUT; NOISE_STOPPED_I <= '1'; elsif CNT_L1_DELAY = (CNT_L1_LIMIT) then NS_SEQ <= SEND_L1; NS_SEQ_N <= "101"; else CNT_L1_DELAY_I <= CNT_L1_DELAY +'1'; end if; CNT_READ_DELAY_I <= CNT_READ_DELAY + '1' ; CS_SEQ_VEC_I <= "100"; --when SEND_L1 => when "101" => if PT_SELECT = "0101" then if LFSR < STRESS_L1 or L1_OVR_EXT ='1' then ISSUE_L1_I <= '1'; NS_SEQ <= READOUT; NS_SEQ_N <= "110"; else NS_SEQ <= CLEAR; NS_SEQ_N <= "111"; end if; else if L1_TRG = '1' or L1_OVR_EXT = '1' then ISSUE_L1_I <= '1'; NS_SEQ <= READOUT; else NS_SEQ <= CLEAR; end if; end if; if L1_TRG_CTB = '0' and L1_TRG_OVR = '1' then L1_COINC_I <= '1'; end if; TRG_CLEAR_I <= '1'; CNT_READ_DELAY_I <= CNT_READ_DELAY + '1' ; CS_SEQ_VEC_I <= "101"; --when READOUT => when "110" => if GTU_BUSY_DISABLE = '1' or READ_DELAY = '1' then if CNT_READ_DELAY >= CNT_READ_LIMIT and GTU_BUSY = '0' then NS_SEQ <= CLEAR; NS_SEQ_N <= "111"; else CNT_READ_DELAY_I <= CNT_READ_DELAY + '1' ; end if; else if GTU_BUSY = '0' then NS_SEQ <= CLEAR; NS_SEQ_N <= "111"; else null; end if; end if; -- -- -- if CNT_READ_DELAY >= CNT_READ_LIMIT then -- if GTU_BUSY = '0' then -- NS_SEQ <= CLEAR; -- else null; -- --CNT_READ_DELAY_I <= CNT_READ_DELAY + '1'; -- end if; -- else -- CNT_READ_DELAY_I <= CNT_READ_DELAY + '1'; -- end if; -- CS_SEQ_VEC_I <= "110"; --when CLEAR => when "111" => if PT_SELECT = "0011" then NS_SEQ <= IDLE; NS_SEQ_N <= "000"; elsif CNT_CLEAR_DELAY >= (CNT_CLEAR_LIMIT) then NS_SEQ <= IDLE; NS_SEQ_N <= "000"; end if; CNT_CLEAR_DELAY_I <= CNT_CLEAR_DELAY + '1'; CS_SEQ_VEC_I <= "111"; end case; end process; -------------------------- --ZUFALLSZAHLEN - LFSR -------------------------- process (nLBRES, TTC_CLK) begin if nLBRES = '0' then LFSR <= X"12a5f56d"; elsif rising_edge (TTC_CLK) then LFSR <= LFSR (30 downto 0) & (LFSR(31) xnor LFSR(21) xnor LFSR(1) xnor LFSR(0)); end if; end process; ---------------------------------------- --NOISE_VETO: if one of the scintillators fires its activated for 140 cycles (=3.5us) ---------------------------------------- SZ_ACTIVE <= SZ_TOP_RED or SZ_BTM_RED; process (TTC_CLK, nLBRES, SZ_ACTIVE, NOISE_VETO) begin if nLBRES = '0' then NOISE_VETO_CNT <= (others => '0'); NOISE_VETO <= '0'; elsif rising_edge (TTC_CLK) then if SZ_ACTIVE = '1' then NOISE_VETO_CNT <= (others => '0'); NOISE_VETO <= '1'; elsif NOISE_VETO = '1' then if NOISE_VETO_CNT >= X"8c" then --3.5us (driftzeit von ca 3us) NOISE_VETO <= '0'; else NOISE_VETO_CNT <= NOISE_VETO_CNT + 1; end if; else null; end if; end if; end process; ------------------- --GTU BUSY -------------------- --GTU_BUSY_IN <= not B_DIN(10); GTU_BUSY_RE <= GTU_BUSY_IN_R and (not GTU_BUSY_IN_RR); --rising edge GTU_BUSY_FE <= (not GTU_BUSY_IN_R) and GTU_BUSY_IN_RR; --falling edge --process (GTU_BUSY_RE, GTU_BUSY_FE, nLBRES) --begin --if nLBRES ='0' or GTU_BUSY_RE = '1' then -- GTU_BUSY_SYNC <= '1'; --elsif GTU_BUSY_FE = '1' then -- GTU_BUSY_SYNC <= '0'; --end if; --end process; GTU_BUSY_SYNC <= GTU_BUSY_IN_R; --process um gtu_busy zu deaktivieren process (GTU_BUSY_DISABLE, TTC_CLK, GTU_BUSY_SYNC) begin if rising_edge (TTC_CLK) then if GTU_BUSY_DISABLE = '1' then GTU_BUSY <= '0'; else GTU_BUSY <= GTU_BUSY_SYNC; end if; else null; end if; end process; --------------------------------------------------------- --STRESSTEST --> signals with variable frequency (STANDARD: 40MHz -->Stresstest) --------------------------------------------------------- process (TTC_CLK, nLBRES) begin if nLBRES = '0' then CNT_VF <= (others => '0'); elsif rising_edge (TTC_CLK) then if CNT_VF >= CNT_VF_LIMIT then CNT_VF <= (others => '0'); -- ENA_VF <= '1'; KHZ <= '1'; else CNT_VF <= CNT_VF + 1; -- ENA_VF <= '0'; KHZ<= '0'; end if; end if; end process; --------------------------------- --NOISE 1KHz --------------------------------- process (TTC_CLK, nLBRES) begin if nLBRES = '0' then CNT_NOISE <= (others => '0'); elsif rising_edge (TTC_CLK) then if CNT_NOISE >= X"9c8f" then CNT_NOISE <= (others => '0'); NOISE <= '1'; else CNT_NOISE <= CNT_NOISE + 1; NOISE <= '0'; end if; end if; end process; ------------------------------ --SINGLE SHOT - ANY TRIGGER ------------------------------ process (ISSUE_L1_R, nLBRES, SNG_PT, TTC_CLK) begin if nLBRES = '0' or ISSUE_L1_R = '1' then VETO_SINGLE_SM <= '1'; elsif rising_edge(TTC_CLK) and SNG_PT = '1' then VETO_SINGLE_SM <= '0'; end if; end process; -------------------------------------- --SINGLE PRETRIGGER -------------------------------------- SNG_PT <= SNG_PT_NEW and (not SNG_PT_OLD); --is register --> can be written from outside --start and stop of trigger sequence process (nLBRES, SNG_PT_STOP, TTC_CLK, SNG_PT) begin if nLBRES = '0' then SNG_PT_START <= '0'; elsif rising_edge (TTC_CLK) then if SNG_PT_STOP = '1' then SNG_PT_START <= '0'; elsif SNG_PT = '1' then SNG_PT_START <= '1'; --start of trigger sequence else null; end if; end if; end process; --trigger sequence process (nLBRES, SNG_PT_START, TTC_CLK) begin if nLBRES = '0' then SNG_PT_STOP <= '0'; --stop signal SNG_PT_CNT <= X"0000"; --counts time between two PTs SNG_PT_SENT <= X"0000"; --counts sent PT SINGLE_PT <= '0'; --output signal elsif rising_edge (TTC_CLK) then if SNG_PT_START = '0' then SNG_PT_STOP <= '0'; elsif SNG_PT_START = '1' then if SNG_PT_SENT < SNG_PT_TIMES then if SNG_PT_CNT = SNG_PT_CNT_LIMIT then SINGLE_PT <= '1'; SNG_PT_CNT <= X"0000"; SNG_PT_SENT <= SNG_PT_SENT +1; else SNG_PT_CNT <= SNG_PT_CNT +1; SINGLE_PT <= '0'; end if; else SNG_PT_STOP <= '1'; SNG_PT_CNT <= X"0000"; SINGLE_PT <= '0'; SNG_PT_SENT <= X"0000"; end if; end if; end if; end process; --**************************** --COINCIDENCE --**************************** --SYNCED with COINC CLK SZ_T1_FAST <= T1_NOW_FAST and (not T1_LAST_FAST) and MASK(0); SZ_T2_FAST <= T2_NOW_FAST and (not T2_LAST_FAST) and MASK(1); SZ_T3_FAST <= T3_NOW_FAST and (not T3_LAST_FAST) and MASK(2); SZ_T4_FAST <= T4_NOW_FAST and (not T4_LAST_FAST) and MASK(3); SZ_B1_FAST <= B1_NOW_FAST and (not B1_LAST_FAST) and MASK(4); SZ_B2_FAST <= B2_NOW_FAST and (not B2_LAST_FAST) and MASK(5); SZ_B3_FAST <= B3_NOW_FAST and (not B3_LAST_FAST) and MASK(6); SZ_B4_FAST <= B4_NOW_FAST and (not B4_LAST_FAST) and MASK(7); SZ_B5_FAST <= B5_NOW_FAST and (not B5_LAST_FAST) and MASK(8); --TOP and BTM vectors coinc clk SZ_TOP_FAST (0) <= SZ_T1_FAST; SZ_TOP_FAST (1) <= SZ_T2_FAST; SZ_TOP_FAST (2) <= SZ_T3_FAST; SZ_TOP_FAST (3) <= SZ_T4_FAST; SZ_BTM_FAST (0) <= SZ_B1_FAST; SZ_BTM_FAST (1) <= SZ_B2_FAST; SZ_BTM_FAST (2) <= SZ_B3_FAST; SZ_BTM_FAST (3) <= SZ_B4_FAST; SZ_BTM_FAST (4) <= SZ_B5_FAST; --TOP and BTM REDUCED coinc clk SZ_TOP_RED_FAST <= OR_REDUCE(SZ_TOP_FAST); SZ_BTM_RED_FAST <= OR_REDUCE(SZ_BTM_FAST); --synced coinc signal COINC2 <= COINC_FAST_NEW and (not COINC_FAST_OLD); --determined with coinc_clk, synced to ttc_clk --if PDL needed TOP_FAST_PDL <= TOP_FAST; BTM_FAST_PDL <= BTM_FAST; COINC_FAST_SHORT <= BTM_FAST_PDL and TOP_FAST_PDL; --coincidence signal with coinc_clk, length one coinc_clk cycle --Stretch Bottom and Top to be compared for coinicidence process (COINC_CLK, nLBRES, SZ_TOP_RED_FAST) begin if nLBRES='0' then TOP_FAST <= '0'; elsif rising_edge (COINC_CLK) then case TOP_FSM is when SZ_LOW => TOP_FAST <= '0'; TOP_SZ_CNT <= (others =>'0'); if SZ_TOP_RED_FAST = '1' then TOP_FSM <= SZ_HIGH; end if; when SZ_HIGH => TOP_FAST <= '1'; if TOP_SZ_CNT >= SZ_FAST_CNT_LIMIT then --X"a" then TOP_FSM <= SZ_LOW; else TOP_SZ_CNT <= TOP_SZ_CNT + 1; end if; end case; end if; end process; process (COINC_CLK, nLBRES, SZ_BTM_RED_FAST) begin if nLBRES='0' then BTM_FAST <= '0'; elsif rising_edge (COINC_CLK) then case BTM_FSM is when SZ_LOW => BTM_FAST <= '0'; BTM_SZ_CNT <= (others =>'0'); if SZ_BTM_RED_FAST = '1' then BTM_FSM <= SZ_HIGH; end if; when SZ_HIGH => BTM_FAST <= '1'; if BTM_SZ_CNT >= SZ_FAST_CNT_LIMIT then --X"a" then BTM_FSM <= SZ_LOW; else BTM_SZ_CNT <= BTM_SZ_CNT + 1; end if; end case; end if; end process; --strech coinc for sync with 40mhz process (COINC_CLK, nLBRES, COINC_FAST_SHORT) begin if nLBRES='0' then COINC_FAST <= '0'; elsif rising_edge (COINC_CLK) then case COINC_FSM is when SZ_LOW => COINC_FAST <= '0'; COINC_SZ_CNT <= (others =>'0'); if COINC_FAST_SHORT = '1' then COINC_FSM <= SZ_HIGH; end if; when SZ_HIGH => COINC_FAST <= '1'; if COINC_SZ_CNT >= X"a" then COINC_FSM <= SZ_LOW; else COINC_SZ_CNT <= COINC_SZ_CNT + 1; end if; end case; end if; end process; --*********************************** --INTERNAL LOGIC ANALYZER --*********************************** --make all RAM related signal r/w ILA_DATA <= ILA_DATA_I; ILA_RDADDRESS <= ILA_RDADDRESS_I; ILA_WRADDRESS <= ILA_WRADDRESS_I; ILA_WREN <= ILA_WREN_I; ILA_Q_I <= ILA_Q; --DATA WORDS (signals to be recorded) on falling edge of TTC_CLK process (TTC_CLK, nLBRES) begin if nLBRES ='0' then ILA_DATA_I <= (others => '0'); elsif falling_edge( TTC_CLK) then ILA_DATA_I (0) <= SM_OUT; --SZ_BTM_RED; ILA_DATA_I (1) <= GTU_OUT; --ISSUE_PT; ILA_DATA_I (2) <= ISSUE_PT; --ISSUE_L0; ILA_DATA_I (3) <= ISSUE_L0; --ISSUE_L1; ILA_DATA_I (4) <= L1_CTB_IN; --GTU_BUSY; ILA_DATA_I (5) <= L1_CTB_SYNC; --GTU_BUSY_IN; ILA_DATA_I (6) <= ISSUE_L1; --L1_CTB_SYNC; ILA_DATA_I (7) <= GTU_BUSY_IN;--L1_CTB_IN; ILA_DATA_I (8) <= GTU_BUSY; --SZ_TOPSM_OUT; ILA_DATA_I (9) <= SZ_TOP_RED; --GTU_OUT; ILA_DATA_I (10) <= SZ_BTM_RED; --COINC2; ILA_DATA_I (11) <= COINC2; --SZ_TOP_RED; ILA_DATA_I (15 downto 13) <= CS_SEQ_N; ILA_DATA_I (12) <= nLBRES; --SZ_BTM_RED_NOT_SYNCED;--(others => '0'); end if; end process; --WRITE ADDRESS COUNTER -increases by one when wren=1 process (TTC_CLK, nLBRES, ILA_WREN_I) begin if nLBRES = '0' then ILA_WRADDRESS_I <= (others => '0'); elsif falling_edge (TTC_CLK) then if ILA_WREN_I = '1' then ILA_WRADDRESS_I <= ILA_WRADDRESS_I + 1; else null; end if; end if; end process; --sync of register bits ILA_ARM <= ILA_ARM_R and (not ILA_ARM_RR); ILA_VME_DONE <= ILA_VME_DONE_R and (not ILA_VME_DONE_RR); ILA_TRG_MANUAL <= ILA_TRG_REG_R and (not ILA_TRG_REG_RR); --trigger bits ILA_TRG (0) <= ILA_TRG_MANUAL; ILA_TRG (1) <= ISSUE_PT; ILA_TRG (2) <= GTU_SM_OUT_OF_SYNC; ILA_TRG (3) <= ISSUE_L1; ILA_TRG (4) <= COINC2; ILA_TRG (5) <= L1_CTB_SYNC; ILA_TRG (6) <= GTU_BUSY_FE; ILA_TRG (7) <= ISSUE_L0; ILA_TRG (8) <= SZ_BTM_RED; ILA_TRG (9) <= GTU_BUSY_RE; ILA_TRG (10) <= NOISE_STOPPED; ILA_TRG (11) <= '1' when ((GTU_BUSY_FE = '1') and (CS_SEQ_VEC = "000")) else '0'; ILA_TRG (12) <= L1_OVR_I; ILA_TRG (13) <= SM_OUT and SM_OUT_R; ILA_TRG (14) <= CLEAR_TOO_LONG and (not CLEAR_TOO_LONG_R); ILA_TRG (15) <= '0'; process (SM_OUT, GTU_OUT, ISSUE_L1_R, ISSUE_PT) begin if (SM_OUT and ISSUE_L1_R) = (GTU_OUT and ISSUE_PT) then GTU_SM_OUT_OF_SYNC <= '0'; else GTU_SM_OUT_OF_SYNC <= '1'; end if; end process; --clear longer than supposed process (TTC_CLK, CS_SEQ) begin if rising_edge (TTC_CLK) then if CS_SEQ_VEC = "111" then CLEAR_COUNTER <= CLEAR_COUNTER + 1; else CLEAR_COUNTER <= (others => '0'); end if; end if; end process; process (CLEAR_COUNTER) begin if CLEAR_COUNTER >= X"002d" then CLEAR_TOO_LONG <= '1'; else CLEAR_TOO_LONG <= '0'; end if; end process; -------------------------------------- --FSM for ILA -------------------------------------- --current seq process (TTC_CLK, nLBRES) begin if falling_edge (TTC_CLK) then if nLBRES = '0' then ILA_CS <= IDLE; ILA_WREN_I <= '0'; ILA_CNT <= (others => '0'); ILA_COMPLETE <= '0'; ILA_ARM_CNT <= (others => '0'); else ILA_CS <= ILA_NS; ILA_WREN_I <= ILA_WREN_I_I; ILA_CNT <= ILA_CNT_I; ILA_COMPLETE <= ILA_COMPLETE_I; ILA_ARM_CNT <= ILA_ARM_CNT_I; end if; end if; end process; --next seq process (nLBRES, ILA_TRG_MASK, ILA_TRG, ILA_ARM, ILA_VME_DONE, ILA_CS, ILA_CNT, ILA_CNT_LIMIT, ILA_MODE, ILA_ARM_CNT) begin ILA_NS <= ILA_CS; ILA_WREN_I_I <= '0'; ILA_COMPLETE_I <= '0'; ILA_CNT_I <= (others => '0'); ILA_ARM_CNT_I <= (others => '0'); if ILA_CS = IDLE then if ILA_ARM = '1' then ILA_NS <= ARM; end if; elsif ILA_CS = ARM then if ILA_ARM_CNT = X"3ff" then ILA_NS <= ARMED; else ILA_ARM_CNT_I <= ILA_ARM_CNT + 1; end if; ILA_WREN_I_I <= '1'; elsif ILA_CS = ARMED then if (ILA_TRG_MASK and ILA_TRG) /= X"0000" then ILA_NS <= TRIGGERED; end if; ILA_WREN_I_I <= '1'; elsif ILA_CS = TRIGGERED then if ILA_MODE = '0' then --pre-mode ILA_NS <= COMPLETE; ILA_WREN_I_I <= '0'; elsif ILA_MODE = '1' then --post-mode if ILA_CNT = ILA_CNT_LIMIT then ILA_NS <= COMPLETE; ILA_CNT_I <= (others => '0'); ILA_WREN_I_I <= '0'; else ILA_CNT_I <= ILA_CNT + 1; ILA_WREN_I_I <= '1'; end if; end if; elsif ILA_CS = COMPLETE then ILA_COMPLETE_I <= '1'; if ILA_VME_DONE = '1' then ILA_NS <= IDLE; end if; end if; end process; --******************************************************** --COUNTER -- ScINTILLATORS, COINCIDENCE, PT, L0 and L1 --******************************************************** process (nLBRES, TTC_CLK, SZ_T1, CNT_RST_T1, CNT_ENA_T1) begin if nLBRES ='0' or CNT_RST_T1 = '1' then CNT_T1 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_T1 = '1' and SZ_T1 = '1' then CNT_T1 <= CNT_T1 + 1; else null; end if; end process; process (nLBRES, TTC_CLK, SZ_T2, CNT_RST_T2, CNT_ENA_T2) begin if nLBRES ='0' or CNT_RST_T2 = '1' then CNT_T2 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_T2 = '1' and SZ_T2 = '1' then CNT_T2 <= CNT_T2 + 1; else null; end if; end process; process (nLBRES, TTC_CLK, SZ_T3, CNT_RST_T3, CNT_ENA_T3) begin if nLBRES ='0' or CNT_RST_T3 = '1' then CNT_T3 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_T3 = '1' and SZ_T3 = '1' then CNT_T3 <= CNT_T3 + 1; else null; end if; end process; process (nLBRES, TTC_CLK, SZ_T4, CNT_RST_T4, CNT_ENA_T4) begin if nLBRES ='0' or CNT_RST_T4 = '1' then CNT_T4 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_T4 = '1' and SZ_T4 = '1' then CNT_T4 <= CNT_T4 + 1; else null; end if; end process; process (nLBRES, TTC_CLK, SZ_B1, CNT_RST_B1, CNT_ENA_B1) begin if nLBRES ='0' or CNT_RST_B1 = '1' then CNT_B1 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_B1 = '1' and SZ_B1 = '1' then CNT_B1 <= CNT_B1 + 1; else null; end if; end process; process (nLBRES, TTC_CLK, SZ_B2, CNT_RST_B2, CNT_ENA_B2) begin if nLBRES ='0' or CNT_RST_B2 = '1' then CNT_B2 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_B2 = '1' and SZ_B2 = '1' then CNT_B2 <= CNT_B2 + 1; else null; end if; end process; process (nLBRES, TTC_CLK, SZ_B3, CNT_RST_B3, CNT_ENA_B3) begin if nLBRES ='0' or CNT_RST_B3 = '1' then CNT_B3 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_B3 = '1' and SZ_B3 = '1' then CNT_B3 <= CNT_B3 + 1; else null; end if; end process; process (nLBRES, TTC_CLK, SZ_B4, CNT_RST_B4, CNT_ENA_B4) begin if nLBRES ='0' or CNT_RST_B4 = '1' then CNT_B4 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_B4 = '1' and SZ_B4 = '1' then CNT_B4 <= CNT_B4 + 1; else null; end if; end process; process (nLBRES, TTC_CLK, SZ_B5, CNT_RST_B5, CNT_ENA_B5) begin if nLBRES ='0' or CNT_RST_B5 = '1' then CNT_B5 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_B5 = '1' and SZ_B5 = '1' then CNT_B5 <= CNT_B5 + 1; else null; end if; end process; process (nLBRES, TTC_CLK, SZ_TOP_RED, CNT_RST_TOP_RED, CNT_ENA_TOP_RED) begin if nLBRES ='0' or CNT_RST_TOP_RED = '1' then CNT_TOP_RED <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TOP_RED = '1' and SZ_TOP_RED = '1' then CNT_TOP_RED <= CNT_TOP_RED + 1; else null; end if; end process; process (nLBRES, TTC_CLK, SZ_BTM_RED, CNT_RST_BTM_RED, CNT_ENA_BTM_RED) begin if nLBRES ='0' or CNT_RST_BTM_RED = '1' then CNT_BTM_RED <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_BTM_RED = '1' and SZ_BTM_RED = '1' then CNT_BTM_RED <= CNT_BTM_RED + 1; else null; end if; end process; process (nLBRES, COINC2, TTC_CLK, CNT_RST_COINC, CNT_ENA_COINC) begin if nLBRES ='0' or CNT_RST_COINC = '1' then CNT_COINC <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_COINC = '1' and COINC2 = '1' then CNT_COINC <= CNT_COINC + 1; else null; end if; end process; --PT process (nLBRES, ISSUE_PT, TTC_CLK, CNT_RST_TRG, CNT_ENA_TRG) begin if nLBRES ='0' or CNT_RST_TRG = '1' then CNT_PRE <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TRG = '1' and ISSUE_PT = '1' then CNT_PRE <= CNT_PRE + 1; else null; end if; end process; --L0 process (nLBRES, ISSUE_L0, TTC_CLK, CNT_RST_TRG, CNT_ENA_TRG) begin if nLBRES ='0' or CNT_RST_TRG = '1' then CNT_L0 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TRG = '1' and ISSUE_L0 = '1' then CNT_L0 <= CNT_L0 + 1; else null; end if; end process; --L1 process (nLBRES, ISSUE_L1, TTC_CLK, CNT_RST_TRG, CNT_ENA_TRG) begin if nLBRES ='0' or CNT_RST_TRG = '1' then CNT_L1 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TRG = '1' and ISSUE_L1 = '1' then CNT_L1 <= CNT_L1 + 1; else null; end if; end process; --L1_OVR_I process (nLBRES, L1_OVR_I, TTC_CLK, CNT_RST_TRG, CNT_ENA_TRG) begin if nLBRES= '0' or CNT_RST_TRG = '1' then CNT_L1_OVR <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TRG = '1' and L1_OVR_I = '1' then CNT_L1_OVR <= CNT_L1_OVR +1; else null; end if; end process; --L1_COINC -- L1 without L1ctb from GTU process (nLBRES, L1_COINC, TTC_CLK, CNT_RST_TRG, CNT_ENA_TRG) begin if nLBRES = '0' or CNT_RST_TRG = '1' then CNT_L1_COINC <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TRG = '1' and L1_COINC = '1' then CNT_L1_COINC <= CNT_L1_COINC + 1; else null; end if; end process; --**************************************************** --10 Counter for calibration of TREFI Thresholds --Coincidence between one input and other sc. layer --**************************************************** --Control Signals CNT_ENA_TREFI <= CNT_TREFI_CTRL (0); CNT_RST_TREFI <= CNT_TREFI_CTRL (1); --PDL for TOP or BTM process (TTC_CLK, TREFI_BTM_TOP_SELECT) begin if rising_edge (TTC_CLK) then case TREFI_BTM_TOP_SELECT is when '0' => PDL0_IN <= (T1_IN or T2_IN or T3_IN or T4_IN); when '1' => PDL0_IN <= (B1_IN or B2_IN or B3_IN or B4_IN or B5_IN); when others => null; end case; else null; end if; end process; --Coincidence and Sync of Coincidence process (TTC_CLK, nLBRES) begin if nLBRES='0' then TREFI0_NOW <= '0'; TREFI1_NOW <= '0'; TREFI2_NOW <= '0'; TREFI3_NOW <= '0'; TREFI4_NOW <= '0'; TREFI5_NOW <= '0'; TREFI6_NOW <= '0'; TREFI7_NOW <= '0'; TREFI8_NOW <= '0'; TREFI9_NOW <= '0'; TREFI0_LAST <= '0'; TREFI1_LAST <= '0'; TREFI2_LAST <= '0'; TREFI3_LAST <= '0'; TREFI4_LAST <= '0'; TREFI5_LAST <= '0'; TREFI6_LAST <= '0'; TREFI7_LAST <= '0'; TREFI8_LAST <= '0'; TREFI9_LAST <= '0'; elsif rising_edge (TTC_CLK) then TREFI0_NOW <= (not B_DIN(14)) and PDL0_OUT; TREFI1_NOW <= (not B_DIN(15)) and PDL0_OUT; TREFI2_NOW <= (not B_DIN(16)) and PDL0_OUT; TREFI3_NOW <= (not B_DIN(17)) and PDL0_OUT; TREFI4_NOW <= (not B_DIN(18)) and PDL0_OUT; TREFI5_NOW <= (not B_DIN(19)) and PDL0_OUT; TREFI6_NOW <= (not B_DIN(20)) and PDL0_OUT; TREFI7_NOW <= (not B_DIN(21)) and PDL0_OUT; TREFI8_NOW <= (not B_DIN(22)) and PDL0_OUT; TREFI9_NOW <= (not B_DIN(23)) and PDL0_OUT; TREFI0_LAST <= TREFI0_NOW; TREFI1_LAST <= TREFI1_NOW; TREFI2_LAST <= TREFI2_NOW; TREFI3_LAST <= TREFI3_NOW; TREFI4_LAST <= TREFI4_NOW; TREFI5_LAST <= TREFI5_NOW; TREFI6_LAST <= TREFI6_NOW; TREFI7_LAST <= TREFI7_NOW; TREFI8_LAST <= TREFI8_NOW; TREFI9_LAST <= TREFI9_NOW; end if; end process; TREFI0 <= TREFI0_NOW and (not TREFI0_LAST); TREFI1 <= TREFI1_NOW and (not TREFI1_LAST); TREFI2 <= TREFI2_NOW and (not TREFI2_LAST); TREFI3 <= TREFI3_NOW and (not TREFI3_LAST); TREFI4 <= TREFI4_NOW and (not TREFI4_LAST); TREFI5 <= TREFI5_NOW and (not TREFI5_LAST); TREFI6 <= TREFI6_NOW and (not TREFI6_LAST); TREFI7 <= TREFI7_NOW and (not TREFI7_LAST); TREFI8 <= TREFI8_NOW and (not TREFI8_LAST); TREFI9 <= TREFI9_NOW and (not TREFI9_LAST); TREFI_ALL <= TREFI0 or TREFI1 or TREFI2 or TREFI3 or TREFI4 or TREFI5 or TREFI6 or TREFI7 or TREFI8 or TREFI9; process (nLBRES, TREFI0, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI0 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI0 = '1' then CNT_TREFI0 <= CNT_TREFI0 + 1; else null; end if; end process; process (nLBRES, TREFI1, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI1 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI1 = '1' then CNT_TREFI1 <= CNT_TREFI1 + 1; else null; end if; end process; process (nLBRES, TREFI2, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI2 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI2 = '1' then CNT_TREFI2 <= CNT_TREFI2 + 1; else null; end if; end process; process (nLBRES, TREFI3, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI3 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI3 = '1' then CNT_TREFI3 <= CNT_TREFI3 + 1; else null; end if; end process; process (nLBRES, TREFI4, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI4 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI4 = '1' then CNT_TREFI4 <= CNT_TREFI4 + 1; else null; end if; end process; process (nLBRES, TREFI5, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI5 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI5 = '1' then CNT_TREFI5 <= CNT_TREFI5 + 1; else null; end if; end process; process (nLBRES, TREFI6, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI6 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI6 = '1' then CNT_TREFI6 <= CNT_TREFI6 + 1; else null; end if; end process; process (nLBRES, TREFI7, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI7 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI7 = '1' then CNT_TREFI7 <= CNT_TREFI7 + 1; else null; end if; end process; process (nLBRES, TREFI8, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI8 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI8 = '1' then CNT_TREFI8 <= CNT_TREFI8 + 1; else null; end if; end process; process (nLBRES, TREFI9, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI9 <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI9 = '1' then CNT_TREFI9 <= CNT_TREFI9 + 1; else null; end if; end process; process (nLBRES, TREFI_ALL, TTC_CLK, CNT_RST_TREFI, CNT_ENA_TREFI) begin if nLBRES = '0' or CNT_RST_TREFI = '1' then CNT_TREFI_ALL <= (others => '0'); elsif rising_edge(TTC_CLK) and CNT_ENA_TREFI = '1' and TREFI_ALL = '1' then CNT_TREFI_ALL <= CNT_TREFI_ALL + 1; else null; end if; end process; --******************************************************************************** -- USER REGISTERS SECTION --******************************************************************************** ------------------------------ --WRITE REGISTERS ------------------------------ P_WREG : process(LCLK, nLBRES) begin if (nLBRES = '0') then CNT_RST <= X"0000"; CNT_ENA <= X"ffff"; CNT_TRG_CTRL <= X"0001"; MODE <= X"0003"; --disabled CNT_VF_LIMIT <= X"00000000"; --40MHz MASK <= X"FFFF"; SNG_PT_REG <= '0'; SNG_PT_TIMES <= X"0001"; SNG_PT_CNT_LIMIT <= X"0190"; --COUNTER_RST <= '0'; CNT_L0_LIMIT <= X"002e"; --1.12us CNT_L1_LIMIT <= X"013c"; --7.88us CNT_CLEAR_LIMIT <= X"0028"; --1us CNT_READ_LIMIT <= X"4e20"; --500us STRESS_L0 <= X"80000000"; --50% STRESS_L1 <= X"80000000"; --50% STRESS_PT <= X"80000000"; --50% (von 40MHz Signal) SZ_FAST_CNT_LIMIT <= X"0005"; --length of pulses for coincidence - 10ns steps ILA_RDADDRESS_I <= "0000000000"; ILA_ARM_REG <= '0'; ILA_VME_DONE_REG <= '0'; ILA_MODE <= '1'; --post mode default ILA_CNT_LIMIT <= X"0348"; --1000 cycles default --> 24 pre-samples ILA_TRG_MASK <= X"0000"; --all unactive is default CNT_TREFI_CTRL <= X"0000"; TREFI_BTM_TOP_SELECT <= '0'; --CNT_TTC_RST <= '0'; -- A_MASK <= X"FFFFFFFF"; -- Default : Unmasked -- B_MASK <= X"FFFFFFFF"; -- Default : Unmasked -- C_MASK <= X"FFFFFFFF"; -- Default : Unmasked -- GATEWIDTH <= X"0004"; -- Default : -- C_CONTROL <= X"00000000"; -- MODE <= X"0008"; -- Default : I/O Register -- SCRATCH <= X"5A5A"; -- G_CONTROL <= X"00000000"; -- Default : Enable G port / Level=TTL -- D_CONTROL <= X"00000000"; -- Default : Enable D port / Level=TTL -- D_DATA <= X"00000000"; -- E_CONTROL <= X"00000000"; -- Default : Enable E port / Level=TTL -- E_DATA <= X"00000000"; -- F_CONTROL <= X"00000000"; -- Default : Enable F port / Level=TTL -- F_DATA <= X"00000000"; PDL_CONTROL <= X"0003"; -- DLY Buffer DIR = DLY -> FPGA; PDL Write Enabled PDL_DATA <= X"0000"; elsif rising_edge(LCLK) then if (REG_WREN = '1') and (USR_ACCESS = '1') then case REG_ADDR is when A_CNT_RST => CNT_RST <= REG_DIN; when A_CNT_ENA => CNT_ENA <= REG_DIN; when A_CNT_TRG_CTRL => CNT_TRG_CTRL <= REG_DIN; when A_MODE => MODE <= REG_DIN; when A_CNT_VF_LIMIT_H => CNT_VF_LIMIT (31 downto 16) <= REG_DIN; when A_CNT_VF_LIMIT_L => CNT_VF_LIMIT (15 downto 0) <= REG_DIN; when A_MASK => MASK (15 downto 0) <= REG_DIN; when A_SNG_PT_REG => SNG_PT_REG <= REG_DIN (0); when A_SNG_PT_TIMES => SNG_PT_TIMES <= REG_DIN; when A_SNG_PT_CNT_LIMIT => SNG_PT_CNT_LIMIT <= REG_DIN; -- when A_COUNTER_RST => COUNTER_RST <= REG_DIN (0); --wait fuer L0,L1,CLEAR,READOUT(state machine) when A_CNT_L0_LIMIT => CNT_L0_LIMIT <= REG_DIN; when A_CNT_L1_LIMIT => CNT_L1_LIMIT <= REG_DIN; when A_CNT_CLEAR_LIMIT => CNT_CLEAR_LIMIT <= REG_DIN; when A_CNT_READ_LIMIT => CNT_READ_LIMIT <= REG_DIN; --random numbers / stresstest --when A_CNT_TTC_RST => CNT_TTC_RST <= REG_DIN(0); when A_STRESS_L0_H => STRESS_L0 (31 downto 16) <= REG_DIN; when A_STRESS_L0_L => STRESS_L0 (15 downto 0) <= REG_DIN; when A_STRESS_L1_H => STRESS_L1 (31 downto 16) <= REG_DIN; when A_STRESS_L1_L => STRESS_L1 (15 downto 0) <= REG_DIN; when A_STRESS_PT_H => STRESS_PT (31 downto 16) <= REG_DIN; when A_STRESS_PT_L => STRESS_PT (15 downto 0) <= REG_DIN; --coincidence when A_SZ_FAST_CNT_LIMIT => SZ_FAST_CNT_LIMIT (15 downto 0) <= REG_DIN; --ILA when A_ILA_RDADDRESS_I => ILA_RDADDRESS_I (9 downto 0) <= REG_DIN (9 downto 0); when A_ILA_ARM_REG => ILA_ARM_REG <= REG_DIN(0); when A_ILA_VME_DONE_REG => ILA_VME_DONE_REG <= REG_DIN (0); when A_ILA_MODE => ILA_MODE <= REG_DIN(0); when A_ILA_CNT_LIMIT => ILA_CNT_LIMIT <= REG_DIN; when A_ILA_TRG_MASK => ILA_TRG_MASK <= REG_DIN; when A_ILA_TRG_REG => ILA_TRG_REG <= REG_DIN (0); --TREFI when A_CNT_TREFI_CTRL => CNT_TREFI_CTRL <= REG_DIN (15 downto 0); when A_TREFI_BTM_TOP_SELECT => TREFI_BTM_TOP_SELECT <= REG_DIN (0); -- when A_AMASK_L => A_MASK(15 downto 0) <= REG_DIN; -- when A_AMASK_H => A_MASK(31 downto 16) <= REG_DIN; -- when A_BMASK_L => B_MASK(15 downto 0) <= REG_DIN; -- when A_BMASK_H => B_MASK(31 downto 16) <= REG_DIN; -- when A_CMASK_L => C_MASK(15 downto 0) <= REG_DIN; -- when A_CMASK_H => C_MASK(31 downto 16) <= REG_DIN; -- when A_GATEWIDTH => GATEWIDTH <= REG_DIN; -- when A_CCTRL_L => C_CONTROL(15 downto 0) <= REG_DIN; -- when A_CCTRL_H => C_CONTROL(31 downto 16) <= REG_DIN; -- when A_MODE => MODE <= REG_DIN; -- when A_SCRATCH => SCRATCH <= REG_DIN; -- when A_GCTRL => G_CONTROL(15 downto 0) <= REG_DIN; -- when A_DCTRL_L => D_CONTROL(15 downto 0) <= REG_DIN; -- when A_DCTRL_H => D_CONTROL(31 downto 16) <= REG_DIN; -- when A_DDATA_L => D_DATA (15 downto 0) <= REG_DIN; -- when A_DDATA_H => D_DATA (31 downto 16) <= REG_DIN; -- when A_ECTRL_L => E_CONTROL(15 downto 0) <= REG_DIN; -- when A_ECTRL_H => E_CONTROL(31 downto 16) <= REG_DIN; -- when A_EDATA_L => E_DATA (15 downto 0) <= REG_DIN; -- when A_EDATA_H => E_DATA (31 downto 16) <= REG_DIN; -- when A_FCTRL_L => F_CONTROL(15 downto 0) <= REG_DIN; -- when A_FCTRL_H => F_CONTROL(31 downto 16) <= REG_DIN; -- when A_FDATA_L => F_DATA (15 downto 0) <= REG_DIN; -- when A_FDATA_H => F_DATA (31 downto 16) <= REG_DIN; when A_PDL_CTRL => PDL_CONTROL <= REG_DIN; when A_PDL_DATA => PDL_DATA <= REG_DIN; when others => null; end case; end if; end if; end process; -- READ REGISTERS P_RREG: process(LCLK, nLBRES) begin if (nLBRES = '0') then REG_DOUT <= X"BEEF"; elsif rising_edge(LCLK) then if (REG_RDEN = '1') and (USR_ACCESS = '1') then case REG_ADDR is when A_CNT_T1_H => REG_DOUT <= CNT_T1 (31 downto 16); when A_CNT_T1_L => REG_DOUT <= CNT_T1 (15 downto 0); when A_CNT_T2_H => REG_DOUT <= CNT_T2 (31 downto 16); when A_CNT_T2_L => REG_DOUT <= CNT_T2 (15 downto 0); when A_CNT_T3_H => REG_DOUT <= CNT_T3 (31 downto 16); when A_CNT_T3_L => REG_DOUT <= CNT_T3 (15 downto 0); when A_CNT_T4_H => REG_DOUT <= CNT_T4 (31 downto 16); when A_CNT_T4_L => REG_DOUT <= CNT_T4 (15 downto 0); when A_CNT_B1_H => REG_DOUT <= CNT_B1 (31 downto 16); when A_CNT_B1_L => REG_DOUT <= CNT_B1 (15 downto 0); when A_CNT_B2_H => REG_DOUT <= CNT_B2 (31 downto 16); when A_CNT_B2_L => REG_DOUT <= CNT_B2 (15 downto 0); when A_CNT_B3_H => REG_DOUT <= CNT_B3 (31 downto 16); when A_CNT_B3_L => REG_DOUT <= CNT_B3 (15 downto 0); when A_CNT_B4_H => REG_DOUT <= CNT_B4 (31 downto 16); when A_CNT_B4_L => REG_DOUT <= CNT_B4 (15 downto 0); when A_CNT_B5_H => REG_DOUT <= CNT_B5 (31 downto 16); when A_CNT_B5_L => REG_DOUT <= CNT_B5 (15 downto 0); when A_TOPR_H => REG_DOUT <= CNT_TOP_RED (31 downto 16); when A_TOPR_L => REG_DOUT <= CNT_TOP_RED (15 downto 0); when A_BTMR_H => REG_DOUT <= CNT_BTM_RED (31 downto 16); when A_BTMR_L => REG_DOUT <= CNT_BTM_RED (15 downto 0); when A_CNT_COINC_H => REG_DOUT <= CNT_COINC (31 downto 16); when A_CNT_COINC_L => REG_DOUT <= CNT_COINC (15 downto 0); -- --abstaende PT - L1 -- when A_COUNTER01 => REG_DOUT <= COUNTER01 (15 downto 0); -- when A_COUNTER02 => REG_DOUT <= COUNTER02 (15 downto 0); -- when A_COUNTER03 => REG_DOUT <= COUNTER03 (15 downto 0); -- when A_COUNTER04 => REG_DOUT <= COUNTER04 (15 downto 0); -- when A_COUNTER05 => REG_DOUT <= COUNTER05 (15 downto 0); -- when A_COUNTER06 => REG_DOUT <= COUNTER06 (15 downto 0); -- when A_COUNTER07 => REG_DOUT <= COUNTER07 (15 downto 0); -- when A_COUNTER08_H => REG_DOUT <= COUNTER08 (31 downto 16); -- when A_COUNTER08_L => REG_DOUT <= COUNTER08 (15 downto 0); -- when A_COUNTER09 => REG_DOUT <= COUNTER09 (15 downto 0); -- when A_COUNTER10 => REG_DOUT <= COUNTER10 (15 downto 0); -- when A_COUNTER11 => REG_DOUT <= COUNTER11 (15 downto 0); -- when A_COUNTER12 => REG_DOUT <= COUNTER12 (15 downto 0); -- when A_COUNTER13 => REG_DOUT <= COUNTER13 (15 downto 0); -- when A_COUNTER14 => REG_DOUT <= COUNTER14 (15 downto 0); -- when A_COUNTER15 => REG_DOUT <= COUNTER15 (15 downto 0); -- when A_COUNTER16 => REG_DOUT <= COUNTER16 (15 downto 0); -- when A_COUNTER17 => REG_DOUT <= COUNTER17 (15 downto 0); -- when A_COUNTER18 => REG_DOUT <= COUNTER18 (15 downto 0); -- when A_COUNTER19 => REG_DOUT <= COUNTER19 (15 downto 0); -- when A_COUNTER20 => REG_DOUT <= COUNTER20 (15 downto 0); -- when A_COUNTER21_H => REG_DOUT <= COUNTER21 (31 downto 16); -- when A_COUNTER21_L => REG_DOUT <= COUNTER21 (15 downto 0); -- when A_COUNTER_MAX => REG_DOUT <= COUNTER_MAX (15 downto 0); -- when A_COUNTER_MIN => REG_DOUT <= COUNTER_MIN (15 downto 0); --zufallszahlen -- when A_CNT_LFSR_H1 => REG_DOUT <= CNT_LFSR_H (31 downto 16); -- when A_CNT_LFSR_H2 => REG_DOUT <= CNT_LFSR_H (15 downto 0); -- when A_CNT_LFSR_L1 => REG_DOUT <= CNT_LFSR_L (31 downto 16); -- when A_CNT_LFSR_L2 => REG_DOUT <= CNT_LFSR_L (15 downto 0); when A_MODE => REG_DOUT <= MODE (15 downto 0); when A_CNT_RST => REG_DOUT <= CNT_RST (15 downto 0); when A_CNT_ENA => REG_DOUT <= CNT_ENA (15 downto 0); when A_CNT_TRG_CTRL => REG_DOUT <= CNT_TRG_CTRL (15 downto 0); when A_MASK => REG_DOUT <= MASK (15 downto 0); --zaehler PT,L0,L1,L1_OVR when A_CNT_PRE_H => REG_DOUT <= CNT_PRE (31 downto 16); when A_CNT_PRE_L => REG_DOUT <= CNT_PRE (15 downto 0); when A_CNT_L0_H => REG_DOUT <= CNT_L0 (31 downto 16); when A_CNT_L0_L => REG_DOUT <= CNT_L0 (15 downto 0); when A_CNT_L1_H => REG_DOUT <= CNT_L1 (31 downto 16); when A_CNT_L1_L => REG_DOUT <= CNT_L1 (15 downto 0); when A_CNT_L1_OVR_H => REG_DOUT <= CNT_L1_OVR (31 downto 16); when A_CNT_L1_OVR_L => REG_DOUT <= CNT_L1_OVR (15 downto 0); when A_CNT_L1_COINC_H => REG_DOUT <= CNT_L1_COINC (31 downto 16); when A_CNT_L1_COINC_L => REG_DOUT <= CNT_L1_COINC (15 downto 0); --ILA when A_ILA_Q_I => REG_DOUT <= ILA_Q_I (15 downto 0); when A_ILA_RDADDRESS_I => REG_DOUT <= "000000" & ILA_RDADDRESS_I; when A_ILA_WRADDRESS_I => REG_DOUT <= "000000" & ILA_WRADDRESS_I; when A_ILA_ARM_REG => REG_DOUT <= X"000" & "000" & ILA_ARM; when A_ILA_VME_DONE_REG => REG_DOUT <= X"000" & "000" & ILA_VME_DONE; when A_ILA_MODE => REG_DOUT <= X"000" & "000" & ILA_MODE; when A_ILA_CNT_LIMIT => REG_DOUT <= ILA_CNT_LIMIT; when A_ILA_COMPLETE => REG_DOUT <= X"000" & "000" & ILA_COMPLETE; when A_ILA_TRG_MASK => REG_DOUT <= ILA_TRG_MASK; when A_ILA_TRG_REG => REG_DOUT <= X"000" & "000" & ILA_TRG_REG; --timings state machine when A_CNT_L0_LIMIT => REG_DOUT <= CNT_L0_LIMIT; when A_CNT_L1_LIMIT => REG_DOUT <= CNT_L1_LIMIT; when A_CNT_READ_LIMIT => REG_DOUT <= CNT_READ_LIMIT; when A_CNT_CLEAR_LIMIT => REG_DOUT <= CNT_CLEAR_LIMIT; when A_CNT_CLEAR_DELAY => REG_DOUT <= CNT_CLEAR_DELAY; when A_CNT_CLEAR_DELAY_I => REG_DOUT <= CNT_CLEAR_DELAY_I; when A_CS_SEQ_N => REG_DOUT <= "0000000000000" & CS_SEQ_N; when A_NS_SEQ_N => REG_DOUT <= "0000000000000" & NS_SEQ_N; --stresstest when A_STRESS_L0_H => REG_DOUT <= STRESS_L0 (31 downto 16); when A_STRESS_L0_L => REG_DOUT <= STRESS_L0 (15 downto 0); when A_STRESS_PT_H => REG_DOUT <= STRESS_PT (31 downto 16); when A_STRESS_PT_L => REG_DOUT <= STRESS_PT (15 downto 0); when A_STRESS_L1_H => REG_DOUT <= STRESS_L1 (31 downto 16); when A_STRESS_L1_L => REG_DOUT <= STRESS_L1 (15 downto 0); when A_CNT_VF_LIMIT_H => REG_DOUT <= CNT_VF_LIMIT (31 downto 16); when A_CNT_VF_LIMIT_L => REG_DOUT <= CNT_VF_LIMIT (15 downto 0); --TREFI when A_CNT_TREFI0 => REG_DOUT <= CNT_TREFI0 (15 downto 0); when A_CNT_TREFI1 => REG_DOUT <= CNT_TREFI1 (15 downto 0); when A_CNT_TREFI2 => REG_DOUT <= CNT_TREFI2 (15 downto 0); when A_CNT_TREFI3 => REG_DOUT <= CNT_TREFI3 (15 downto 0); when A_CNT_TREFI4 => REG_DOUT <= CNT_TREFI4 (15 downto 0); when A_CNT_TREFI5 => REG_DOUT <= CNT_TREFI5 (15 downto 0); when A_CNT_TREFI6 => REG_DOUT <= CNT_TREFI6 (15 downto 0); when A_CNT_TREFI7 => REG_DOUT <= CNT_TREFI7 (15 downto 0); when A_CNT_TREFI8 => REG_DOUT <= CNT_TREFI8 (15 downto 0); when A_CNT_TREFI9 => REG_DOUT <= CNT_TREFI9 (15 downto 0); when A_CNT_TREFI_ALL => REG_DOUT <= CNT_TREFI_ALL (15 downto 0); -- when A_ASTATUS_L => REG_DOUT <= A_STATUS (15 downto 0); -- when A_ASTATUS_H => REG_DOUT <= A_STATUS (31 downto 16); -- when A_BSTATUS_L => REG_DOUT <= B_STATUS (15 downto 0); -- when A_BSTATUS_H => REG_DOUT <= B_STATUS (31 downto 16); -- when A_CSTATUS_L => REG_DOUT <= C_STATUS (15 downto 0); -- when A_CSTATUS_H => REG_DOUT <= C_STATUS (31 downto 16); -- when A_SCRATCH => REG_DOUT <= SCRATCH; -- when A_DCTRL_L => REG_DOUT <= D_CONTROL(15 downto 0); -- when A_DCTRL_H => REG_DOUT <= D_CONTROL(31 downto 16); -- when A_DDATA_L => REG_DOUT <= D_DIN (15 downto 0); -- when A_DDATA_H => REG_DOUT <= D_DIN (31 downto 16); -- when A_ECTRL_L => REG_DOUT <= E_CONTROL(15 downto 0); -- when A_ECTRL_H => REG_DOUT <= E_CONTROL(31 downto 16); -- when A_EDATA_L => REG_DOUT <= E_DIN (15 downto 0); -- when A_EDATA_H => REG_DOUT <= E_DIN (31 downto 16); -- when A_FCTRL_L => REG_DOUT <= F_CONTROL(15 downto 0); -- when A_FCTRL_H => REG_DOUT <= F_CONTROL(31 downto 16); -- when A_FDATA_L => REG_DOUT <= F_DIN (15 downto 0); -- when A_FDATA_H => REG_DOUT <= F_DIN (31 downto 16); -- when A_REVISION => REG_DOUT <= REVISION; when A_PDL_CTRL => REG_DOUT <= PDL_CONTROL; when A_PDL_DATA => REG_DOUT <= X"00" & PDL_READ; -- when A_DIDCODE => REG_DOUT <= X"000" & '0' & D_IDCODE; -- when A_EIDCODE => REG_DOUT <= X"000" & '0' & E_IDCODE; -- when A_FIDCODE => REG_DOUT <= X"000" & '0' & F_IDCODE; when others => REG_DOUT <= X"BEEF"; end case; end if; end if; end process; END rtl;