Quick SCSN
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Autor: Thomas Janson, 2009

Description:
The ACEX-Card acts as SCSN Master.
There are two rings r0 and r1. The Master sends in r0/r1 a SCSN frame and reads back on output ( r0_in -> r0_out, r1_in -> r1_out ).
If the ring is broken, you will get an error ( tester reports as TIMEOUT ... ).

CHECK THE SCSN CONNECTORS FIRST!!

Reason:
On of these rings is broken ( of course ).
This can be 
  bad soldering, 
  broken wire bond,
  one of the MCM is tot or
  one of the voltage regulator is bad.

MCM is tot:
If a MCM is total dead, there will not be a PLL Clock output signal, so the problem is in the PLL Clock output tree.


The way you encircle the error may differ and is also depending whats wrong.
Take a look on the SCSN tree and use the testers SCSN bridge test to find out where the ring is broken. The SCSN tree and the structure how the MCMs are provided with current gives you information about the kind of error. The same about the PLL Clock tree. So first you have to understand the basic working of the board.
The SCSN tree and PLL clock tree is documented on WIKI. Information about the SCSN frame may be found in TRAP USER Manual.

           -------      -------            -------
out r0 <--| slv18 |<---| slv17 |<-- ... --| slv1  |<-- in r0
          |       |    |       |          |       |
in r1  -->| slv1  |--->| slv2  |-- ... -->| slv18 |--> out r1
           -------      -------            -------
Board Type T1A,T1B,T2B,T4A,T4B has 18 slaves. r0:slv1 and r1:slv18 is the external MCM on tester!!
Board Type T3A,T3B has 21 slaves. r0:slv1,slv2,slv3 and r1:slv21,slv20,slv19 are the external MCMs on tester!!

Quick SCSN test: ping through r0 from in to out. If the line is broken, you will see a timeout.
ping into r0_in: answering from out_r0
ping into r1_in: answering from out_r1
To find out where the ring is broken, you have to do the SCSN bridge test.

SCSN bridge test: the tester sets MCM by MCM into bridge mode and reports until the SCSN bus is ok.

                        bridged!
           -------      -------            -------
out r0 <--| slv18 |<---|<-| |--|<-- ... --| slv1  |<-- in r0
          |       |    |  | |  |          |       |
in r1  -->| slv1  |--->|--| |->|-- ... -->| slv18 |--> out r1
           -------      -------            -------