/**************************************/ /* ALICE TRD */ /* Read-out board */ /* SCSN Configuration File */ /* */ /* 2004-03-08 */ /* Jan de Cuveland, Venelin Angelov */ /**************************************/ // Svn $Id$: // // Readout tree (logical view) // // 00 01 -0> 02 <3- 03 // `--------1/ \----------, // | // 04 05 -0> 06 <3- 07 2 // `--------1/ \--------0,| // || // 16 --> // 08 09 -0> 10 <3- 11 || // `--------1/ \--------1´| // | // 12 13 -0> 14 <3- 15 3 // `--------1/ \----------´ // ************************************* // Common parameters // ************************************* // some timing settings // w/r // 11 - fastest, 00 - slowest write ARBTIM, arbiter_timing write DMDELA, dmem_delayA write DMDELS, dmem_delayS write MEMCOR, hamming_imem | (hamming_dmem << 4) | (HAMMDB << 8); // set to 0x00 for ADC readout or to 0x1E for test data readout //write EBAQA, 0x00; // already set in filter.tcs! //write TPCBY, 0 // ------------------------ // set constant registers // ------------------------ // Event Counter, con12 write C12CPUA,1; // the counting starts from 1 // Number of Samples, c13 write C13CPUA,nsamples // Tracklet & Raw Data End Marker write NES, (nsig_rr << 16) | nsig_tr // ------------------------- // set int entry addresses // ------------------------- write IA0+IRQ_CLR, lbl_CLR_cpu0; // set int_clr start addr for cpu0 write IA1+IRQ_CLR, lbl_CLR_cpu1; // set int_clr start addr for cpu1 write IA2+IRQ_CLR, lbl_CLR_cpu2; // set int_clr start addr for cpu2 write IA3+IRQ_CLR, lbl_CLR_cpu3; // set int_clr start addr for cpu3 write IA0+IRQ_ACQ, lbl_ACQ_cpu0; // set int_acq start addr for cpu0 write IA1+IRQ_ACQ, lbl_ACQ_cpu1; // set int_acq start addr for cpu1 write IA2+IRQ_ACQ, lbl_ACQ_cpu2; // set int_acq start addr for cpu2 write IA3+IRQ_ACQ, lbl_ACQ_cpu3; // set int_acq start addr for cpu3 write IA0+IRQ_RAW, lbl_RAW_cpu0; // set int_raw start addr for cpu0 write IA1+IRQ_RAW, lbl_RAW_cpu1; // set int_raw start addr for cpu1 write IA2+IRQ_RAW, lbl_RAW_cpu2; // set int_raw start addr for cpu2 write IA3+IRQ_RAW, lbl_RAW_cpu3; // set int_raw start addr for cpu3 write IA0+IRQ_TST, lbl_LPW_cpu0; // set int_clr start addr for cpu0 write IA1+IRQ_TST, lbl_LPW_cpu1; // set int_clr start addr for cpu0 write IA2+IRQ_TST, lbl_LPW_cpu2; // set int_clr start addr for cpu0 write IA3+IRQ_TST, lbl_LPW_cpu3; // set int_clr start addr for cpu0 // --------------- // set int masks // --------------- write IRQHW0, irq_msk; // set irq_hw mask for cpu0 write IRQHL0, irq_msk; // set irq_hl mask cor cpu0 write IRQHW1, irq_msk; // set irq_hw mask for cpu1 write IRQHL1, irq_msk; // set irq_hl mask cor cpu1 write IRQHW2, irq_msk; // set irq_hw mask for cpu2 write IRQHL2, irq_msk; // set irq_hl mask cor cpu2 write IRQHW3, irq_msk; // set irq_hw mask for cpu3 write IRQHL3, irq_msk; // set irq_hl mask cor cpu3 // -------------------------------- // NI transmission delay // -------------------------------- // for 50:50 here the number of 32 bit words send by each CPU. // delay between ni_ctrl and end marker, this is c11 of cpu3, set to 0 for no delay write C08CPU3, delay_ni; // const8 write IA3+IRQ_NI+2, lbl_NIFIFOE_cpu3; // start address irq_ni for fifo empty write NBND, 0xF001; // thresholds fifo write IA3+IRQ_TM, lbl_LOCALTM_cpu3; // start address counter/timer // -------------------------------- // configure global state machine // -------------------------------- write SML0, LTIME0 | (ignore_L0R << 14); // the time for L0 accept write SML2, LTIME2 | (ignore_L1R << 14); // the actual L1 time write SML1, LTIME1 | (1 << 14); // the time to start the raw data readout, a little bit later write ADCPAR, adc_power_backgr | (adc_az_backgr << 3) | (adc_enibf_backgr << 4) | (adc_power_pretr << 5) | (adc_az_pretr << 8) | (adc_enibf_pretr << 9) | (adc_smp_phase << 10) | (adc_irq_phase << 14); write ADCMSK, 0x1FFFFF write ADCINB, 10b; // invert bits write ADCDAC, ADCDAC_value; // ADC DAC 5-bit // ------------------------- // configure clock control // ------------------------- write CPU0CLK, 0x1F; write CPU1CLK, 0x1F; write CPU2CLK, 0x1F; write CPU3CLK, 0x1F; // ----------------------------- // configure network interface // ----------------------------- // NI output excludes and ctrl delay // root(bit14) and oase(bit15) flags are cleared write NED , (0 << 15) | (0 << 14) | (t_parit_bit << 10) | (t_false_bit << 6) | (t_ctrl_delay << 3) | t_strb_delay; write NDLY, (t_data_delay0) | (t_data_delay1 << 3) | (t_data_delay2 << 6) | (t_data_delay3 << 9) | (t_data_delay4 << 12) | (t_data_delay5 << 15) | (t_data_delay6 << 18) | (t_data_delay7 << 21) | (t_data_delay8 << 24) | (t_data_delay9 << 27); write NP0, (t_parit_bit << 7) | (t_false_bit << 3) | 4; write NP1, (t_parit_bit << 7) | (t_false_bit << 3) | 4; write NP2, (t_parit_bit << 7) | (t_false_bit << 3) | 4; write NP3, (t_parit_bit << 7) | (t_false_bit << 3) | 4; // set NI trigger readout order write NTRO, niro_nm; write NRRO, niro_nm; //write NITM0, 0x01D0+30; // 0x153; // NI timer 0 (clock) write NITM0, nsamples*12+50; //write NITM0, 0x3FFF; //write NITM1, 0x01E2; // 0x165; // NI timer 1 (IO data) write NIP4D, 0x03; // delays write NICLK, 0x1F; write NIODE, 11011b; write NIOCE, 0x1F; write NIIDE, 0x02; write NIICE, 0x1F; // ************************************* // Specific configuration // ************************************* // ************************************* // Normal chips, no merger // ************************************* // switching the unused pre & clk & ni ports off of the normal chips write chip0 , SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip1 , SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip3 , SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip4 , SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip5 , SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip7 , SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip8 , SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip9 , SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip11, SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip12, SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip13, SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip15, SMMODE, (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; // Boundary chips, mask unused ADC channels (and edge pads with high noise) restrict MASK_BOUNDARY_ADCS write chip_a_side | chip0 , ADCMSK, 0x07FFFF write chip_a_side | chip4 , ADCMSK, 0x07FFFF write chip_a_side | chip8 , ADCMSK, 0x07FFFF write chip_a_side | chip12 , ADCMSK, 0x07FFFF write chip_b_side | chip3 , ADCMSK, 0x1FFFF8 write chip_b_side | chip7 , ADCMSK, 0x1FFFF8 write chip_b_side | chip11 , ADCMSK, 0x1FFFF8 write chip_b_side | chip15 , ADCMSK, 0x1FFFF8 restrict 1 // ************************************* // Column mergers readout order // ************************************* write chip2, NTRO, niro_cm; write chip6, NTRO, niro_cm; write chip10, NTRO, niro_cm; write chip14, NTRO, niro_cm; write chip2, NRRO, niro_cm; write chip6, NRRO, niro_cm; write chip10, NRRO, niro_cm; write chip14, NRRO, niro_cm; write chip2 , SMMODE, (1011b << 12) | (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip6 , SMMODE, (1011b << 12) | (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip10, SMMODE, (1011b << 12) | (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; write chip14, SMMODE, (1011b << 12) | (smmode_simflag << 11) | (smmode_eod2cpu << 4) | smmode_delta; // ************************************* // Board mergers // ************************************* // Tracklet readout order write chip_bm, NTRO, niro_bm; // set NI raw data readout order write chip_bm, NRRO, niro_bm; write chip_bm, ADCMSK, 0; write chip_bm, SMMODE, (1111b << 12) | (smmode_eod2cpu << 4) | smmode_delta; write chip_bm, C08CPU3, 0; // const8, delay ni not necessary if no data // ************************************* // Half-chamber mergers // ************************************* write chip_hm, NED, (0 << 15) | (1 << 14) | (m_parit_bit << 10) | (m_false_bit << 6) | (m_ctrl_delay << 3) | m_strb_delay; write chip_hm, NDLY, (m_data_delay0) | (m_data_delay1 << 3) | (m_data_delay2 << 6) | (m_data_delay3 << 9) | (m_data_delay4 << 12) | (m_data_delay5 << 15) | (m_data_delay6 << 18) | (m_data_delay7 << 21) | (m_data_delay8 << 24) | (m_data_delay9 << 27); write chip_hm, NTRO, niro_hm4; write chip_hm, NRRO, niro_hm4; write chip_hm4, NTRO, niro_hm4; write chip_hm4, NRRO, niro_hm4; write chip_hm3, NTRO, niro_hm3; write chip_hm3, NRRO, niro_hm3; write chip_hm, NIODE, 10b; write chip_hm, NIOCE, 0x01; write chip_hm, NIIDE, 0x07; write chip_hm, NIICE, 0x07; // ADC off //write chip_hm, ADCEN, 0; write chip_hm, ADCMSK, 0; write chip_hm, SMMODE, (1111b << 12) | (smmode_eod2cpu << 4) | smmode_delta; write chip_hm, C08CPU3, 0; // const8, delay ni not necessary if no data // Chip Position (ROB specific soon) board_no = 2; chip_rob = 0; // here for sinlge ROB dummy hc_0_SM_sector_nr = 8; // 5 bits, 0..17 hc_0_plane_nr = 1; // 3 bits, 0..5 hc_0_chamber_nr = 1; // 3 bits, 0..4 hc_0_side_chamber = 1; // 1 bits, 0..1 const HC_0 = (hc_0_raw_ver_spec_nr << 29) | (hc_0_raw_ver_maj_nr << 22) | (hc_0_raw_ver_min_nr << 15) | (hc_0_add_hd_words << 12) | (hc_0_SM_sector_nr << 7) | (hc_0_plane_nr << 4) | (hc_0_chamber_nr << 1) | hc_0_side_chamber; // VA-TMP!!! const HC_0DT = (hc_0_raw_ver_spec_nr << 29) | ( (hc_0_raw_ver_maj_nr | (1 << 4) ) << 22) | (hc_0_raw_ver_min_nr << 15) | (hc_0_add_hd_words << 12) | (hc_0_SM_sector_nr << 7) | (hc_0_plane_nr << 4) | (hc_0_chamber_nr << 1) | hc_0_side_chamber; include src/write_mcmid.tcs write chip_bm, C14CPUA, 0; // send nothing write chip_hm, C14CPUA, (1100b << 16); // send hc header 0 and 1 // VA-TMP!!! write C15CPUA, HC_0; // for all MCMs //write C15CPUA, HC_0DT; // for all MCMs //write chip2, C15CPUA, HC_0; // for all MCMs // EBIS, EBIT, EBIL, EBIN exist in filter.tcs, the values are in parameters.tcs! // clear the low power counters, beginning of IMEM restrict 1 write 0xF0E8, 0 write 0xF0EA, 0 write 0xF0EC, 0 write 0xF0EE, 0 // clear the low power counters, end of IMEM write 0xF0E9, 0 write 0xF0EB, 0 write 0xF0ED, 0 write 0xF0EF, 0 restrict 1 // Configure Global Counter sel_inp = 0; // external ext_sel = 2; // pretriger decoded (1) write CTGCTRL, 0xE1F | (sel_inp << 5) | (ext_sel << 7); write CTGDINI, 0; LP_REP = 0xF0E4 write LP_REP , 0xDEAD0 write LP_REP+1, 0xDEAD1 write LP_REP+2, 0xDEAD2 write LP_REP+3, 0xDEAD3 restrict ADC2CPU one_adc_one_mcm_dec = 0; one_adc_one_mcm = 1; two_adcs_two_mcms = 0; two_adcs_one_mcm = 0; include src/adc2cpu.tcs restrict 1; // for cosmic trigger: set the thresholds: write C10CPU3, (COSMIC_Q_SHR & 0x0007) | ((COSMIC_MIN_HITS & 0x001F) << 3) | ((COSMIC_Q_THR & 0xFFFF) << 8); write 0xC028, 0x40000000 write 0xC029, 40 write 0xC02A, 0x40000000 write 0xC02B, 0x200*4