/**************************************/
/* ALICE TRD                          */
/* Read-out board                     */
/* SCSN Configuration File            */
/*                                    */
/* 2004-03-08                         */
/* Jan de Cuveland, Venelin Angelov   */
/**************************************/

// ----------------------------
//  define SCSN IDs for ring 0
// ----------------------------
include src/scsn_ids.tcs

// TRAP definitions
include src/defines.tcs
include src/parameters.tcs

restrict 1-SIMULATION
// optional for simulation
include src/position.tcs
restrict 1

restrict smmode_simflag
chipTK = 127;
mask = 0;
basel = 9;
earladc = 0;
secadc = 0;
lateadc = 0;
cadc = basel;
secch = 0;
include src/TRAP_EB_init.tcs
chipTK = chip0;
mask = 1;
secadc = 0;
earladc = 9;
lateadc = 9;
secch = 100;
include src/TRAP_EB_init.tcs

restrict 1


include wrk/cpu0_labels.tcs
include wrk/cpu1_labels.tcs
include wrk/cpu2_labels.tcs
include wrk/cpu3_labels.tcs


include src/filter.tcs

include src/main.tcs



//restrict 1-SIMULATION
// reset ORI again
write chip_mode, SEBDEN, 11b;
write chip_jtag, SEBDEN, 111b;
write chip_mode2, SEBDEN, 0;
write chip_jtag2, SEBDEN, 0;
write chip_mode, SEBDOU, mode_rstn;
//wait 1000;
write chip_mode, SEBDOU, mode_jtag;
restrict 1

restrict USE_J2C
include src/j2c_init.tcs
restrict 1


pretrigger 5
expect 127, 0x0A04, 0x300000a0


// Temporary

write  chip3,  ADCMSK, 0x1FFFFF
//write  chip3,  ADCMSK, 0

restrict PASAPULSE
write           C11CPU3,        0;               // const11
//////// Some shift
write PASAPRA, 0x30; // min: 0x00, max: 0x3F
write PASAPHA, 9
write PASADAC, pasa_pulse_height
write PASACHM, 0x55555
//write PASACHM, 0xAAAAA
//write chip2, PASACHM, (1 << 10)
write PASACHM, (1 << 18); // | (1 << 7) | (1 << 11) | (1 << 15)
//write PASACHM, 0
write PASACHM, 0x7FFFF
//write chip1, PASACHM, (1 << 2); // | (1 << 7) | (1 << 11) | (1 << 15)
write PASACHM, 0
write chip5, PASACHM, (1 << 18)
write PASAPR1, 0
// start once
write PASAPR1, 1
wait 100
// clear
pretrigger 2
write PASAPR1, 0
write PASAPR1, 1
wait 100
write PASAPR1, 0
// clear
pretrigger 2
write           C11CPU3,        delay_ni;               // const11
write           C12CPUA,1; // the counting starts from 1
// In PASA Pulse mode the pretrigger counters in chips can not start siumultaneously because
// they will be first synchronized with the slow clock
// Note that in the normal pretrigger mode this is not the case!
// So, only in case of PASA Pulse we need the NI control signals permanently enabled.
// This leads to about 140 mA more /ROB.
restrict 0;
write chip_hm,  NIOCE,  0x01;
write chip_bm,  NIOCE,  0x01;

write chip_bm,  NIICE,  0x01;
write chip_hm,  NIICE,  0x01;

write chip2  ,  NIICE,  0x01;
write chip6  ,  NIICE,  0x01;
write chip10 ,  NIICE,  0x01;
write chip14 ,  NIICE,  0x01;
write chip2  ,  NIOCE,  0x01;
write chip6  ,  NIOCE,  0x01;
write chip10 ,  NIOCE,  0x01;
write chip14 ,  NIOCE,  0x01;
restrict 1;
//write ADCMSK, 0
//write FPCL, 0
write FPCL, 1

restrict 0
// CM without CPUs
//write chip6,    NITM2, LTIME1+20;
write chip6,    ADCMSK, 0;      // => mask all ADCs, may be not very necessary
// bits 15..12 are port enables for NI ports 3..0.
//      - 1011b is the normal mask for a column merger
// bit 11 is simulation flag, in this case is don't care
// bit 10 is no CPU flag and must be set
// bit 9 is merger only flag, this disables the ADCs and the slow clock (10MHz)
// bits 8..4 is the number of samples, as the preprocessor is not running, this must be set here.
//      - note that here stays actually nsamples+1 !!!
write chip6,    SMMODE, (1011b << 12) | (0 << 11) | (0 << 10) | (1 << 9) | ((nsamples+1) << 4) | smmode_delta;
// the order in the NI ports now without the own data
write chip6,    NTRO, 0x3fe19;  // => NI order  1 0 3
write chip6,    NRRO, 0x3fe19;  // => NI order  1 0 3
//
// if some more MCMs in the same column need to be excluded from the readout tree, please
// adjust NTRO, NRRO and bits 15..12 in SMMODE !!!
//
write chip6,    CPU0CLK, 0;     // => turn off all CPUs permanently
write chip6,    CPU1CLK, 0;
write chip6,    CPU2CLK, 0;
write chip6,    CPU3CLK, 0;
write chip6,    IRQHW0, 0;      // => disable all IRQs
write chip6,    IRQHL0, 0;
write chip6,    IRQHW1, 0;
write chip6,    IRQHL1, 0;
write chip6,    IRQHW2, 0;
write chip6,    IRQHL2, 0;
write chip6,    IRQHW3, 0;
write chip6,    IRQHL3, 0;
write chip6,    FILCLK, 0;
write chip6,    PRECLK, 0;
write chip6,    NIICE, 1;       // => permanently on
write chip7,    NIOCE, 1;
restrict 1
//write ADCMSK, 0