ROB_1A=0;
ROB_1B=0;
ROB_2B=0;
ROB_3A=0;
ROB_3B=0;
ROB_4A=0;
ROB_4B=0;
MCM   =0;
WAFER =0;

ROB_1A=1;
HAMMIM=0;
HAMMDM=0;
HAMMDB=0;

EXTENDED=0;
SINGLEROB=1;



/////////////////////////////////////////////////////////////////////
//
// scsn_ids.tcs for ROB Tester / 03.2006 JM
//
// *** IMPORTANT: The lines above are modified automatically by PVSS.
// 
// If necessary, those lines can be edited accordingly (see below):
//
//
// From the types below, one of them must be set, EITHER to 0 or 1:
// ROB_1A=0; // 0 or 1
// ROB_1B=0; // 0 or 1
// ROB_2B=0; // 0 or 1
// ROB_3A=0; // 0 or 1
// ROB_3B=0; // 0 or 1
// ROB_4A=0; // 0 or 1
// ROB_4B=0; // 0 or 1
// MCM   =0; // 0 or 1
// WAFER =0; // 0 or 1
//
// Select the hamming correction ON/OFF (0/1)
// HAMMIM=0;
// HAMMDM=0;
// HAMMDB=0;
// 
// *********************  DO NOT MODIFY BELOW!  *********************
//
/////////////////////////////////////////////////////////////////////

//EXTENDED=1; // 1 for extended setup (3A/3B), 0 for single ROB
//SINGLEROB=0;
SIMULATION=0; // Used for ROB_ORI
FULLROB=1;    // Used for ROB_ORI
scsn_shift_T3=3; // 3 for extended setup (3A/3B), 0 for single ROB
scsn_shift=1; // 1 for extended setup (1A,1B,2B,4A,4B), 0 for singleROB
 
// ----------------------------------------------------------
//  define SCSN IDs for ring 0 (ALICE numbering v.s. SCSN ID)
// ----------------------------------------------------------

ROB = ROB_1A | ROB_1B | ROB_2B | ROB_3A | ROB_3B | ROB_4A | ROB_4B

restrict ROB

const chip_hm3    = 00001000100b; // Half chamber merger on C0 chamber
const chip_hm4    = 00000000000b; // Half chamber merger on C1 chamber

const chip_a_side = 0;
const chip_b_side = 0;


restrict ROB_1A | ROB_4A
const chip0  =  10+scsn_shift;
const chip1  =  11+scsn_shift;
const chip2  =  12+scsn_shift; // merger
const chip3  =  13+scsn_shift;
const chip4  =  09+scsn_shift;
const chip5  =  16+scsn_shift;
const chip6  =  15+scsn_shift; // merger
const chip7  =  14+scsn_shift;
const chip8  =  08+scsn_shift;
const chip9  =  06+scsn_shift;
const chip10 =  07+scsn_shift; // merger
const chip11 =  01+scsn_shift;
const chip12 =  05+scsn_shift;
const chip13 =  04+scsn_shift;
const chip14 =  03+scsn_shift; // merger
const chip15 =  02+scsn_shift;
const chip_bm = 17+scsn_shift;
const chip_hm = scsn_shift;
 
restrict ROB_1B | ROB_2B | ROB_4B
const chip0  =  11+scsn_shift;
const chip1  =  12+scsn_shift;
const chip2  =  13+scsn_shift; // merger
const chip3  =  14+scsn_shift;
const chip4  =  10+scsn_shift;
const chip5  =  17+scsn_shift;
const chip6  =  16+scsn_shift; // merger
const chip7  =  15+scsn_shift;
const chip8  =  09+scsn_shift;
const chip9  =  07+scsn_shift;
const chip10 =  08+scsn_shift; // merger
const chip11 =  02+scsn_shift;
const chip12 =  06+scsn_shift;
const chip13 =  05+scsn_shift;
const chip14 =  04+scsn_shift; // merger
const chip15 =  03+scsn_shift;
const chip_bm = 01+scsn_shift;
const chip_hm = scsn_shift;
 
restrict ROB_3A
//  SCSN = ID in Ivan's document - "18", not 17 !!
const chip0  =  10+scsn_shift_T3;
const chip1  =  11+scsn_shift_T3;
const chip2  =  12+scsn_shift_T3; // merger
const chip3  =  13+scsn_shift_T3;
const chip4  =  09+scsn_shift_T3;
const chip5  =  16+scsn_shift_T3;
const chip6  =  15+scsn_shift_T3; // merger
const chip7  =  14+scsn_shift_T3;
const chip8  =  08+scsn_shift_T3;
const chip9  =  06+scsn_shift_T3;
const chip10 =  07+scsn_shift_T3; // merger
const chip11 =  01+scsn_shift_T3;
const chip12 =  05+scsn_shift_T3;
const chip13 =  04+scsn_shift_T3;
const chip14 =  03+scsn_shift_T3; // merger
const chip15 =  02+scsn_shift_T3;
const chip_bm = 18+scsn_shift_T3; // board merger
const chip_hm = 17+scsn_shift_T3; // half chamber merger

restrict ROB_3B
const chip0  =  12+scsn_shift_T3;
const chip1  =  13+scsn_shift_T3;
const chip2  =  14+scsn_shift_T3; // merger
const chip3  =  15+scsn_shift_T3;
const chip4  =  11+scsn_shift_T3;
const chip5  =  18+scsn_shift_T3;
const chip6  =  17+scsn_shift_T3; // merger
const chip7  =  16+scsn_shift_T3;
const chip8  =  10+scsn_shift_T3;
const chip9  =  08+scsn_shift_T3;
const chip10 =  09+scsn_shift_T3; // merger
const chip11 =  03+scsn_shift_T3;
const chip12 =  07+scsn_shift_T3;
const chip13 =  06+scsn_shift_T3;
const chip14 =  05+scsn_shift_T3; // merger
const chip15 =  04+scsn_shift_T3;
const chip_bm = 02+scsn_shift_T3; // board merger
const chip_hm = 01+scsn_shift_T3; // half chamber merger

restrict EXTENDED
const chip19 = 01;
const chip20 = 02;
const chip21 = 03;

restrict ROB
// if 0 - for single chip
const  type=1

// 1 for single chip, 2 for the new MCM tester, 127 for the ROB
const dut = 127;
const scheck = 2;

restrict ROB_3A | ROB_3B
const chip_mode  = chip11; // main chip
const chip_mode2 = chip15; // the alternative
const chip_jtag  = chip7;  // main chip
const chip_jtag2 = chip3;  // alternative

restrict 1 - (ROB_3A | ROB_3B)
const chip_mode  = 99; // not present
const chip_jtag  = 99; // not present
const chip_mode2 = 99; // not present
const chip_jtag2 = 99; // not present

restrict MCM

// 1 for ROB, 0 for single chip of GIOtst
const type = 0;

// 1 for single chip, 2 for the new MCM tester, 3 for the wafer tester, 127 for the ROB
const fpga2 = 1;
const fpga1 = 2;
const dut = 2;
const ni0 = 3;
const ni1 = 4;
const ni2 = 5;
const ni3 = 6;
const scheck =2;

restrict WAFER
// 1 for ROB, 0 for single chip of GIOtst
const type = 0;

// 1 for single chip, 2 for the new MCM tester, 3 for the wafer tester, 127 for the ROB
const fpga2 = 1;
const fpga1 = 2;
const dut = 3;
const scheck = 3;


// For ORI test:

restrict ROB_3A | ROB_3B
const dutOri = chip_hm; // for ROB=17, for single chip = 1
//const chip_mode  = chip15; // for ROB =1, for single chip is jumper
//const chip_jtag  = chip7; // for ROB=13, for single chip = 1

restrict 1 - (ROB_3A | ROB_3B)
//const chip_mode  = 99; // not present
//const chip_jtag  = 99; // not present

restrict 1

//USE_J2C = 1;