include scsn_ids.tcs

restrict ROB_1A | ROB_1B | ROB_2B | ROB_3A | ROB_3B | ROB_4A | ROB_4B

reset

write chip_bm, SEBDEN, 7
write chip_bm, SEBDOU, 0
write chip_bm, SEBDOU, 7

// switching the unused pre & clk & ni ports off
// normal chips 2, 6, 10, 14
write chip0 , SMMODE, 0x00E2
write chip1 , SMMODE, 0x00E2
write chip3 , SMMODE, 0x00E2
//
write chip4 , SMMODE, 0x00E2
write chip5 , SMMODE, 0x00E2
write chip7 , SMMODE, 0x00E2
//
write chip8 , SMMODE, 0x00E2
write chip9 , SMMODE, 0x00E2
write chip11, SMMODE, 0x00E2
//
write chip12, SMMODE, 0x00E2
write chip13, SMMODE, 0x00E2
write chip15, SMMODE, 0x00E2
//
// column merger chips
write chip2 , SMMODE, 0xB0E2
write chip6 , SMMODE, 0xB0E2
write chip10, SMMODE, 0xB0E2
write chip14, SMMODE, 0xB0E2
//


restrict MCM

const scsn_sw = 0x4400;
// reset
write fpga2, scsn_sw, 0;
write fpga2, scsn_sw, 0;
reset
write fpga2, 0x4420
write fpga2, 0x4430
// not practical for simulation!
write scsn_sw, 4; // fpga2+dut only
reset
nop
nop
// reset test DUT
write  dut,   0x0A00, 0x0BCD
expect dut,   0x0A00, 0x0BCD
write  fpga2, 0x4430, 0; // hardware reset
expect dut,   0x0A00, 0x4050
write  dut,   0x0A00, 0x0BCD
expect dut,   0x0A00, 0x0BCD
reset dut; // scsn reset
expect dut,   0xA00,  0x4050
// reset dut
wait 20;
nop;
// switching the unused pre & clk & ni ports off
write dut, SMMODE, 0xE2
//

restrict WAFER

const scsn_sw = 0x4400;
// specific for the wafer tester
const rst_inv = 0; // must be 0 if no additional reset inverter is soldered
const rst_opend = 1; // if open drain the pull up in the TRAP can be measured.

// reset
write scsn_sw, 0; // fpga2 only
reset;  // FPGA only
wait 20;
write scsn_sw, 7; // fpga2-fpga1-WDUT
// here the reset output config of the fpga1
write fpga1, 0x6000, (rst_inv << 8) | (rst_opend << 9);
// exclude and parity bits in FPGA design, reset conf and reset read back
// check if the pull up of the reset is seen
expect fpga1, 0x6000, (rst_inv << 8) | (rst_opend << 9) | (1 << 10);
// not practical for simulation!
// reset test DUTq
//write  fpga1, 0x6003, 0; // here the timeout in scsn is an additional indication for the reset in TRAP!
reset dut
expect dut,   0x0A00, 0x4050
write  dut,   0x0A00, 0x0BCD
expect dut,   0x0A00, 0x0BCD
write  fpga1, 0x6003, 0; // here the timeout in scsn is an additional indication for the reset in TRAP!
reset dut
expect dut,   0xA00,  0x4050
// reset dut
wait 20;
nop;
// switching the unused pre & clk & ni ports off
// normal chips 2, 6, 10, 14
write dut, SMMODE, 0xE2

// COMMON TO ALL

restrict 1

// reduce power
write NICLK,  0;
write NIODE,  0;
write NIOCE,  0;
write NIIDE,  0;
write NIICE,  0;
write ADCEN,  0;
write PRECLK, 0;
//write ADCMSK, 0;
write SADCAZ, 1

// some timing settings
//            w/r
// 11 - fastest, 00 - slowest
write ARBTIM, 1101b
write DMDELA, 2
write DMDELS, 15
// enable/disable hamming correction
hamming_imem = HAMMIM | (HAMMIM << 1) | (HAMMIM << 2) | (HAMMIM << 3);
hamming_dmem = HAMMDM | (HAMMDM << 1) | (HAMMDM << 2) | (HAMMDM << 3);
write MEMCOR, hamming_imem | (hamming_dmem << 4) | (HAMMDB << 8);