// ***************************************************************************
// Program parameters
// ***************************************************************************

const PASAPULSE=0;
const USE_J2C = 0;

// hc header field, some of them used in the normal chips!
hc_0_raw_ver_spec_nr = 1; // 1 bit = const 1
hc_0_add_hd_words    = 2; // 3 bits  0..2 implemented!!!

ZSon     = 0;    // 1 or 0
TCKL_DIS = 0;    // 1 or 0
TST_PATT = 0;    // 1 or 0
ADC2CPU  = 0;

// Test pattern # or options for ZS
// in ZS mode, OPT[0] disables sending of MCM header followed by an empty ADC Mask
//             OPT[2..1] = 1,2,3: send every 128/256/1024 event without suppression
// In test patter mode, OPT means;
// 0 : counter/rob/mcm/cpu
// 1 : pseudorandom gen 10bit for ADC data
// 2 : evncnt( 6)/sector+1(5)/chamber+1(3)/plane+1(3)/rob(3)/mcm(4)/cpu(2)/cnt++
// 3 : evncnt(12)/sector+1(5)/chamber+1(3)/plane+1(3)/rob(3)/mcm(4)/cpu(2)
// in non-ZS, non-TP mode, OPT[0] enables calculating the ADC statistics
OPT      = 1;    // 0..7

// the major version is used in the assembler program
hc_0_raw_ver_maj_nr = (TST_PATT << 6) | (ZSon << 5) | (TCKL_DIS << 4) | (OPT << 0);
hc_0_raw_ver_min_nr = 0; // unused in the assembler program

// PASA Pulser Setup (0 to 255)
const pasa_pulse_height = 255;

const ROW = 0; // used for the tables of Jan

const root_all = 0;

const dmem_delayA =  2;         // Nominal:2  used in DMDELA
const dmem_delayS = 15;         // Nominal:15 used in DMDELS

const arbiter_timing = 1101b;

// Parts of the configuration register SMMODE
const smmode_delta   = 10;      // 4 bit, window for L0A, L1A
const smmode_eod2cpu =  8;      // 5 bit, end of drift time to CPU on delay
const smmode_simflag =  0;      // 1 bit, simulation flag used to replay the ADC data from EB

// Parts of the configuration register SM0..2
const ignore_L0R = 1;
const ignore_L1R = 1;

const LTIME0 = 0x0050-(smmode_delta >> 1);     // 14-bit, used for L0A/R

//const LTIME1 = 0x02BC+300;                     // 14-bit, used to start the raw data readout
const LTIME1 = 0x02BC+000;                     // 14-bit, used to start the raw data readout
//const LTIME1 = 0x02FC;                         // 14-bit, used to start the raw data readout
//const LTIME2 = 0x0230-(smmode_delta >> 1);     // 14-bit, used for L1A/R
//const LTIME2 = LTIME1-10;
const LTIME2 = 0x0230-(smmode_delta >> 1);     // 14-bit, used for L1A/R

// enable/disable hamming correction used in MEMCOR
hamming_imem = HAMMIM | (HAMMIM << 1) | (HAMMIM << 2) | (HAMMIM << 3);
hamming_dmem = HAMMDM | (HAMMDM << 1) | (HAMMDM << 2) | (HAMMDM << 3);

// Enable/Disable the filter stages
// 1/0 enable/disable the corresponding filter or correction
const EnableNonlinearity=0;             // 1/0 enable/disable the corresponding
const EnablePedestal=1;                 // filter or correction
const EnableGainCorrection=1;
const EnableTailCancellation=0;
const EnableXtalkSuppression=0;

// Preprocessor and filter parameters

const nsamples  =  30;                  // Number of samples, used in many registers
const ADCdatapipe = 5;                  // 0 to 5, used in EBD register, 2 are already in the Crosstalk filter
const ADCraw = 0;                       // 0 or 1, store the filtered(0) or unfiltered(1) ADC data, used in EBSF
// Indicators for marking the ADC samples for raw readout
const EBSingleIndicatorThreshold=2;     // used in EBIS, in ADC units above the pedestal
const EBSumIndicatorThreshold=4;        // used in EBIT, in ADC units above the pedestal
const EBIndicatorLookupTable=0xF0;      // see the TRAP user manual, used in EBIL
const EBmarkIgnoreNeighbour=1;          // used in EBIN
// Fit interval
const PrepLinearFitStart=5;             // used in TPFS
const PrepLinearFitEnd=20;              // used in TPFE
// Charge accumulators
const PrepQacc0Start=0;                 // Preprocessor Charge Accumulator 0 Start
const PrepQacc0End=10;                  // Preprocessor Charge Accumulator 0 End
const PrepQacc1Start=11;                // Preprocessor Charge Accumulator 1 Start
const PrepQacc1End=20;                  // Preprocessor Charge Accumulator 1 End
// Hit detection
const MinClusterCharge=20;              // in ADC units

// Tail cancellation filter parameters
//const LongDecayWeight=98;
//const LongDecayParameter=330;
//const ShortDecayParameter=3;
//const TailF0=1+EnableTailCancellation;  // The DC responce of the filter, must be calculated
//                                        // later using the decay parameters

const LongDecayWeight=270;              // 0 to 1024 corresponds to 0 to 0.5
const LongDecayParameter=348;           // 0 to 511 corresponds to 0.75 to 1
const ShortDecayParameter=449;          // 0 to 511 correponds to 0.25 to 0.5
const TCAttenuationParameter=45/14;      // = -alphaL/ln(lambdaL)-(1-alphaL)/ln(lambdaS)
const TailF0=1+EnableTailCancellation*(-1+TCAttenuationParameter);   // 1 if TC off


// Crosstalk Filter Parameters
const XtalkM0=0x1E * EnableXtalkSuppression;    // not expected to be used actually
const XtalkM1=0xD4 * EnableXtalkSuppression;
const XtalkM2=0xE6 * EnableXtalkSuppression;
const XtalkM3=0x4A * EnableXtalkSuppression;
const XtalkM4=0xEF * EnableXtalkSuppression;
const XtalkF0=1;                        // The DC responce of the filter, must be calculated
                                        // in case of filter usage!
                                        // This is correct only when Xtalk disabled!
// Pedestal filter parameters
const PedestalTimeConstant=0;           // 0 for fastest, 3 for slowest
const EffectPedestal=30;                // in ADC units the desired baseline
// The baseline at the output of the pedestal filter, it is still not the final!
//const FPNPvalue=4*EffectPedestal*TailF0*XtalkF0*(9-EnableGainCorrection)/9;
const FPNPvalue=4*EffectPedestal;
//const GainPedestalIni=4*EffectPedestal*TailF0*XtalkF0*EnableGainCorrection*1/9;
const GainPedestalIni=0;

// ADC parameters, IRQ, sampling phase, en inp buffer, autozero, power
const adc_power_backgr = 2; // 0..7   = p
const adc_power_pretr  = 2; // 0..7   = h
const adc_irq_phase    = 6; // 0..11  = i
const adc_smp_phase    = 2; // 0..11  = s
const adc_enibf_backgr = 0; // 0 or 1 = e
const adc_enibf_pretr  = 0; // 0 or 1 = b
const adc_az_backgr    = 0; // 0 or 1 = a
const adc_az_pretr     = 0; // 0 or 1 = z
const ADCDAC_value     = 00000b; // 5 bit
const MASK_BOUNDARY_ADCS=1;

const irq_msk = (1 << IRQ_ACQ) | (1 << IRQ_CLR) | (1 << IRQ_RAW) | (1 << IRQ_TST);

// ****************************************
// READOUT TREE parameters
// ****************************************

// End signature for NI port
const nsig_tr = 0x1000;         // used in the assembler program and in
//const nsig_tr = 0xaaaa;         // used in the assembler program and in
const nsig_rr = 0x0000;         // the configuration register NES

// Temporary slow down the readouttree, put 0 to disable it
const delay_ni  = nsamples*21*2/3*121/125; // for long data transmission
//const delay_ni  = 0;
//const delay_ni  = nsamples*21*2/3*120/125/6; // for 1 ROB
// nsamples/3 is the number of 32 bit words per ADC
// *21 adcs, *2 to get 16-bit words
// *120/125 as the TRAP works at 120 MHz and ORI at 125 MHz
// this is the time in CPU clock for the data transmission
// and we want to wait the same time


// Readout tree on all boards except for half-chamber merger

//  00    01 -0> 02 <3- 03
//    `--------1/ \----------,
//                           |
//  04    05 -0> 06 <3- 07   2
//    `--------1/ \--------0,|
//                          ||
//                          16 -->
//  08    09 -0> 10 <3- 11  ||
//    `--------1/ \--------1´|
//                           |
//  12    13 -0> 14 <3- 15   3
//    `--------1/ \----------´

// Here one can see the connectivity of the readout tree.
// For example MCM00 sends its data to NI input port 1 of the column merger MCM02,
// its output goes to NI input port 2 of the board merger MCM16.

// Readout tree on the boards with half-chamber mergers

//  00    01 -0> 02 <3- 03
//    `--------1/ \----------,
//                           |
//  04    05 -0> 06 <3- 07   2
//    `--------1/ \--------0,|
//                          ||
//                          16 -- 3->17->ORI
//  08    09 -0> 10 <3- 11  ||
//    `--------1/ \--------1´|
//                           |
//  12    13 -0> 14 <3- 15   3
//    `--------1/ \----------´
//
// Readout order for the CM-mergers: p1 -> p0 -> p4 -> p3, here p4 means the own data
// Readout order for the BM-mergers: p2 -> p0 -> p1 -> p3

// readout order configuration constants
const niro_nm     = 0x0003fffc; // for normal chips, send only own data

// 1 -> 0 -> own -> 3
const niro_cm     = 0x0001fe21; // for column merger chips

restrict FULLROB
const niro_bm     = 0x000170cc; // 4 2 0 1 3
//const niro_bm     = 0x0003f0ca; // 2 0 1 3
//const niro_bm     = 0x19e4; // 4 3 1 0 2
//const niro_bm     = 0x39e13; // 3 1 0 2

restrict (1-FULLROB)
const niro_bm     = 0x00017ffc; // own -> 2, used in simulation normally

restrict 1
// C0 chamber
//
//                  ---------       ---------       ---------
//                  |  2:0  |       |  1:0  |       |  0:0  |
//                  |  BM   |       |       |       |       |
//                  |  p3   |<-p1---|       |-------|--BM   |  Side A
//                  |  HCM  |<-p0---|--BM   |       |       |
//                  |  T3A  |       |  T1A  |       |  T1A  |
//                  ---------       ---------       ---------
//                      4               2               0
//
//
//                  ---------       ---------       ---------
//                  |  2:1  |       |  1:1  |       |  0:1  |
//                  |  BM   |       |       |       |       |
//                  |  p3   |<-p1---|       |-------|--BM   |  Side B
//                  |  HCM  |<-p0---|--BM   |       |       |
//                  |  T3B  |       |  T2B  |       |  T1B  |
//                  ---------       ---------       ---------
//                      5               3               1
//
// Readout order for the HC-mergers: p1 -> p0 -> p3
// own -> 1 -> 0 -> 3
const niro_hm3    = 0x0000fe1c; // for half-chamber merger chips sending header as own data

// C1 chamber
//
//  ---------       ---------       ---------       ---------
//  |  3:0  |       |  2:0  |       |  1:0  |       |  0:0  |
//  |       |       |  BM   |       |       |       |       |
//  |       |       |  p3   |<-p1---|       |-------|--BM   |  Side A
//  |   BM--|--p2-> |  HCM  |<-p0---|--BM   |       |       |
//  |  T4A  |       |  T3A  |       |  T1A  |       |  T1A  |
//  ---------       ---------       ---------       ---------
//      6               4               2               0
//
//
//  ---------       ---------       ---------       ---------
//  |  3:1  |       |  2:1  |       |  1:1  |       |  0:1  |
//  |       |       |  BM   |       |       |       |       |
//  |       |       |  p3   |<-p1---|       |-------|--BM   |  Side B
//  |   BM--|--p2-> |  HCM  |<-p0---|--BM   |       |       |
//  |  T4B  |       |  T3B  |       |  T2B  |       |  T1B  |
//  ---------       ---------       ---------       ---------
//     7                5               3               1
//
restrict (1-SINGLEROB)
// Readout order for the HC-mergers: p1 -> p0 -> p3 -> p2
// own -> 1 -> 0 -> 3 -> 2
const niro_hm4    = 0x0000ae1c; // for half-chamber merger chips sending header as own data

restrict SINGLEROB
// own -> 3, used only in single ROB configuration
const niro_hm4    = 0x0001fffc; // for half-chamber merger chips sending header as own data

restrict 1

// ***************************
// TRAP => TRAP delay and exclude parameters
// ***************************
const t_data_delay  = 2; // if strobe delay is 0, here should work with 1..3 and minor errors at 0 at 4
// individual delays, normally we don't need to use different values here
const t_data_delay0 = t_data_delay;
const t_data_delay1 = t_data_delay;
const t_data_delay2 = t_data_delay;
const t_data_delay3 = t_data_delay;
const t_data_delay4 = t_data_delay;
const t_data_delay5 = t_data_delay;
const t_data_delay6 = t_data_delay;
const t_data_delay7 = t_data_delay;
const t_data_delay8 = t_data_delay;
const t_data_delay9 = t_data_delay;

const t_strb_delay = 0; // 0, better not to change, actually the difference data_delay-strb_delay is important
const t_ctrl_delay = 0; // 0..7 not used between the TRAPs

// this is only the default configuration and will be changed individually if necessary!
const t_false_bit  = 8; // 0..9
const t_parit_bit  = 9; // 0..9

// ***************************
// Last merger => ORI delay and exclude parameters
// ***************************
const m_data_delay = 2; // 1..4, 2 and 3 work for sure
// individual delays, normally we don't need to use different values here
const m_data_delay0 = m_data_delay;
const m_data_delay1 = m_data_delay;
const m_data_delay2 = m_data_delay;
const m_data_delay3 = m_data_delay;
const m_data_delay4 = m_data_delay;
const m_data_delay5 = m_data_delay;
const m_data_delay6 = m_data_delay;
const m_data_delay7 = m_data_delay;
const m_data_delay8 = m_data_delay;
const m_data_delay9 = m_data_delay;

const m_strb_delay = 0; // 0
const m_ctrl_delay = 0; // 0..7 not used at all, only in the case of OASE chip but not in ORI

// this is only the default configuration and will be changed if necessary!
const m_false_bit  = 8; // 0..9
const m_parit_bit  = 9; // 0..9

const mode_jtag = 01b;
const mode_rstn = 00b;
const mode_i2c  = 11b;

reg_j2c = m_parit_bit | (m_false_bit << 4);

// IO addresses to communucate with any service program
const srv_command = 0xF0E0; // for the code of the operation and if enough for in/out data
const srv_indata  = 0xF0E1; // for input data, stored by the SCSN master
const srv_outdata = 0xF0F0; // for output data, stored by the TRAP program

// I2C devices
i2c_addr_ltc = 0x14;    // LTC chip
i2c_addr_eep = 0xAE;    // serial EEPROM chip
eep_write_time = 2000;  // us timedelay after write

lp_state = 0x020;
fault_ltc = 1;
eeprom_offs_addr = 0x60; // for 2401, for 2400 is not important
eeprom_offs_addr_ser = 0;
eeprom_offs_addr_PI  = 0x10;
ver_cpld = 8;