// ADC mask
restrict SIMULATION
write ADCMSK, 0;
restrict 1
//
//
//
//
//-------------------------------------------------------------------------------
//
// Preprocessor / Event Buffer
//
//-------------------------------------------------------------------------------
//
// Common Timer Delay -- Do not change due to NI LVDS timing
write TPPT0, 0x00;
//
// Event Buffer Data Acquisition End
write TPPAE, nsamples+3; // was 0x21; SIMULATE !!!
//
// Response Time to GSM
write TPPGR, nsamples+2; // TPPAE - 1
//
// Event Buffer Input Delay
write EBD, ADCdatapipe; // 0 to 5
//
// Event Buffer Storage Mode
write EBSF, ADCraw;
//
// Event Buffer Acquisition Offset Address
write EBAQA, 0;
//
// Event Buffer Simulation Mode
write EBSIM, 1-smmode_simflag; // active low
//
// Event Buffer Simulation Offset Address
write EBSIA, 0x20;              // start address for ADC read data in simulation mode
//
// Event Buffer Parity Bit Mask
write EBPP, 1; // 0 for parity bit enable, 1 for mask
//
restrict ADCraw; // store raw data case
// Event Buffer Single Indicator Threshold
write EBIS, 0
//
// Event Buffer Sum Indicator Threshold
write EBIT, 0
//

restrict 1-ADCraw; // store filtered ADC data case
// Event Buffer Single Indicator Threshold
write EBIS, EBSingleIndicatorThreshold+EffectPedestal;
//
// Event Buffer Sum Indicator Threshold
write EBIT, EBSumIndicatorThreshold+EffectPedestal;

restrict 1;

//
// Event Buffer Indicator Look-up Table
write EBIL, EBIndicatorLookupTable; //  0xF0;
//
// Event Buffer Indicator Neighbor Sensitivity
write EBIN, EBmarkIgnoreNeighbour;
//
// Preprocessor Linear Fit Start
write TPFS, PrepLinearFitStart; //  5;
//
// Preprocessor Linear Fit End
write TPFE, PrepLinearFitEnd; //  20;
//
// Preprocessor Charge Accumulator 0 Start
write TPQS0, PrepQacc0Start;
//
// Preprocessor Charge Accumulator 0 End
write TPQE0, PrepQacc0End; //  10;
//
// Preprocessor Charge Accumulator 1 Start
write TPQS1, PrepQacc1Start;
//
// Preprocessor Charge Accumulator 1 End
write TPQE1, PrepQacc1End;
//
// Cluster Charge Threshold (reset value 160, best about 232 with FPNP=60)
write TPHT, 3*4*EffectPedestal+4*MinClusterCharge;
//
// Cluster Verification Bypass
write TPVBY, 0;
//
// Cluster Qualitiy Threshold
write TPVT, 0;
//
// Filtered Pedestal
write TPFP, 4*EffectPedestal;
//
//-------------------------------------------------------------------------------
//
// Filter: Nonlinearity Correction
//
//-------------------------------------------------------------------------------
//
// Bypass
write FLBY, EnableNonlinearity;
//
restrict EnableNonlinearity;
// Look Up Table
write FLL+0x00, 0x20*EnableNonlinearity;
write FLL+0x01, 0x23*EnableNonlinearity;
write FLL+0x02, 0x26*EnableNonlinearity;
write FLL+0x03, 0x29*EnableNonlinearity;
write FLL+0x04, 0x2C*EnableNonlinearity;
write FLL+0x05, 0x2E*EnableNonlinearity;
write FLL+0x06, 0x31*EnableNonlinearity;
write FLL+0x07, 0x33*EnableNonlinearity;
write FLL+0x08, 0x36*EnableNonlinearity;
write FLL+0x09, 0x38*EnableNonlinearity;
write FLL+0x0A, 0x3A*EnableNonlinearity;
write FLL+0x0B, 0x3B*EnableNonlinearity;
write FLL+0x0C, 0x3D*EnableNonlinearity;
write FLL+0x0D, 0x3E*EnableNonlinearity;
write FLL+0x0E, 0x3E*EnableNonlinearity;
write FLL+0x0F, 0x3F*EnableNonlinearity;
write FLL+0x10, 0x3F*EnableNonlinearity;
write FLL+0x11, 0x3F*EnableNonlinearity;
write FLL+0x12, 0x3E*EnableNonlinearity;
write FLL+0x13, 0x3E*EnableNonlinearity;
write FLL+0x14, 0x3D*EnableNonlinearity;
write FLL+0x15, 0x3B*EnableNonlinearity;
write FLL+0x16, 0x3A*EnableNonlinearity;
write FLL+0x17, 0x38*EnableNonlinearity;
write FLL+0x18, 0x36*EnableNonlinearity;
write FLL+0x19, 0x33*EnableNonlinearity;
write FLL+0x1A, 0x31*EnableNonlinearity;
write FLL+0x1B, 0x2E*EnableNonlinearity;
write FLL+0x1C, 0x2C*EnableNonlinearity;
write FLL+0x1D, 0x29*EnableNonlinearity;
write FLL+0x1E, 0x26*EnableNonlinearity;
write FLL+0x1F, 0x2E*EnableNonlinearity;
write FLL+0x20, 0x20*EnableNonlinearity;
write FLL+0x21, 0x1C*EnableNonlinearity;
write FLL+0x22, 0x19*EnableNonlinearity;
write FLL+0x23, 0x16*EnableNonlinearity;
write FLL+0x24, 0x13*EnableNonlinearity;
write FLL+0x25, 0x11*EnableNonlinearity;
write FLL+0x26, 0x0E*EnableNonlinearity;
write FLL+0x27, 0x0E*EnableNonlinearity;
write FLL+0x28, 0x0C*EnableNonlinearity;
write FLL+0x29, 0x07*EnableNonlinearity;
write FLL+0x2A, 0x05*EnableNonlinearity;
write FLL+0x2B, 0x04*EnableNonlinearity;
write FLL+0x2C, 0x02*EnableNonlinearity;
write FLL+0x2D, 0x01*EnableNonlinearity;
write FLL+0x2E, 0x01*EnableNonlinearity;
write FLL+0x2F, 0x00*EnableNonlinearity;
write FLL+0x30, 0x00*EnableNonlinearity;
write FLL+0x31, 0x00*EnableNonlinearity;
write FLL+0x32, 0x01*EnableNonlinearity;
write FLL+0x33, 0x01*EnableNonlinearity;
write FLL+0x34, 0x02*EnableNonlinearity;
write FLL+0x35, 0x04*EnableNonlinearity;
write FLL+0x36, 0x05*EnableNonlinearity;
write FLL+0x37, 0x07*EnableNonlinearity;
write FLL+0x38, 0x09*EnableNonlinearity;
write FLL+0x39, 0x0C*EnableNonlinearity;
write FLL+0x3A, 0x0E*EnableNonlinearity;
write FLL+0x3B, 0x11*EnableNonlinearity;
write FLL+0x3C, 0x13*EnableNonlinearity;
write FLL+0x3D, 0x16*EnableNonlinearity;
write FLL+0x3E, 0x16*EnableNonlinearity;
write FLL+0x3F, 0x1C*EnableNonlinearity;
restrict 1
//
//
//
//-------------------------------------------------------------------------------
//
// Filter: Pedestal Correction
//
//-------------------------------------------------------------------------------
//
// Bypass
write FPBY, EnablePedestal;
//
restrict EnablePedestal;
// Time Constant
write FPTC, PedestalTimeConstant;
//
// Additive
write FPNP, FPNPvalue;
//
// Clear
write FPCL, 0;
write FPCL, 1;
restrict 1
//
//
//
//-------------------------------------------------------------------------------
//
// Filter: Gain Correction
//
//-------------------------------------------------------------------------------
//
// Bypass
write FGBY, EnableGainCorrection;
//
restrict EnableGainCorrection;
// Counter Threshold A
write FGTA, 0x014;
//
// Counter Threshold B
write FGTB, 0x80C;
//
// Factors, 256 corresponds to 1
write FGFn+0x00, 0x100;
write FGFn+0x01, 0x100;
write FGFn+0x02, 0x100;
write FGFn+0x03, 0x100;
write FGFn+0x04, 0x100;
write FGFn+0x05, 0x100;
write FGFn+0x06, 0x100;
write FGFn+0x07, 0x100;
write FGFn+0x08, 0x100;
write FGFn+0x09, 0x100;
write FGFn+0x0A, 0x100;
write FGFn+0x0B, 0x100;
write FGFn+0x0C, 0x100;
write FGFn+0x0D, 0x100;
write FGFn+0x0E, 0x100;
write FGFn+0x0F, 0x100;
write FGFn+0x10, 0x100;
write FGFn+0x11, 0x100;
write FGFn+0x12, 0x100;
write FGFn+0x13, 0x100;
write FGFn+0x14, 0x100;
//
// Additives
write FGAn+0x00, GainPedestalIni;
write FGAn+0x01, GainPedestalIni;
write FGAn+0x02, GainPedestalIni;
write FGAn+0x03, GainPedestalIni;
write FGAn+0x04, GainPedestalIni;
write FGAn+0x05, GainPedestalIni;
write FGAn+0x06, GainPedestalIni;
write FGAn+0x07, GainPedestalIni;
write FGAn+0x08, GainPedestalIni;
write FGAn+0x09, GainPedestalIni;
write FGAn+0x0A, GainPedestalIni;
write FGAn+0x0B, GainPedestalIni;
write FGAn+0x0C, GainPedestalIni;
write FGAn+0x0D, GainPedestalIni;
write FGAn+0x0E, GainPedestalIni;
write FGAn+0x0F, GainPedestalIni;
write FGAn+0x10, GainPedestalIni;
write FGAn+0x11, GainPedestalIni;
write FGAn+0x12, GainPedestalIni;
write FGAn+0x13, GainPedestalIni;
write FGAn+0x14, GainPedestalIni;
restrict 1
//
//
//
//-------------------------------------------------------------------------------
//
// Filter: Tail Cancellation
//
//-------------------------------------------------------------------------------
//
// Bypass
write FTBY, EnableTailCancellation;
//
restrict EnableTailCancellation;
// Long Decay Weight
write FTAL, LongDecayWeight;
//
// Long Decay Parameter
write FTLL, LongDecayParameter;
//
// Short Decay Parameter
write FTLS, ShortDecayParameter;
restrict 1;
//
//
//
//-------------------------------------------------------------------------------
//
// Filter: Crosstalk Suppression
//
//-------------------------------------------------------------------------------
//
// Bypass
write FCBY, 1;
//
// Weight 0
write FCWn+0, XtalkM0;
//
// Weight 1
write FCWn+1, XtalkM1;
//
// Weight 2
write FCWn+2, XtalkM2;
//
// Weight 3
write FCWn+3, XtalkM3;
//
// Weight 4
write FCWn+4, XtalkM4;
restrict 1;
//