/**************************************/
/* ALICE TRD                          */
/* 3 Merger Boards                    */
/* SCSN Configuration File            */
/*                                    */
/* 2004-10-20                         */
/* Jan de Cuveland, Venelin Angelov   */
/**************************************/

// ----------------------------
//  define SCSN IDs for ring 0
// ----------------------------
const chip_rm = 01; // root merger
const chip_bm0= 99; // left
const chip_bm1= 99; // right
const m_false_bit  = 8; // 0..9
const m_parit_bit  = 9; // 0..9
const nsig_tr = 0xAAAA;
const nsig_rr = 0x0000;

reset


// left  is connected to port NI_3 of the RM
// right is connected to port NI_0 of the RM

// -------------------------------------------------------
//  enable/disable clock and pretrigger fanout LVDS cells
// -------------------------------------------------------

write           SMMODE, 0xF774; // later pure merger
write chip_rm,  SMMODE, 1001011101110100b; // full-time merger (no CPU)

// -------------------------
//  configure clock control
// -------------------------

write CPU0CLK, 0x00;
write CPU1CLK, 0x00;
write CPU2CLK, 0x00;
write CPU3CLK, 0x00;

//write SMCMD,  0x0112; // go to acq mode to switch filter/preprocessor clocks on
//write FILCLK, 0;      // now filter preprocessor can be switched off,
//write PRECLK, 0;      //   ... but we need some clocks!!!
//write SMCMD,  0x0012; // low power mode

// -----------------------------
//  configure network interface
// -----------------------------

// readout order configuration constants
const niro_bm0    = 0x0003fff8; // 0
const niro_bm1    = 0x0003fff8; // 0

// temp!!!
const niro_rm     = 0x0003fff8; // 0
// merge from the two merger boards
//const niro_rm     = 111111111111011000b; // port 0, port 3, no own data

// NI output excludes and ctrl delay: chip_rm is root in optical link mode
write          NDLY,    0x12492492; // all data bits delay 2
write chip_rm, NDLY,   0x01B6DB6DB; // all data bits delay 3


const NPw = (m_parit_bit << 7) | (m_false_bit << 3) | 4;


// all chips, all input ports, exclude bits
write          NP0,    NPw;
write          NP1,    NPw;
write          NP2,    NPw;
write          NP3,    NPw;

write          NED,    0x1E40; // incl bm0, bm1 now
write chip_rm, NED,    0xDE58; // oase mode, excl 7

// set NI trigger readout order
write chip_bm0, NTRO, niro_bm0;
write chip_bm1, NTRO, niro_bm1;
write chip_rm,  NTRO, niro_rm;

// set NI raw data readout order
write chip_bm0, NRRO, niro_bm0;
write chip_bm1, NRRO, niro_bm1;
write chip_rm,  NRRO, niro_rm;

// set end signature
write  NES, nsig_tr | (nsig_rr << 16);

// timers for NI signals
write NITM0, 0x01D8;          // NI timer 0 (clock)
write NITM1, 0x01E2;          // NI timer 1 (IO data)
write NITM2, 0x022F+24+100;   // NI timer 2 (clock)

write NIP4D, 0xFF;   // delays

// configuration of the NI clock
write NICLK, 11011b;

// configuration of the NI output data port
write NIODE, 11111b;

// configuration of the NI output control port
write NIOCE, 0x01; // can be optimized later

// configuration of the NI input data ports
write NIIDE, 0x07;

// configuration of the NI input control ports
write NIICE, 0x01;

// ---------------------
//  misc. configuration
// ---------------------

// ADC off
write ADCEN, 0;
write ADCMSK, 0;

include SRC/acex.tcs

// --------------------------------
//  configure global state machine
// --------------------------------

write SML0, 0x00004050;         // consider L0 & L0_time = 0x050 (80)
write SML1, 0x00004230+24+100;  // consider L1 & L1_time = 0x200 (512)
write SML2, 0x000042BC+100;     // consider L2 & L2_time = 0x2BC (700)

// --------------------------
//  go to "acquisition" mode
// --------------------------

write SMCMD, 0x00000112;  // go to acqusition mode -> command register