/**************************************/
/* ALICE TRD                          */
/* Read-out board                     */
/* SCSN Configuration File            */
/*                                    */
/* 2004-03-08                         */
/* Jan de Cuveland, Venelin Angelov   */
/**************************************/

const nsig_tr = 0xAAAA;
const nsig_rr = 0x0000;
const irq_clr = 0; // Note irq_clr is 4 in trap2!
const irq_acq = 2;
const irq_raw = 4;

// ------------------------
//  set constant registers
// ------------------------

// hamming correction for all memories!
write dut,      MEMCOR, 0x01FF;
// arbiter timing
write dut,      ARBTIM, 1101b;

// -------------------------
//  set int entry addresses
// -------------------------

include cpu0_labels.tcs
include cpu1_labels.tcs
include cpu2_labels.tcs
include cpu3_labels.tcs

write dut,      IA0+irq_clr, lbl_CLR_cpu0;   // set int_clr start addr for cpu0
write dut,      IA1+irq_clr, lbl_CLR_cpu1;   // set int_clr start addr for cpu1
write dut,      IA2+irq_clr, lbl_CLR_cpu2;   // set int_clr start addr for cpu2
write dut,      IA3+irq_clr, lbl_CLR_cpu3;   // set int_clr start addr for cpu3

write dut,      IA0+irq_acq, lbl_ACQ_cpu0;   // set int_acq start addr for cpu0
write dut,      IA1+irq_acq, lbl_ACQ_cpu1;   // set int_acq start addr for cpu1
write dut,      IA2+irq_acq, lbl_ACQ_cpu2;   // set int_acq start addr for cpu2
write dut,      IA3+irq_acq, lbl_ACQ_cpu3;   // set int_acq start addr for cpu3

write dut,      IA0+irq_raw, lbl_RAW_cpu0;   // set int_raw start addr for cpu0
write dut,      IA1+irq_raw, lbl_RAW_cpu1;   // set int_raw start addr for cpu1
write dut,      IA2+irq_raw, lbl_RAW_cpu2;   // set int_raw start addr for cpu2
write dut,      IA3+irq_raw, lbl_RAW_cpu3;   // set int_raw start addr for cpu3

// ---------------
//  set int masks
// ---------------

const irq_msk = (1 << irq_acq) | (1 << irq_clr) | (1 << irq_raw);

write dut,        IRQHW0, irq_msk;   // set irq_hw mask for cpu0
write dut,        IRQHL0, irq_msk;   // set irq_hl mask cor cpu0
write dut,        IRQHW1, irq_msk;   // set irq_hw mask for cpu1
write dut,        IRQHL1, irq_msk;   // set irq_hl mask cor cpu1
write dut,        IRQHW2, irq_msk;   // set irq_hw mask for cpu2
write dut,        IRQHL2, irq_msk;   // set irq_hl mask cor cpu2
write dut,        IRQHW3, irq_msk;   // set irq_hw mask for cpu3
write dut,        IRQHL3, irq_msk;   // set irq_hl mask cor cpu3


// -------------------------
//  configure clock control
// -------------------------
write dut,      CPU0CLK, 0x3F;
write dut,      CPU1CLK, 0x3F;
write dut,      CPU2CLK, 0x3F;
write dut,      CPU3CLK, 0x3F;

// -----------------------------
//  configure network interface
// -----------------------------

// output delays optimized for the FPGA

write dut, NED,(root_flag << 14) | (oase_mode << 15) | (f_parit_bit << 10) | (f_false_bit << 6) | (f_ctrl_delay << 3) | f_strb_delay;
write dut, NDLY, (f_data_delay0) | (f_data_delay1 << 3) | (f_data_delay2 << 6) | (f_data_delay3 << 9) | (f_data_delay4 << 12) | (f_data_delay5 << 15) | (f_data_delay6 << 18) | (f_data_delay7 << 21) | (f_data_delay8 << 24) | (f_data_delay9 << 27);

// readout order configuration constants
const niro_dut    = 0x0003fffc; // own data only

// set NI tracklet readout order
write dut,      NTRO, niro_dut;

// set NI raw data readout order
write dut,      NRRO, niro_dut;

// set end signature (rr: 0x----0000, tr: 0x----1000)
write dut,      NES, nsig_tr | (nsig_rr << 16);

// timers for NI signals
write dut,      NITM0, 0x01D0; // 0x153;   // NI timer 0 (clock)
write dut,      NITM1, 0x01E2; // 0x165;   // NI timer 1 (IO data)
write dut,      NITM2, 0x022F+24+100;   // NI timer 2 (clock)

write dut,      NIP4D, 0xFF;   // delays

// configuration of the NI clock
write dut,      NICLK,  0x3F;

// configuration of the NI output data port
write dut,      NIODE,  00010b;

// configuration of the NI output control port
write dut,      NIOCE,  0x01; // was 3 // was 7

// configuration of the NI input data ports
write dut,      NIIDE,  0x3F;

// configuration of the NI input control ports
write dut,      NIICE,  0x3F;

// ---------------------
//  misc. configuration
// ---------------------

// ADC off
// mask the ADCs with open inputs, first mask all
write dut,    ADCMSK, 0x0

// Drift time
write dut,    TPPT0,  0x0D; // skip first 10 samples
write dut,    TPPAE,  0x15; // acquire 21 samples
write dut,    TPPGR,  0x14; // start CPUs after 20 samples

// --------------------------------
//  configure global state machine
// --------------------------------

write dut,    SML0, L0time;  // consider L0 & L0_time = 0x050 (80)
write dut,    SML1, L1time;  // consider L1 & L1_time = 0x200 (512)
write dut,    SML2, L2time;  // consider L2 & L2_time = 0x2BC (700)

// --------------------------------
// Assembler program parameters
// --------------------------------

// c15
write dut,    0x0C07, nsig_rr

// c12
write dut,    0x0C04, nwords;

// c13, what to send in tracklet mode
write dut,  0x0C05, 0xFB04C040;

// c14, the mode word of the psr_counter
write dut,  0xC06, 010000101111b | (cnt_mode << 9);

// init the PSRG counters
// c8
write dut, 0x0C00, 0xABCDF000 & simple_test_n;//
write dut, 0x0C08, 0x12348200 & simple_test_n;//
write dut, 0x0C10, 0x56788300 & simple_test_n;//
write dut, 0x0C18, 0x9ABC8400 & simple_test_n;//