// switch and reset test of DUT
//
//  0       only the local scsn slave
//  1       the local and the other fpga slave
//  2       the local, the other fpga slave and the 4 traps for ni test
//  3       the local and the DUT
//  4       the local, the DUT and the 4 traps for ni test
//  5       the local and the WT
//  6       the local and the 4 traps for ni test
//  7       the local, the other fpga and the WT
//             In cases without DUT in the chain, bit3 of the switch determines
//             the static value to SCSN0 input of DUT (useful for JTAG tests)

include chip_def.tcs

// reset
write 0x4400, 0; // fpga2 only
reset;  // FPGA only
wait 20;
write 0x4400, 7; // fpga2-fpga1-WDUT
// here the reset output config of the fpga1
write fpga1, 0x6000, (f_false_bit << 0) | (f_parit_bit << 4) | (rst_inv << 8) | (rst_opend << 9);
// exclude and parity bits in FPGA design, reset conf and reset read back
// check if the pull up of the reset is seen
expect fpga1, 0x6000, (f_false_bit << 0) | (f_parit_bit << 4) | (rst_inv << 8) | (rst_opend << 9) | (1 << 10);
// not practical for simulation!
// reset test DUT
write  fpga1, 0x6003, 0; // here the timeout in scsn is an additional indication for the reset in TRAP!
expect dut,   0x0A00, 0x4050
write  dut,   0x0A00, 0x0BCD
expect dut,   0x0A00, 0x0BCD
write  fpga1, 0x6003, 0; // here the timeout in scsn is an additional indication for the reset in TRAP!
expect dut,   0xA00,  0x4050
// reset dut
wait 20;
nop;