include ../scsn_ids.tcs

const xor_mask  = 0x3FF;
const and_mask  = 0x3FF;
const f1_bit = 10; // >9 for no
const f2_bit = 10;
const or_mask  = ( (1 << f1_bit) | (1 << f2_bit) ) & 0x3FF;

const oase_mode  = 0; // 1 or 0

const root_flag  = 0; // 1 or 0

const f_false_bit  = 8; // 0..9
const f_parit_bit  = 9; // 0..9

// all delays:    min .best. max
const f_ctrl_delay = 3;  // 2 .3. 4 stable

const f_data_delay0 = 4; //
const f_data_delay1 = 4; //
const f_data_delay2 = 4; //
const f_data_delay3 = 4; //
const f_data_delay4 = 4; //   3..6
const f_data_delay5 = 4; //
const f_data_delay6 = 4; //
const f_data_delay7 = 4; //
const f_data_delay8 = 4; //
const f_data_delay9 = 4; //

const f_strb_delay = 2; // data-4 ... data delay

// RESET SECTION =============================
write 0x4400, 0; // fpga2 only
reset;  // FPGA only
wait 20;
write 0x4400, 7; // fpga2-fpga1-WDUT
// reset test DUT
write  fpga1, 0x6003, 0; // here the timeout in scsn is an additional indication for the reset in TRAP!
reset dut
// reset dut
wait 20;
// simulated bit errors
write fpga1, 0x6001, (xor_mask << 20) | (and_mask << 10) | or_mask;
nop;
// ============================================

write dut, NMOD, 0x1C
expect dut, NMOD, 0x1C
write NICLK, 1
write NIOCE, 1
write NIODE, 1
write dut, NDLY, (f_data_delay0) | (f_data_delay1 << 3) | (f_data_delay2 << 6) | (f_data_delay3 << 9) | (f_data_delay4 << 12) | (f_data_delay5 << 15) | (f_data_delay6 << 18) | (f_data_delay7 << 21) | (f_data_delay8 << 24) | (f_data_delay9 << 27);


write fpga1, 0x6000, (f_false_bit << 0) | (f_parit_bit << 4)
write dut, NED,(root_flag << 14) | (oase_mode << 15) | (f_parit_bit << 10) | (f_false_bit << 6) | (f_ctrl_delay << 3) | f_strb_delay;

//==============================
testpatt = 0x55555555

write dut, NTP, testpatt

// clear the ni-input in FPGA
write   fpga1, 0x6002, 0
// number of 16-bit words
expect  fpga1, 0x6002, 0x800800
// parity counters
expect fpga1, 0x6003, 0
expect fpga1, 0x6800, testpatt
expect fpga1, 0x6801, testpatt

//==============================
testpatt = 0xAAAAAAAA

write dut, NTP, testpatt

// clear the ni-input in FPGA
write   fpga1, 0x6002, 0
// number of 16-bit words
expect  fpga1, 0x6002, 0x800800
// parity counters
expect fpga1, 0x6003, 0
expect fpga1, 0x6800, testpatt
expect fpga1, 0x6801, testpatt

//==============================
testpatt = 0x00FFAA55

write dut, NTP, testpatt

// clear the ni-input in FPGA
write   fpga1, 0x6002, 0
// number of 16-bit words
expect  fpga1, 0x6002, 0x800800
// parity counters
expect fpga1, 0x6003, 0
expect fpga1, 0x6800, testpatt
expect fpga1, 0x6801, testpatt

reset dut