const nchips = 1;

const nwords = 63;

const cnt_mode = 1;
//const simple_test_n  = 0xFFFF; // or 0
//const simple_test_n  = 0xFFFF0000; // or 0
//const simple_test_n  = 0x0000FFFF; // or 0
const simple_test_n  = 0xFFFF;

const oase_mode  = 0; // 1 or 0

const root_flag  = 0; // 1 or 0

const xor_mask  = 0x3FF;
const and_mask  = 0x3FF;
const  or_mask  = 0x000;

const rst_inv = 0; // must be 0 if no additional reset inverter is soldered
const rst_opend = 1; // if open drain the pull up in the TRAP can be measured.

const L0time= 0x00000050;
const L1time= 0x000042BC+100;   // the start of readout, no confirm, used only internally
const L2time= 0x00000230+24+100; // this is for ALICE the L1A

// all delays can be from 0 to 7

// configuration for DUT -> FPGA readout
// all delays:    min .best. max
const f_ctrl_delay = 3;  // 2 .3. 4 stable

const f_data_delay0 = 3; //
const f_data_delay1 = 3; //
const f_data_delay2 = 3; //
const f_data_delay3 = 3; //
const f_data_delay4 = 3; //   3..6
const f_data_delay5 = 3; //
const f_data_delay6 = 3; //
const f_data_delay7 = 3; //
const f_data_delay8 = 3; //
const f_data_delay9 = 3; //

const f_strb_delay = 3; //
const f_false_bit  = 8; // 0..9
const f_parit_bit  = 9; // 0..9