/**************************************/
/* ALICE TRD                          */
/* Tester   board                     */
/* SCSN Configuration File            */
/*                                    */
/* 2004-12-02                         */
/* Venelin Angelov                    */
/**************************************/

const nsig_tr = 0xAAAA;
const nsig_rr = 0x0000;
const irq_clr = 0; // Note irq_clr is 4 in trap2!
const irq_acq = 2;
const irq_raw = 4;

// --------------------------------
// arbiter, hamming
// --------------------------------
// hamming correction for all memories!
write dut,      MEMCOR, 0x01FF;
// arbiter timing
write dut,      ARBTIM, 1101b;

const ReadoutFlag = 11b;

//***************************
//* ADCs                    *
//***************************
// ADC parameters, IRQ, sampling phase, en inp buffer, autozero, power

const power_backgr = 7; // 0..7
const power_pretr  = 7; // 0..7
const irq_phase    = 6; // 0..11
const smp_phase    = 5; // 0..11
const enibf_backgr = 0; // 0 or 1
const enibf_pretr  = 0; // 0 or 1
const az_backgr    = 1; // 0 or 1
const az_pretr     = 1; // 0 or 1

write ADCPAR, power_backgr | (az_backgr << 3) | (enibf_backgr << 4) | (power_pretr << 5) | (az_pretr << 8) | (enibf_pretr << 9) | (smp_phase << 10) | (irq_phase << 14)

// invert bits
write ADCINB, 10b;

// ADC DAC 5-bit
write ADCDAC, 10000b;
// end ADC
// -------------------------

// -------------------------
// CPU configuration
// -------------------------

// include the label information from the compilation, here are defined the addresses
// of the IRQ clear and IRQ acq

include cpu0_labels.tcs
include cpu1_labels.tcs
include cpu2_labels.tcs
include cpu3_labels.tcs

// -------------------------
//  set int entry addresses
// -------------------------

write IA0+irq_clr, lbl_CLR_cpu0;   // set int_clr start addr for cpu0
write IA1+irq_clr, lbl_CLR_cpu1;   // set int_clr start addr for cpu1
write IA2+irq_clr, lbl_CLR_cpu2;   // set int_clr start addr for cpu2
write IA3+irq_clr, lbl_CLR_cpu3;   // set int_clr start addr for cpu3

write IA0+irq_acq, lbl_ACQ_cpu0;   // set int_acq start addr for cpu0
write IA1+irq_acq, lbl_ACQ_cpu1;   // set int_acq start addr for cpu1
write IA2+irq_acq, lbl_ACQ_cpu2;   // set int_acq start addr for cpu2
write IA3+irq_acq, lbl_ACQ_cpu3;   // set int_acq start addr for cpu3

write IA0+irq_raw, lbl_RAW_cpu0;   // set int_raw start addr for cpu0
write IA1+irq_raw, lbl_RAW_cpu1;   // set int_raw start addr for cpu1
write IA2+irq_raw, lbl_RAW_cpu2;   // set int_raw start addr for cpu2
write IA3+irq_raw, lbl_RAW_cpu3;   // set int_raw start addr for cpu3

// ---------------
//  set int masks
// ---------------

const irq_msk = (1 << irq_acq) | (1 << irq_clr) | (1 << irq_raw);

write dut,      IRQHW0, irq_msk;   // set irq_hw mask for cpu0
write dut,      IRQHL0, irq_msk;   // set irq_hl mask cor cpu0
write dut,      IRQHW1, irq_msk;   // set irq_hw mask for cpu1
write dut,      IRQHL1, irq_msk;   // set irq_hl mask cor cpu1
write dut,      IRQHW2, irq_msk;   // set irq_hw mask for cpu2
write dut,      IRQHL2, irq_msk;   // set irq_hl mask cor cpu2
write dut,      IRQHW3, irq_msk;   // set irq_hw mask for cpu3
write dut,      IRQHL3, irq_msk;   // set irq_hl mask cor cpu3

// -------------------------
//  configure clock control
// -------------------------
write dut,      CPU0CLK, 0x3F;
write dut,      CPU1CLK, 0x3F;
write dut,      CPU2CLK, 0x3F;
write dut,      CPU3CLK, 0x3F;


// --------------------------------
// PREPROCESSOR
// --------------------------------

// set to 0x00 for ADC readout or to 0x1E for test data readout
// Drift time
write TPPT0,  0x01; // skip first nn samples
write TPPAE,  0x3F; // acquire 63 samples
write TPPGR,  0x3F; // start CPUs after 63 samples



// --------------------------------
// NI configuration
// --------------------------------

// output delays optimized for the FPGA

write dut,      NED, (root_flag << 14) | (oase_mode << 15) | (f_parit_bit << 10) | (f_false_bit << 6) | (f_ctrl_delay << 3) | f_strb_delay;
write dut,      NDLY, (f_data_delay0) | (f_data_delay1 << 3) | (f_data_delay2 << 6) | (f_data_delay3 << 9) | (f_data_delay4 << 12) | (f_data_delay5 << 15) | (f_data_delay6 << 18) | (f_data_delay7 << 21) | (f_data_delay8 << 24) | (f_data_delay9 << 27);
const niro_dut    = 0x0003fffc; // own data only
// set NI tracklet readout order
write dut,      NTRO, niro_dut;
// set NI raw data readout order
write dut,      NRRO, niro_dut;
// timers for NI signals
write dut,      NITM0, 0x01D0+30*12; // 0x153;   // NI timer 0 (clock)
write dut,      NITM1, 0x01E2+30*12; // 0x165;   // NI timer 1 (IO data)
write dut,      NITM2, 0x022F+24+100+30*12;   // NI timer 2 (clock)

write dut,      NIP4D, 0xFF;   // delays

// configuration of the NI clock
write dut,      NICLK,  0x3F;

// configuration of the NI output data port
write dut,      NIODE, 00010b;

// configuration of the NI output control port
write dut,      NIOCE,  0x01;
// set end signature (rr: 0x----0000, tr: 0x----1000)
write dut,      NES, nsig_tr | (nsig_rr << 16);

// --------------------------------
//  configure global state machine
// --------------------------------

write dut,    SML0, L0time;  // consider L0 & L0_time = 0x050 (80)
write dut,    SML1, L1time;  // consider L1 & L1_time = 0x200 (512)
write dut,    SML2, L2time;  // consider L2 & L2_time = 0x2BC (700)

// --------------------------------
// Assembler program parameters
// --------------------------------

write 0x0C05, ReadoutFlag;
// Number of Samples, c11
write 0x0C03, nsamples
write 0x0C0B, nsamples
write 0x0C13, nsamples
write 0x0C1B, nsamples
// Event counter, c12
write 0x0C04, 0

write 0x0C00, 0x0000+24;
write 0x0C08, 0x0000+(nsamples / 3)*5*4+24;
write 0x0C10, 0x0000+(nsamples / 3)*10*4+24;
write 0x0C18, 0x0000+(nsamples / 3)*15*4+24;

// Tracklet & Raw Data End Marker

write 0x0C06, nsig_tr
// c15
write 0x0C07, nsig_rr