Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.3, Apr 2004 Please send any comments to: angelov@kip.uni-heidelberg.de 22:25:09 / 06 Jul 2005 Source code file: fitred.asm Memory initialisation file: Log file: cpu2.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU2 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 1: ;################################################# 2: ;# 3: ;# Rudimentary Readout Program for TRAP3 chip 4: ;# 5: ;# Marcus Gutfleisch, V.Angelov 6: ;# Universitaet Heidelberg, Kirchhoff-Institut fue 7: ;# 8: ;# Heidelberg, 15.10.2004 9: ;# Heidelberg, 08.12.2004 10: ;# 11: ;# Stores in DMEM and in NI 12: ;# 13: ;# 0: tracklet cpu0 14: ;# 1: tracklet cpu1 15: ;# 2: tracklet cpu2 16: ;# 3: tracklet cpu3 17: ;# 4: endmark tracklet 18: ;# 5: endmark tracklet 19: ;# 6: adc[ch=0,timebin=2] & adc[ch=0,timebin=1] 20: ;# 7: adc[ch=0,timebin=5] & adc[ch=0,timebin=4] 21: ;# ... 22: ;# n: adc[ch=1,timebin=2] & adc[ch=1,timebin=1] 23: ;# ... 24: ;# 25: ;# Stores only in DMEM 26: ;# 27: ;# 0x200..0x207: fit register 0..7 of ch=0 28: ;# 0x208..0x20F: fit register 0..7 of ch=1 29: ;# ... 30: ;# 0x2A0..0x2A7: fit register 0..7 of ch=20 31: ;# 32: ;# 0x300..0x303: the automatically selected channe 33: ;# f0 & f8 (as 8-bit numbers) for cp 34: ;# f0 & f8 (as 8-bit numbers) for cp 35: ;# f0 & f8 (as 8-bit numbers) for cp 36: ;# f0 & f8 (as 8-bit numbers) for cp 37: ;# 38: ;# Note: the addresses are word addresses (with th 39: ;# used to read the data using the scsn. 40: ;# 41: ;################################################# 42: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 31: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 32: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 33: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 34: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 35: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 36: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 37: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 38: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 39: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 40: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 41: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 42: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 43: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 44: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 45: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 46: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 47: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 48: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 49: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 50: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 51: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 52: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 53: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 54: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 55: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 56: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 57: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 58: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 59: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 60: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 61: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 62: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 63: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 64: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 65: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 66: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 67: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 68: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 69: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 70: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 71: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 72: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 73: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 74: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 75: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 76: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 77: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 78: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 79: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 80: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 81: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 82: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 83: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 84: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 85: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 86: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 87: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 88: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 89: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 90: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 91: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 92: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 93: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 94: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 95: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 96: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 97: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 98: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 99: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 100: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 101: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 102: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 103: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 104: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 105: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 106: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 107: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 108: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 109: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 110: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 111: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 112: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 113: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 114: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 115: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 116: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 117: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 118: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 119: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 120: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 121: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 122: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 123: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 124: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 125: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 126: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 127: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 128: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 129: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 130: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 131: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 132: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 133: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 134: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 135: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 136: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 137: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 138: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 139: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 140: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 141: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 142: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 143: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 144: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 145: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 146: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 147: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 148: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 149: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 150: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 151: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 152: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 153: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 154: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 155: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 156: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 157: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 158: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 159: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 160: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 161: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 162: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 163: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 164: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 165: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 166: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 167: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 168: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 169: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 170: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 171: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 172: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 173: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 174: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 175: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 176: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 177: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 178: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 179: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 180: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 181: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 182: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 183: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 184: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 185: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 186: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 187: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 188: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 189: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 190: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 191: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 192: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 193: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 194: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 195: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 196: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 197: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 198: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 199: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 200: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 201: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 202: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 203: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 204: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 205: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 206: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 207: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 208: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 209: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 210: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- *** End of include file /cad/tools/bin/conf_va.inc 44: 45: ;################################################# 46: ;# 47: ;# defines 48: ;# 49: ;################################################# 50: 51: #def endsig_tr = c14 ; end sign 52: #def endsig_rr = c15 ; end sign 53: #def nsamples = c11 ; number o 54: #def EventCounter = c12 ; event co 55: #def ReadoutFlag = c13 ; bit1: NI 56: ; bit0: SC 57: #def scsn_start = c8 ; start ad 58: #def EvtCtrGIOAdr = 0xC0C ; Address 59: 60: #def rstack = r8 ; program 61: #def rio = r14 ; local I/ 62: 63: #ifdef cpu0 64: #def clk_onoff = CPU0SS ; own cloc 65: #def clk_onoff_next = CPU1SS ; for dela 66: #def LSBdata = 0x03 ; LSBs for 67: #def TPCIn = TPCI0 ; Tracklet 68: #def TPPCH_s = 0 ; Tracklet 69: #def TPPCH_e = 3 ; Tracklet 70: #endif 71: 72: #ifdef cpu1 73: #def clk_onoff = CPU1SS ; own cloc 74: #def clk_onoff_next = CPU2SS ; for dela 75: #def LSBdata = 0x02 ; LSBs for 76: #def TPCIn = TPCI1 ; Tracklet 77: #def TPPCH_s = 4 ; Tracklet 78: #def TPPCH_e = 8 ; Tracklet 79: #endif 80: 81: #ifdef cpu2 82: #def clk_onoff = CPU2SS ; own cloc 83: #def clk_onoff_next = CPU3SS ; for dela 84: #def LSBdata = 0x03 ; LSBs for 85: #def TPCIn = TPCI2 ; Tracklet 86: #def TPPCH_s = 9 ; Tracklet 87: #def TPPCH_e = 13 ; Tracklet 88: #endif 89: 90: #ifdef cpu3 91: #def clk_onoff = CPU3SS ; own cloc 92: #def LSBdata = 0x02 ; LSBs for 93: #def TPCIn = TPCI3 ; Tracklet 94: #def TPPCH_s = 14 ; Tracklet 95: #def TPPCH_e = 20 ; Tracklet 96: #endif 97: 98: 99: ;################################################# 100: ;# 101: ;# 0x000: Infinite Loop at Instruction Memory Rese 102: ;# 103: ;################################################# 104: 105: ORG 0x0; 106: 107: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 108: nop 0001 : 0000_0000_0000_0000_0000_0000 109: 110: 111: ;################################################# 112: ;# 113: ;# 0x100: Interrupt Clear Jump Address 114: ;# 115: ;################################################# 116: 117: ORG 0x100; 118: 119: clr: nop 0100 : 0000_0000_0000_0000_0000_0000 120: 121: #ifdef cpu0 122: iext b1111_0101_0000_0000_0010_0000; 123: mov b1111_0101_0000_0000_0010_0000, r1 124: jmpr cc_busy, 0 125: sgio r1, SMOFFON ; switch off all NI LVDS 126: #endif 127: 128: #ifdef cpu1 129: mov cmd_ext_clr, r0 130: jmpr cc_busy, 0 131: sgio r0, SMCMD ; clear ready (VA) 132: nop 133: #endif 134: 135: #ifdef cpu2 136: iext TPCBY 0101 : 0101_0000_0000_0000_0000_0011 137: mov TPCBY, r0 0102 : 1100_0110_0000_1000_1100_0000 138: mov 1, r1 0103 : 1100_0110_0000_0000_0010_0001 139: sgio r1, r0 0104 : 0010_0100_0001_0000_0000_0000 140: #endif 141: 142: jmpr cc_uncond, 0 0105 : 0000_0100_0010_0000_1010_1111 143: nop 0106 : 0000_0000_0000_0000_0000_0000 144: 145: 146: ;################################################# 147: ;# 148: ;# 0x200: Interrupt Tracklet Processing Jump Addre 149: ;# 150: ;################################################# 151: 152: ORG 0x200; 153: 154: acq: nop 0200 : 0000_0000_0000_0000_0000_0000 155: 156: #ifdef cpu0 157: mov b0000_0010_0000, r1 158: jmpr cc_busy, 0 159: sgio r1, SMOFF ; switch off clk_fil 160: #endif 161: ; store the automatically selected channel in GR 162: #ifdef cpu0 163: mov f0, g0 164: shl 8, g0, g0 165: or f8, g0, g0 166: #endif 167: #ifdef cpu1 168: mov f0, g1 169: shl 8, g1, g1 170: or f8, g1, g1 171: #endif 172: #ifdef cpu2 173: mov f0, g2 0201 : 1100_0010_0000_0100_0001_0010 174: shl 8, g2, g2 0202 : 1011_0010_1000_0010_0101_0010 175: or f8, g2, g2 0203 : 1010_1011_1000_0010_0101_0010 176: #endif 177: #ifdef cpu3 178: mov f0, g3 179: shl 8, g3, g3 180: or f8, g3, g3 181: #endif 182: 183: mov 30, r0 0204 : 1100_0110_0000_0011_1100_0000 184: delay: ; wait a while to 185: sub r0, c1, r0 ; NI are ready for 0205 : 1000_1010_0000_0110_0010_0000 186: jmp cc_nzero, delay ; transition. 0206 : 0000_0100_0000_0000_0000_0001 187: 188: ; mov endsig_tr r0 ; load Tracklet E 189: mov scsn_start r0 ; load start addr 0207 : 1100_0010_0000_0111_0000_0000 190: ; store in DMEM the same 191: #ifdef cpu0 192: sra r0, 0 193: #endif 194: #ifdef cpu1 195: sra r0, 4 196: #endif 197: #ifdef cpu2 198: sra r0, 8 0208 : 0100_0000_0000_0000_0000_1000 199: mov 0, r1 0209 : 1100_0110_0000_0000_0000_0001 200: iext TPCBY 020A : 0101_0000_0000_0000_0000_0011 201: sgio r1,TPCBY ; switch to bypass 020B : 0010_1000_0001_0000_0100_0110 202: #endif 203: #ifdef cpu3 204: sra r0, 12 205: mov endsig_tr r2 ; load Tracklet En 206: swp r2, r2 207: mov endsig_tr r1 ; load Tracklet En 208: or r2, r1, r2 209: sra r2 16 210: nop 211: sra r2 20 212: #endif 213: 214: spio r0 NODP ; Send Tracklet da 020C : 0010_0000_0000_0000_0000_0000 215: 216: jmpr cc_uncond 0 020D : 0000_0100_0100_0001_1010_1111 217: nop 020E : 0000_0000_0000_0000_0000_0000 218: 219: 220: ;################################################# 221: ;# 222: ;# 0x400: Interrupt Raw Data Transmission Jump Add 223: ;# 224: ;################################################# 225: 226: ORG 0x400 227: 228: raw: nop 0400 : 0000_0000_0000_0000_0000_0000 229: 230: #ifdef cpu0 231: mov cmd_CPU_done r0 ; CPU0 indicates u 232: sgio r0 SMCMD; 233: jmp cc_uncond, continue ; CPU0 fills FIFO 234: #endif 235: 236: mov 0, r0 ; switch off own c 0401 : 1100_0110_0000_0000_0000_0000 237: sgio r0, clk_onoff; ; CPU2 and CPU3 ar 0402 : 0010_1000_0000_1010_0010_0101 238: jmpr cc_busy, 0 ; They will be sta 0403 : 0000_0100_1000_0000_0111_0111 239: 240: nop 0404 : 0000_0000_0000_0000_0000_0000 241: nop 0405 : 0000_0000_0000_0000_0000_0000 242: nop 0406 : 0000_0000_0000_0000_0000_0000 243: nop 0407 : 0000_0000_0000_0000_0000_0000 244: nop 0408 : 0000_0000_0000_0000_0000_0000 245: 246: continue: 247: 248: ;############################################## 249: ;# Store Start addresses for SCSN transfer via D 250: ;############################################## 251: 252: mov scsn_start, r15 0409 : 1100_0010_0000_0111_0000_1111 253: 254: ;############################################## 255: ;# NI transfer event header (CPU0 only) 256: ;############################################## 257: 258: mov LSBdata, r7 ; pass the two LSB 040A : 1100_0110_0000_0000_0110_0111 259: 260: iext 0xFFFF ; high word mask f 040B : 0101_0000_0000_0000_0000_1111 261: mov 0xFFFF, r11 040C : 1100_0111_1111_1111_1110_1011 262: swp r11, r11 040D : 0111_1010_0000_0001_0110_1011 263: 264: run_tmsn: 265: 266: ;############################################## 267: ;# NI&SCSN transfer 1st channel 268: ;############################################## 269: 270: mov EBR0, rio ; address in LIO o 040E : 1100_0111_0000_0000_0000_1110 271: mov nsamples,r1 ; number of sample 040F : 1100_0010_0000_0111_0110_0001 272: mvpcr +2, rstack 0410 : 1100_0110_1000_0010_0100_1000 273: jmp cc_uncond, ChTML; 0411 : 0000_0100_0000_0000_0000_1111 274: 275: ;############################################## 276: ;# NI&SCSN transfer 2nd channel 277: ;############################################## 278: 279: mov EBR1, rio ; address in LIO o 0412 : 1100_0111_0000_1000_0000_1110 280: mov nsamples,r1 ; number of sample 0413 : 1100_0010_0000_0111_0110_0001 281: mvpcr +2, rstack 0414 : 1100_0110_1000_0010_1100_1000 282: jmp cc_uncond, ChTML; 0415 : 0000_0100_0000_0000_0000_1111 283: 284: ;############################################## 285: ;# NI&SCSN transfer 3rd channel 286: ;############################################## 287: 288: mov EBR2, rio ; address in LIO o 0416 : 1100_0111_0001_0000_0000_1110 289: mov nsamples,r1 ; number of sample 0417 : 1100_0010_0000_0111_0110_0001 290: mvpcr +2, rstack 0418 : 1100_0110_1000_0011_0100_1000 291: jmp cc_uncond, ChTML; 0419 : 0000_0100_0000_0000_0000_1111 292: 293: ;############################################## 294: ;# NI&SCSN transfer 4th channel 295: ;############################################## 296: 297: mov EBR3, rio ; address in LIO o 041A : 1100_0111_0001_1000_0000_1110 298: mov nsamples,r1 ; number of sample 041B : 1100_0010_0000_0111_0110_0001 299: mvpcr +2, rstack 041C : 1100_0110_1000_0011_1100_1000 300: jmp cc_uncond, ChTML; 041D : 0000_0100_0000_0000_0000_1111 301: 302: ;############################################## 303: ;# NI&SCSN transfer 5th channel 304: ;############################################## 305: 306: mov EBR4, rio ; address in LIO o 041E : 1100_0111_0010_0000_0000_1110 307: mov nsamples,r1 ; number of sample 041F : 1100_0010_0000_0111_0110_0001 308: mvpcr +2, rstack 0420 : 1100_0110_1000_0100_0100_1000 309: jmp cc_uncond, ChTML; 0421 : 0000_0100_0000_0000_0000_1111 310: 311: ;############################################## 312: ;# NI&SCSN transfer 6th channel (CPU3 only) 313: ;############################################## 314: 315: #ifdef cpu3 316: mov EBR5, rio ; address in LIO o 317: mov nsamples,r1 ; number of sample 318: mvpcr +2, rstack 319: jmp cc_uncond, ChTML; 320: mov endsig_rr r0 321: sra+ r0 322: nop 323: sra+ r0 324: #endif; 325: 326: complete_ni_tmsn: 327: ; read the fit register and store in DMEM 328: mov TPPCH_s, r0 ; Set Preprocesso 0422 : 1100_0110_0000_0001_0010_0000 329: iext TPCIn 0423 : 0101_0000_0000_0000_0000_0011 330: sgio r0, TPCIn 0424 : 0010_1000_0000_0000_0100_1010 331: shl 5, r0, r15 ; start addres = 0425 : 1011_0010_0101_0000_0000_1111 332: mov 0x800, r1 0426 : 1100_0111_0000_0000_0000_0001 333: add r1, r15, r15 0427 : 1000_0010_0001_0001_1110_1111 334: 335: read_frf: 336: jmpr cc_busy, 0 0428 : 0000_0100_1000_0101_0001_0111 337: nop 0429 : 0000_0000_0000_0000_0000_0000 338: nop 042A : 0000_0000_0000_0000_0000_0000 339: nop 042B : 0000_0000_0000_0000_0000_0000 340: mov f8, r1 042C : 1100_0010_0000_0101_0000_0001 341: sra+ r1 042D : 0011_1000_0001_0000_0000_0000 342: mov f9, r1 042E : 1100_0010_0000_0101_0010_0001 343: sra+ r1 042F : 0011_1000_0001_0000_0000_0000 344: mov f10,r1 0430 : 1100_0010_0000_0101_0100_0001 345: sra+ r1 0431 : 0011_1000_0001_0000_0000_0000 346: mov f11,r1 0432 : 1100_0010_0000_0101_0110_0001 347: sra+ r1 0433 : 0011_1000_0001_0000_0000_0000 348: mov f12,r1 0434 : 1100_0010_0000_0101_1000_0001 349: sra+ r1 0435 : 0011_1000_0001_0000_0000_0000 350: mov f13,r1 0436 : 1100_0010_0000_0101_1010_0001 351: sra+ r1 0437 : 0011_1000_0001_0000_0000_0000 352: mov f14,r1 0438 : 1100_0010_0000_0101_1100_0001 353: sra+ r1 0439 : 0011_1000_0001_0000_0000_0000 354: mov f15,r1 043A : 1100_0010_0000_0101_1110_0001 355: sra+ r1 043B : 0011_1000_0001_0000_0000_0000 356: add r0, c1, r0 043C : 1000_0010_0000_0110_0010_0000 357: iext TPCIn 043D : 0101_0000_0000_0000_0000_0011 358: sgio r0, TPCIn 043E : 0010_1000_0000_0000_0100_1010 359: cmp r0, TPPCH_e 043F : 1100_1000_0000_0000_0000_1101 360: jmp cc_leu, read_frf 0440 : 0000_0100_0000_0000_0001_1000 361: mov 0xC00, r15 0441 : 1100_0111_1000_0000_0000_1111 362: shl 2, c5, r1 0442 : 1011_0010_0010_0110_1010_0001 363: add r1, r15, r15 0443 : 1000_0010_0001_0001_1110_1111 364: #ifdef cpu0 365: mov g0, r0 366: #endif 367: #ifdef cpu1 368: mov g1, r0 369: #endif 370: #ifdef cpu2 371: mov g2, r0 0444 : 1100_0010_0000_0010_0100_0000 372: #endif 373: #ifdef cpu3 374: mov g3, r0 375: #endif 376: sra+ r0 0445 : 0011_1000_0000_0000_0000_0000 377: 378: 379: ;############################################## 380: ;# CPU0, CPU1: start CPU2 and CPU3 for delayed t 381: ;############################################## 382: 383: mov 1, r1 0446 : 1100_0110_0000_0000_0010_0001 384: jmpr cc_busy, 0 0447 : 0000_0100_1000_1000_1111_0111 385: #ifdef cpu3 386: nop 387: #else 388: sgio r1 clk_onoff_next 0448 : 0010_1000_0001_1010_0010_0111 389: #endif 390: 391: ;############################################## 392: ;# CPU3: Increment Event Counter 393: ;############################################## 394: 395: #ifdef cpu3 396: 397: mov EventCounter, r0 398: add r0, c1, r0 399: iext 0x1FFFFF 400: mov 0x1FFFFF, r1 401: and r1, r0, r0 402: jmp cc_nzero, EvtCtrOK 403: mov 10, r0 404: EvtCtrOK: 405: jmpr cc_busy, 0 406: sgio r0 EvtCtrGIOAdr 407: 408: #endif 409: 410: ;############################################## 411: ;# NI&SCSN transfer end marker 412: ;############################################## 413: 414: mov endsig_rr r0 0449 : 1100_0010_0000_0111_1110_0000 415: spio r0 NODP 044A : 0010_0000_0000_0000_0000_0000 416: 417: ;############################################## 418: ;# switch off own clock after transfer 419: ;############################################## 420: 421: coff: 422: mov 0, r0 044B : 1100_0110_0000_0000_0000_0000 423: 424: jmpr cc_busy, 0 044C : 0000_0100_1000_1001_1001_0111 425: sgio r0 clk_onoff 044D : 0010_1000_0000_1010_0010_0101 426: jmpr cc_busy, 0 044E : 0000_0100_1000_1001_1101_0111 427: 428: nop 044F : 0000_0000_0000_0000_0000_0000 429: nop 0450 : 0000_0000_0000_0000_0000_0000 430: nop 0451 : 0000_0000_0000_0000_0000_0000 431: nop 0452 : 0000_0000_0000_0000_0000_0000 432: nop 0453 : 0000_0000_0000_0000_0000_0000 433: nop 0454 : 0000_0000_0000_0000_0000_0000 434: nop 0455 : 0000_0000_0000_0000_0000_0000 435: 436: jmp cc_uncond, coff 0456 : 0000_0100_0000_0000_0000_1111 437: nop 0457 : 0000_0000_0000_0000_0000_0000 438: 439: ;################################################# 440: ;# 441: ;# NI transmission of one channel 442: ;# 443: ;################################################# 444: ;# 445: ;# Interface: 446: ;# 447: ;# Input: r14 start address of event buf 448: ;# r1 number of time bins to rea 449: ;# r7 OR mask for the 32 bit wor 450: ;# 451: ;# Output: sends data to the NI outpu 452: ;# Modifies: r3, r4, r5, r14, r1 (0) 453: ;# 454: ;################################################# 455: 456: ;################# 457: ;# BEGIN data tran 458: ChTML: ;################# 459: 460: lpio+ r3 ; initial read has 0458 : 1110_1110_0000_0000_0000_0011 461: lpio+ r3 ; memory delay (sy 0459 : 1110_1110_0000_0000_0000_0011 462: lpio+ r4 045A : 1110_1110_0000_0000_0000_0100 463: lpio rio, r5 045B : 1110_0010_0000_0001_1100_0101 464: 465: shl 10, r5, r5 ; combine three 10 045C : 1011_0010_1010_0000_1010_0101 466: or r5, r4, r5 ; to one (32=10+10 045D : 1010_1010_0101_0000_1000_0101 467: shl 10, r5, r5 045E : 1011_0010_1010_0000_1010_0101 468: or r5, r3, r5 045F : 1010_1010_0101_0000_0110_0101 469: shl 2, r5, r5 0460 : 1011_0010_0010_0000_1010_0101 470: or r5, r7, r5 ; set the two LSBs 0461 : 1010_1010_0101_0000_1110_0101 471: 472: spio r5, NODP ; write to NI 0462 : 0010_0000_0101_0000_0000_0000 473: 474: sra+ r5 ; write to DMEM fo 0463 : 0011_1000_0101_0000_0000_0000 475: 476: sub r1, c3, r1 ; decrease number 0464 : 1000_1010_0001_0110_0110_0001 477: jmp cc_gtu, ChTML ; loop 0465 : 0000_0100_0000_0000_0000_1000 478: 479: xor r7, c1, r7 0466 : 1010_0010_0111_0110_0010_0111 480: jmp cc_uncond, rstack ; return from subr 0467 : 0000_1000_1000_0000_0000_1111 481: ;################# 482: ;# END data transf 483: ;################# 484: nop 0468 : 0000_0000_0000_0000_0000_0000 Source file read, 0 error(s), 0 warning(s).