Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.8, Jul 2008 SVN Revision 2158, SVN Date 2008-07-17 Please send any comments to: angelov@kip.uni-heidelberg.de 11:11:44 / 09 Mar 2009 Source code file: SRC/fitred.asm Memory initialisation file: Log file: WRK/cpu2.log Program memory size in words: 4096 Default constants, read from /usr/local/share/trap/asm_mimd.inc 1 CPU2 = 2 CC_SIGNED = 0X14 3 CC_NSIGNED = 0X04 4 CC_ZERO = 0X11 5 CC_NZERO = 0X01 6 CC_OVERFL = 0X13 7 CC_NOVERFL = 0X03 8 CC_NEG = 0X12 9 CC_NNEG = 0X02 10 CC_CARRY = 0X10 11 CC_NCARRY = 0X00 12 CC_BUSY = 0X17 13 CC_NBUSY = 0X07 14 CC_DIVB = 0X15 15 CC_NDIVB = 0X05 16 CC_ERRDIV = 0X16 17 CC_NERRDIV = 0X06 18 CC_UNCOND = 0X0F 19 CC_EQ = 0X11 20 CC_NEQ = 0X01 21 CC_NEG = 0X12 22 CC_POS0 = 0X02 23 CC_LTS = 0X14 24 CC_GES = 0X04 25 CC_LTU = 0X10 26 CC_GEU = 0X00 27 CC_LES = 0X19 28 CC_GTS = 0X09 29 CC_LEU = 0X18 30 CC_GTU = 0X08 31 RR_BYTE = 3 32 RR_WORD = 1 33 RR_DWORD = 0 34 LRA1 = LRA 3, 35 LRA2 = LRA 1, 36 LRA4 = LRA 0, 37 LRA4+ = LRA+ 0, 38 XOR = EOR 39 NOT = COM 40 SHLT = SHL 41 ANDT = AND 42 R0 = PRF[0] 43 R1 = PRF[1] 44 R2 = PRF[2] 45 R3 = PRF[3] 46 R4 = PRF[4] 47 R5 = PRF[5] 48 R6 = PRF[6] 49 R7 = PRF[7] 50 R8 = PRF[8] 51 R9 = PRF[9] 52 R10 = PRF[10] 53 R11 = PRF[11] 54 R12 = PRF[12] 55 R13 = PRF[13] 56 R14 = PRF[14] 57 R15 = PRF[15] 58 G0 = GRF[0] 59 G1 = GRF[1] 60 G2 = GRF[2] 61 G3 = GRF[3] 62 G4 = GRF[4] 63 G5 = GRF[5] 64 G6 = GRF[6] 65 G7 = GRF[7] 66 G8 = GRF[8] 67 G9 = GRF[9] 68 G10 = GRF[10] 69 G11 = GRF[11] 70 G12 = GRF[12] 71 G13 = GRF[13] 72 G14 = GRF[14] 73 G15 = GRF[15] 74 F0 = FIT[0] 75 F1 = FIT[1] 76 F2 = FIT[2] 77 F3 = FIT[3] 78 F4 = FIT[4] 79 F5 = FIT[5] 80 F6 = FIT[6] 81 F7 = FIT[7] 82 F8 = FIT[8] 83 F9 = FIT[9] 84 F10 = FIT[10] 85 F11 = FIT[11] 86 F12 = FIT[12] 87 F13 = FIT[13] 88 F14 = FIT[14] 89 F15 = FIT[15] 90 C0 = CON[0] 91 C1 = CON[1] 92 C2 = CON[2] 93 C3 = CON[3] 94 C4 = CON[4] 95 C5 = CON[5] 96 C6 = CON[6] 97 C7 = CON[7] 98 C8 = CON[8] 99 C9 = CON[9] 100 C10 = CON[10] 101 C11 = CON[11] 102 C12 = CON[12] 103 C13 = CON[13] 104 C14 = CON[14] 105 C15 = CON[15] 106 ASM_SVN_REV = 2158 1: ;########################################################### 2: ;# 3: ;# Rudimentary Readout Program for TRAP3 chip 4: ;# 5: ;# Marcus Gutfleisch, Venelin Angelov 6: ;# Universitaet Heidelberg, Kirchhoff-Institut fuer Physik 7: ;# 8: ;# $Id: fitred.asm 2666 2009-03-06 07:07:25Z angelov $: 9: ;# 10: ;########################################################### 11: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt tttt tttt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt tttt tttt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt tttt tttt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snme eeee ddd 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc cccc cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- ---- --St oam 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- ---- --St oam 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- ---- --St oam 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- ---- --St oam 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- ---- --St oam 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- ---- --St oam 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- ---- --St oam 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- ---- --St oam 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- ---- --St oam 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- ---- --St oam 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- ---- --St oam 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- ---- --St oam 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- ---- ---- --- 30: 31: #def CTGDINI=0x0B80; dddd dddd dddd dddd dddd dddd dddd dddd 32: #def CTGCTRL=0x0B81; ---- ---- ---- ---- ---S idce essb bbbb 33: #def CTGDOUT=0x0B82; DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 34: #def CTPDINI=0x0200; dddd dddd dddd dddd dddd dddd dddd dddd 35: #def CTPCTRL=0x0201; ---- ---- ---- ---- ---S idce essb bbbb 36: #def CTPDOUT=0x0202; DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 37: 38: #def PASADEL=0x3158; ---- ---- ---- ---- ---- ---- aaaa aaa 39: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- ---- --aa aaa 40: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- ---- --aa aaa 41: #def PASADAC=0x315B; ---- ---- ---- ---- ---- ---- aaaa aaa 42: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaaa aaaa aaa 43: #def PASASTL=0x315D; ---- ---- ---- ---- ---- ---- aaaa aaa 44: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- ---- ---- --- 45: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- ---- ---- --- 46: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaaa aaaa aaa 47: #def ADCINB=0x3051; ---- ---- ---- ---- ---- ---- ---- --m 48: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- ---- ---d ddd 49: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssbz hhhe app 50: #def ADCTST=0x3054; ---- ---- ---- ---- ---- ---- ---- --t 51: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- ---- ---- --- 52: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- ---- ---- --- 53: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- ---- ---- --- 54: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- ---- ---- -aa 55: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- ---- -ret aii 56: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaaa aaaa aaa 57: #def SADCEC=0x3166; ---- ---- ---- ---- ---- ---- -daa ate 58: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --AA AAAA AAA 59: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --AA AAAA AAA 60: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --AA AAAA AAA 61: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --AA AAAA AAA 62: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --AA AAAA AAA 63: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --AA AAAA AAA 64: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --AA AAAA AAA 65: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --AA AAAA AAA 66: #def SADCMC=0x3170; ---- ---- ---- ---- ---- ---- aaaa aaa 67: #def SADCOC=0x3171; ---- ---- ---- ---- ---- ---- aaaa aaa 68: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd cccc bbbb aaa 69: #def SADCTC=0x3173; ---- ---- ---- ---- ---- ---- ---- -aa 70: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -eaa aaaa aaa 71: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- ---- ---- -ee 72: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- ---- ---- -oo 73: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- ---- ---- -ii 74: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAAA AAAA AAA 75: #def TPPT0=0x3000; ---- ---- ---- ---- ---- ---- -ddd ddd 76: #def TPPAE=0x3004; ---- ---- ---- ---- ---- ---- -ddd ddd 77: #def TPPGR=0x3003; ---- ---- ---- ---- ---- ---- -ddd ddd 78: #def FLBY=0x3018; ---- ---- ---- ---- ---- ---- ---- --- 79: #def FLL=0x3100; ---- ---- ---- ---- ---- ---- --dd ddd 80: #def FPBY=0x3019; ---- ---- ---- ---- ---- ---- ---- --- 81: #def FPTC=0x3020; ---- ---- ---- ---- ---- ---- ---- --d 82: #def FPNP=0x3021; ---- ---- ---- ---- ---- ---d dddd ddd 83: #def FPCL=0x3022; ---- ---- ---- ---- ---- ---- ---- --- 84: #def FPA=0x3060; --dd dddd dddd dddd dddd dddd dddd ddd 85: #def FGBY=0x301A; ---- ---- ---- ---- ---- ---- ---- --- 86: #def FGFn=0x3080; ---- ---- ---- ---- ---- ---d dddd ddd 87: #def FGAn=0x30A0; ---- ---- ---- ---- ---- ---- --dd ddd 88: #def FGTA=0x3028; ---- ---- ---- ---- ---- dddd dddd ddd 89: #def FGTB=0x3029; ---- ---- ---- ---- ---- dddd dddd ddd 90: #def FGCL=0x302A; ---- ---- ---- ---- ---- ---- ---- --- 91: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd dddd dddd ddd 92: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd dddd dddd ddd 93: #def FTBY=0x301B; ---- ---- ---- ---- ---- ---- ---- --- 94: #def FTAL=0x3030; ---- ---- ---- ---- ---- --dd dddd ddd 95: #def FTLL=0x3031; ---- ---- ---- ---- ---- --dd dddd ddd 96: #def FTLS=0x3032; ---- ---- ---- ---- ---- --dd dddd ddd 97: #def FCBY=0x301C; ---- ---- ---- ---- ---- ---- ---- --- 98: #def FCWn=0x3038; ---- ---- ---- ---- ---- ---- dddd ddd 99: #def TPFS=0x3001; ---- ---- ---- ---- ---- ---- -ddd ddd 100: #def TPFE=0x3002; ---- ---- ---- ---- ---- ---- -ddd ddd 101: #def TPQS0=0x3005; ---- ---- ---- ---- ---- ---- -ddd ddd 102: #def TPQE0=0x3006; ---- ---- ---- ---- ---- ---- -ddd ddd 103: #def TPQS1=0x3007; ---- ---- ---- ---- ---- ---- -ddd ddd 104: #def TPQE1=0x3008; ---- ---- ---- ---- ---- ---- -ddd ddd 105: #def TPHT=0x3041; ---- ---- ---- ---- --dd dddd dddd ddd 106: #def TPVBY=0x3043; ---- ---- ---- ---- ---- ---- ---- --- 107: #def TPVT=0x3042; ---- ---- ---- ---- ---- ---- --dd ddd 108: #def TPFP=0x3040; ---- ---- ---- ---- ---- ---- --dd ddd 109: #def TPL=0x3180; ---- ---- ---- ---- ---- ---- ---d ddd 110: #def TPCL=0x3045; ---- ---- ---- ---- ---- ---- ---d ddd 111: #def TPCT=0x3044; ---- ---- ---- ---- ---- ---- ---d ddd 112: #def TPD=0x3047; ---- ---- ---- ---- ---- ---- ---- ddd 113: #def TPH=0x3140; ---- ---- ---- ---- ---- ---- ---d ddd 114: #def TPCBY=0x3046; ---- ---- ---- ---- ---- ---- ---- --- 115: #def TPCI0=0x3048; ---- ---- ---- ---- ---- ---- ---d ddd 116: #def TPCI1=0x3049; ---- ---- ---- ---- ---- ---- ---d ddd 117: #def TPCI2=0x304A; ---- ---- ---- ---- ---- ---- ---d ddd 118: #def TPCI3=0x304B; ---- ---- ---- ---- ---- ---- ---d ddd 119: #def EBD=0x3009; ---- ---- ---- ---- ---- ---- ---- -dd 120: #def EBSF=0x300C; ---- ---- ---- ---- ---- ---- ---- --- 121: #def EBAQA=0x300A; ---- ---- ---- ---- ---- ---- -ddd ddd 122: #def EBSIM=0x300D; ---- ---- ---- ---- ---- ---- ---- --- 123: #def EBSIA=0x300B; ---- ---- ---- ---- ---- ---- -ddd ddd 124: #def EBR=0x0800; ---- ---- ---- ---- ---- -pdd dddd ddd 125: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pdd dddd ddd 126: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pdd dddd ddd 127: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pdd dddd ddd 128: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pdd dddd ddd 129: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pdd dddd ddd 130: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pdd dddd ddd 131: #def EBW=0x2000; ---- ---- ---- ---- ---- --dd dddd ddd 132: #def EBPP=0x300E; ---- ---- ---- ---- ---- ---- ---- --- 133: #def EBPC=0x300F; ---- ---- ---- ---- ---- ---- ---- --- 134: #def EBP0=0x3010; ---- ---- ---- ---- ---- ---d dddd ddd 135: #def EBP1=0x3011; ---- ---- ---- ---- ---- ---d dddd ddd 136: #def EBP2=0x3012; ---- ---- ---- ---- ---- ---d dddd ddd 137: #def EBP3=0x3013; ---- ---- ---- ---- ---- ---d dddd ddd 138: #def EBIS=0x3014; ---- ---- ---- ---- ---- --dd dddd ddd 139: #def EBIT=0x3015; ---- ---- ---- ---- ---- dddd dddd ddd 140: #def EBIL=0x3016; ---- ---- ---- ---- ---- ---- dddd ddd 141: #def EBIN=0x3017; ---- ---- ---- ---- ---- ---- ---- --- 142: #def EBI=0x0980; dddd dddd dddd dddd dddd dddd dddd ddd 143: #def EBI0=0x0980; dddd dddd dddd dddd dddd dddd dddd dd 144: #def EBI1=0x0981; dddd dddd dddd dddd dddd dddd dddd dd 145: #def EBI2=0x0982; dddd dddd dddd dddd dddd dddd dddd dd 146: #def EBI3=0x0983; dddd dddd dddd dddd dddd dddd dddd dd 147: #def EBI4=0x0984; dddd dddd dddd dddd dddd dddd dddd dd 148: #def EBI5=0x0985; dddd dddd dddd dddd dddd dddd dddd dd 149: #def EBI6=0x0986; dddd dddd dddd dddd dddd dddd dddd dd 150: #def EBI7=0x0987; dddd dddd dddd dddd dddd dddd dddd dd 151: #def EBI8=0x0988; dddd dddd dddd dddd dddd dddd dddd dd 152: #def EBI9=0x0989; dddd dddd dddd dddd dddd dddd dddd dd 153: #def EBIA=0x098A; dddd dddd dddd dddd dddd dddd dddd dd 154: #def EBIB=0x098B; dddd dddd dddd dddd dddd dddd dddd dd 155: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- ---- ---- wwr 156: #def MEMRW=0xD000; ---- ---- ---- ---- ---- ---- -www wrr 157: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- ---b dddd iii 158: #def DMDELA=0xD002; ---- ---- ---- ---- ---- ---- ---- aaa 159: #def DMDELS=0xD003; ---- ---- ---- ---- ---- ---- ---- sss 160: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 161: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 162: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 163: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 164: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 165: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 166: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 167: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 168: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaaa aaaa aaa 169: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaaa aaaa aaa 170: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaaa aaaa aaa 171: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaaa aaaa aaa 172: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmmm mmmm mmm 173: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmmm mmmm mmm 174: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmmm mmmm mmm 175: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmmm mmmm mmm 176: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmmm mmmm mmm 177: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmmm mmmm mmm 178: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmmm mmmm mmm 179: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmmm mmmm mmm 180: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmmm mmmm mmm 181: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmmm mmmm mmm 182: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmmm mmmm mmm 183: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmmm mmmm mmm 184: #def NMOD=0x0D40; ---- ---- ---- ---- ---- ---- ---i cmm 185: #def NTRO=0x0D43; ---- ---- ---- --ii iddd cccb bbaa aff 186: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt tttt tttt ttt 187: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbbb aaaa aaa 188: #def NRRO=0x0D44; ---- ---- ---- --ii iddd cccb bbaa aff 189: #def NTP=0x0D46; pppp pppp pppp pppp pppp pppp pppp ppp 190: #def NP0=0x0D48; ---- ---- ---- ---- ---- -ppp pfff fec 191: #def NP1=0x0D49; ---- ---- ---- ---- ---- -ppp pfff fec 192: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -ppp pfff fec 193: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -ppp pfff fec 194: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLLL CCCC CCC 195: #def NED=0x0D42; ---- ---- ---- ---- orpp ppff ffcc css 196: #def NDLY=0x0D41; --jj jiii hhhg ggff feee dddc ccbb baa 197: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhhh llll lll 198: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DSS EHLZ YXW 199: #def NLE=0x00C2; ---- ---- ---- ---- ---- ---- EEEE EEE 200: #def NFE=0x0DC1; ---- ---- ---- ---- ---- ---- ---- DCB 201: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- ---- ---- --- 202: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- ---- ---S SSS 203: #def NITM0=0x0A08; ---- ---- ---- ---- --tt tttt tttt ttt 204: #def NITM1=0x0A09; ---- ---- ---- ---- --tt tttt tttt ttt 205: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt tttt tttt ttt 206: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt tttt tttt ttt 207: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd dddd dddd ddd 208: #def SMON=0x0A06; ---- ---- ---- ---- ---- dddd dddd ddd 209: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- dddd dddd ddd 210: #def NODP=0x0000; dddd dddd dddd dddd dddd dddd dddd ddd 211: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- ---- ---- 212: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- ---- ---- 213: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- ---- ---- 214: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- ---- ---- 215: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- ---- ---- 216: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- ---- ---- 217: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- ---- ---- 218: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- ---- ---- 219: #def GBUSR0=0x0300; -- readonly 220: #def GBUSR1=0x0301; -- readonly *** End of include file /usr/local/share/trap/conf_va.inc 13: ; #def set_NFSM_acq = 1 14: ; #def delay_hcm = 350 15: ; #def FIT2DM = 1; store the fitregisters in DMEM 16: #def trckl_delay = 13; 17: ; #def AVOID_DTR = 1; 18: 19: ; define at which event (full readout) to send the configura 20: ;#def ConfigEvent = 1; 21: 22: ;#def testmode_t = 1 ; for tracklets - not up to date, pl 23: 24: ; major version bits 25: ; - 1 bit as ZS flag 26: ; - 1 bit as tracklet disable flag 27: ; - 1 bit for ADC data/test pattern 28: ; if ZS then 29: ; - 1 bit: suppress sending of empty header/mask 30: ; - 2 bits: 01/10/11: send every 128/256/1024 events compl 31: ; else 32: ; if Testpattern Mode then 33: ; - 3 bits to define the pattern 34: ; else 35: ; - send full data, 1 bit: accumulate sum(ADC) and sum(ADC 36: ; ... 37: ; 38: ; -------------------- 39: ; Ressources in TRAP: 40: ; -------------------- 41: ; DMEM (without BM/HCM chips) 42: ; -------------------- 43: ; Word-Addr Byte-Addr Used for Copi 44: ; 45: ; 0..0x01F 0..0x07C 2**31/N LUT - 46: ; 0x020 0x080 pad row number g8 47: ; 0x021 0x084 y-coord offset g9 48: ; 0x022 0x088 deflection corr g10 49: ; 0x023 0x08C scale_y g11 50: ; 0x024 0x090 scale_d g12 51: ; 0x025 0x094 ndrift for fitprogram g13 52: ; 0x030..0x053 0x0C0..0x14C deflection range table 53: ; 54: ; 0x058..0x096 0x160..0x258 ADC statistics, see below: 55: ; 0x058+3*ch 0x160+12*ch ch=0..20, Sum(ADC) 56: ; 0x059+3*ch 0x164+12*ch ch=0..20, Sum(ADC**2), lower 57: ; 0x05A+3*ch 0x168+12*ch ch=0..20, Sum(ADC**2), highe 58: 59: ; 0x100..0x13F 0x400..0x4FC fit register for debugging 60: ; 0x140..0x143 0x500..0x50C tracklets for scsn readout 61: ; or 62: ; 0x100..0x2FF 0x400..0xBFF e/pi probability LUT (not im 63: 64: ; 0x300..0x33F 0xC00..0xCFF ADC data of CPU0 for scsn re 65: ; 0x340..0x37F 0xD00..0xDFF ADC data of CPU1 for scsn re 66: ; 0x380..0x3BF 0xE00..0xEFF ADC data of CPU2 for scsn re 67: ; 0x3C0..0x3FF 0xF00..0xFFF ADC data of CPU3 for scsn re 68: 69: 70: ; -------------------- 71: ; DBANK 72: ; -------------------- 73: ; Address Used for 74: ; 75: ; 0xF000..0xF0DF packed configuration, used for refreshin 76: ; 0xF0E0..0xF0FF packed configuration and single GIO inst 77: ; 0xF0E0..0xF0FF MCM3,7,11,15: mailbox, used for service 78: ; 0xF0F0..0xF0FF HCM only: headers for SCSN readout 79: 80: ; -------------------- 81: ; Constants 82: ; -------------------- 83: ; CPU0 84: ; 8 : the start address in GIO of the packed confi 85: ; 9 : counter for L0A without tracklet, CPU0 86: ; 10 : temporary used ifdef set_NFSM_acq 87: ; 11 : - 88: ; -------------------- 89: ; CPU1 90: ; 8 : HCM only, used to detect the first irq_clr 91: ; 9 : counter for L0A without tracklet, CPU1 92: ; 10 : - 93: ; 11 : - 94: ; -------------------- 95: ; CPU2 96: ; 8 : - 97: ; 9 : counter for L0A without tracklet, CPU2 98: ; 10 : - 99: ; 11 : - 100: ; -------------------- 101: ; CPU3 102: ; 8 : programmable network interface readout delay 103: ; 9 : counter for L0A without tracklet, CPU3 104: ; 10 : - 105: ; 11 : 106: ; -------------------- 107: ; CPU-all 108: ; 12 : event counter, incremented by CPU3 after raw 109: ; 13 : number of samples, used for raw data readout 110: ; 14 : Chip Position for MCM Header (bits 0..6) and 111: ; 15 : half-chamber header 0 112: 113: ; Testpatterns 114: ; 115: ;########################################################### 116: ;# 117: ;# defines 118: ;# 119: ;########################################################### 120: #def FIT_SVN_REV = $Rev: 2666 $; 121: ; ASM_SVN_REV is internally defined in the assembler, i 122: ; for I2C and JTAG 123: #def srv_command = 0xF0E0 124: #def srv_indata = 0xF0E1 125: #def srv_outdata = 0xF0F0 126: #def LP_REP = 0xF0E4 127: ; #def DBANKscsn = 1 ; store the ADC 128: ; otherwise use 129: 130: #def nachkommast = 5 131: #def minus_nachk = -5 132: #def rounding_add = 17; 2**(nachkommast-1)+1 133: #def pad_ext = 13; 8 + nachkommast. 134: 135: ; the constants here are used to move the corresponding bi 136: #def TPATTflag = -7; test pattern flag (raw data) in bi 137: #def ZSflag = -6; zero suppression flag in bit 5 138: #def TDISflag = -5; disable tracklets flag in bit 4 139: #def COSMflag = -4; cosmic trigger flag, bit 3 140: #def ZS_no_empty = -1; suppress sending of empty header/m 141: ; if so finally, some instructions can be optimized 142: #def OPTs = 0; options, 0..15 in bits 3..0, now u 143: 144: ; For the tracklet calculation 145: ; Name GIO Ad 146: #def pad_row_n = g8; pad row number 0xC020 147: #def yoffs = g9; y-coord offset 0xC021 148: #def defl_cor = g10; deflection corr 0xC022 149: #def scale_y = g11; 0.162354 = 0x29900000 / 2^32 0xC023 150: #def scale_d = g12; 0.185547 = 0x2F800000 / 2^32 0xC024 151: #def ndrift = g13; drift time in ADC samples 0xC025 152: 153: #def endsig_rr_tr = g15 ; end signature 154: #def nsamples = c13 ; number of ADC 155: #def ChipPOS = c14 ; Chip Position 156: #def EventCounter = c12 ; event counter 157: #def EvtCtrGIOAdr = 0xC04 ; Address of Eve 158: #def h_0 = c15 ; half-chamber h 159: #def func_code = g14 ; functional cod 160: #def L0AnTRcnt = c9 ; counter for L0 161: 162: #def rstack = r8 ; program counte 163: #def rio = r14 ; local I/O auto 164: #def mask_7F = g1 ; mask for the d 165: #def mask_FF = g2 ; mask for the t 166: #def mask_1FFF = g3 ; mask for the o 167: #def ClrCntCxx = c11 ; constant used 168: #ifdef cpu0 169: ; #def FIT_READ = 1 ; read the fitr 170: ; Note: Merging is not supported in this case! 171: 172: #def clk_onoff = CPU0SS ; own clock 173: #def LSBdata = 0x03 ; LSBs for data 174: #def AddrSCdata = 0xF000 ; Address in GIO 175: #def AddrDMdata = 0x0C00 ; Address in DM 176: #def AddrDMstat = 0x0160 ; Address in DM 177: #def lpcount0 = 0xF03C ; counts the num 178: #def lpcount1 = 0xF07C ; counts the num 179: #def adc_ch_msk = g4 180: #def L0AnTRcntIO = 0x0C01 181: ; #def TimerCPU = 0x0A0 ; timer to meas 182: ; #def TimerCPUsendc = 0x0A0 ; timer to meas 183: #def TrcklDMEMa = 0x500 ; store the trac 184: #def TPCI = TPCI0 ; 185: ;#def ClrCntGio = 0x0C03 186: #ifdef FIT_READ 187: #inc "fit_values0.asm" 188: #endif 189: #endif 190: 191: #ifdef cpu1 192: ; #def FIT_READ = 1 ; read the fitr 193: ; Note: Merging is not supported in this case! 194: 195: #def clk_onoff = CPU1SS ; own clock 196: #def LSBdata = 0x02 ; LSBs for data 197: #def AddrSCdata = 0xF040 ; Address in GIO 198: #def AddrDMdata = 0x0D00 ; Address in DM 199: #def AddrDMstat = 0x019C ; Address in DM 200: #def lpcount0 = 0xF03D ; counts the num 201: #def lpcount1 = 0xF07D ; counts the num 202: #def adc_ch_msk = g5 203: #def L0AnTRcntIO = 0x0C09 204: #def TrcklDMEMa = 0x504 ; store the trac 205: ; #def TimerCPU = 0x0A4 ; timer to meas 206: ; #def TimerCPUsendc = 0x0A4 ; timer to meas 207: #def TPCI = TPCI1 ; 208: ;#def ClrCntGio = 0x0C0B 209: #ifdef FIT_READ 210: #inc "fit_values1.asm" 211: #endif 212: #endif 213: 214: #ifdef cpu2 215: #def clk_onoff = CPU2SS ; own clock 216: #def LSBdata = 0x03 ; LSBs for data 217: #def AddrSCdata = 0xF080 ; Address in GIO 218: #def AddrDMdata = 0x0E00 ; Address in DM 219: #def AddrDMstat = 0x01D8 ; Address in DM 220: #def lpcount0 = 0xF03E ; counts the num 221: #def lpcount1 = 0xF07E ; counts the num 222: #def adc_ch_msk = g6 223: #def L0AnTRcntIO = 0x0C11 224: ; #def TimerCPU = 0x0A8 ; timer to meas 225: ; #def TimerCPUsendc = 0x0A8 ; timer to meas 226: #def TrcklDMEMa = 0x508 ; store the trac 227: #def TPCI = TPCI2 ; 228: ;#def ClrCntGio = 0x0C13 229: #ifdef FIT_READ 230: #inc "fit_values2.asm" 231: #endif 232: #endif 233: 234: #ifdef cpu3 235: #def clk_onoff = CPU3SS ; own clock 236: #def LSBdata = 0x02 ; LSBs for data 237: #def AddrSCdata = 0xF0C0 ; Address in GIO 238: #def AddrDMdata = 0x0F00 ; Address in DM 239: #def AddrDMstat = 0x0214 ; Address in DM 240: #def lpcount0 = 0xF03F ; counts the num 241: #def lpcount1 = 0xF07F ; counts the num 242: #def adc_ch_msk = g7 243: #def L0AnTRcntIO = 0x0C19 244: ; #def TimerCPU = 0x0AC ; timer to meas 245: ; #def TimerCPUsendc = 0x0AC ; timer to meas 246: #def TrcklDMEMa = 0x50C ; store the trac 247: #def TPCI = TPCI3 ; 248: ;#def ClrCntGio = 0x0C1B 249: #ifdef FIT_READ 250: #inc "fit_values3.asm" 251: #endif 252: #def NI_tmsn_delay = c8 ; programmable n 253: #endif 254: 255: 256: ;########################################################### 257: ;# 258: ;# 0x000: Infinite Loop at Instruction Memory Reset Address 259: ;# 260: ;########################################################### 261: 262: ORG 0x0; 263: lpw: 264: nop 0000 : 0000_0000_0000_0000_0000_0000 265: nop 0001 : 0000_0000_0000_0000_0000_0000 266: nop 0002 : 0000_0000_0000_0000_0000_0000 267: 268: iext lpcount0 0003 : 0101_0000_0000_0000_0000_1111 269: lgio 0, lpcount0 0004 : 1110_1100_1111_0000_0011_1110 270: jmpr cc_busy, 0 0005 : 0000_0100_0000_0000_1011_0111 271: lpio GBUSR0, r1 0006 : 1110_0110_0110_0000_0000_0001 272: add r1, c1, r1 0007 : 1000_0010_0001_0110_0010_0001 273: iext lpcount0 0008 : 0101_0000_0000_0000_0000_1111 274: sgio r1, lpcount0 0009 : 0010_1000_0001_0000_0011_1110 275: jmpr cc_uncond, 0 000A : 0000_0100_0000_0001_0100_1111 276: nop 000B : 0000_0000_0000_0000_0000_0000 277: 278: lpw2: 279: nop 000C : 0000_0000_0000_0000_0000_0000 280: nop 000D : 0000_0000_0000_0000_0000_0000 281: iext lpcount1 000E : 0101_0000_0000_0000_0000_1111 282: lgio 0, lpcount1 000F : 1110_1100_1111_0000_0111_1110 283: jmpr cc_busy, 0 0010 : 0000_0100_0000_0010_0001_0111 284: lpio GBUSR0, r1 0011 : 1110_0110_0110_0000_0000_0001 285: add r1, c1, r1 0012 : 1000_0010_0001_0110_0010_0001 286: iext lpcount1 0013 : 0101_0000_0000_0000_0000_1111 287: sgio r1, lpcount1 0014 : 0010_1000_0001_0000_0111_1110 288: jmpr cc_uncond, 0 0015 : 0000_0100_0000_0010_1010_1111 289: nop 0016 : 0000_0000_0000_0000_0000_0000 290: 291: 292: ;########################################################### 293: ;# 294: ;# 0x100: Interrupt Clear Jump Address 295: ;# 296: ;########################################################### 297: 298: ; In IRQ CLR some data are copied from DMEM to GRF 299: ; 1) read pad_row_n (pad row number) from 0xC020 and put in 300: ; 2) read yoffset (y-coordinate offset) from 0xC021 and put 301: ; 3) read defl_cor (deflection correction constant) from 0xC 302: ; 4) read scale_y : 0.162354 = 0x29900000 / 2^32 from 0xC023 303: ; 5) read scale_d : 0.185547 = 0x2F800000 / 2^32 from 0xC024 304: 305: 306: ORG 0x100; 307: 308: clr: 309: mov 0, r12 0100 : 1100_0110_0000_0000_0000_1100 310: #ifdef cpu0 311: #ifdef ClrCntGio 312: mov ClrCntCxx, r1 313: add r1, c1, r1 314: sgio r1, ClrCntGio 315: #endif 316: iext b1111_0000_0000_0000_0010_0000; 317: mov b1111_0000_0000_0000_0010_0000, r1 318: jmpr cc_busy, 0 319: sgio r1, SMOFFON ; switch off all NI 320: 321: mov 0x28, r0 ; clear NI fifo 322: jmpr cc_busy, 0 323: sgio r0, NMOD 324: 325: mov 0x08, r0 326: jmpr cc_busy, 0 327: sgio r0, NMOD 328: 329: #else ; cpu1,2,3 330: #ifdef ClrCntGio 331: mov ClrCntCxx, r1 332: add r1, c1, r1 333: sgio r1, ClrCntGio 334: #endif 335: ; check the type of the chip 336: swp ChipPOS, r1 ; the flags are in t 0101 : 0111_1010_0000_0111_1100_0001 337: andt r1, c3 ; if 0, HCM or BM 0102 : 1010_0100_0001_0110_0110_0000 338: jmp cc_zero, clr_bm_hcm 0103 : 0000_0100_0000_0000_0001_0001 339: 340: ; clr for normal chips, cpu1,2,3 341: 342: #ifdef cpu1 343: mov 0x080, r15; prepare for reading from DMEM, the I 344: mov 18, r0 ; or may be 17? 345: lra rr_dword, r1 346: lra+ rr_dword, r1 347: mov r1, pad_row_n 348: 349: lra rr_dword, r1 350: lra+ rr_dword, r1 351: shl pad_ext, r0, r0 ; 18*256*2**nachkomm 352: add r1, r0, yoffs 353: #endif 354: 355: #ifdef cpu2 356: mov 0x088, r15 ; prepare for readin 0104 : 1100_0110_0001_0001_0000_1111 357: nop 0105 : 0000_0000_0000_0000_0000_0000 358: nop 0106 : 0000_0000_0000_0000_0000_0000 359: lra rr_dword, r1 0107 : 1101_0010_0000_0000_0000_0001 360: lra+ rr_dword, r1 0108 : 1111_0010_0000_0000_0000_0001 361: mov r1, defl_cor 0109 : 1100_0010_0000_0000_0011_1010 362: 363: lra rr_dword, r1 010A : 1101_0010_0000_0000_0000_0001 364: lra+ rr_dword, r1 010B : 1111_0010_0000_0000_0000_0001 365: mov r1, scale_y 010C : 1100_0010_0000_0000_0011_1011 366: #endif 367: 368: #ifdef cpu3 369: mov 0x090, r15 ; prepare for readin 370: ; switch off the NIICE lvds cells 371: mov 0, r0 372: sgio r0, NIICE 373: lra rr_dword, r1 374: lra+ rr_dword, r1 375: mov r1, scale_d 376: lra rr_dword, r1 377: lra+ rr_dword, r1 378: mov r1, ndrift 379: #endif 380: #endif 381: clr_endloop: 382: nop 010D : 0000_0000_0000_0000_0000_0000 383: nop 010E : 0000_0000_0000_0000_0000_0000 384: nop 010F : 0000_0000_0000_0000_0000_0000 385: nop 0110 : 0000_0000_0000_0000_0000_0000 386: nop 0111 : 0000_0000_0000_0000_0000_0000 387: nop 0112 : 0000_0000_0000_0000_0000_0000 388: nop 0113 : 0000_0000_0000_0000_0000_0000 389: nop 0114 : 0000_0000_0000_0000_0000_0000 390: nop 0115 : 0000_0000_0000_0000_0000_0000 391: nop 0116 : 0000_0000_0000_0000_0000_0000 392: nop 0117 : 0000_0000_0000_0000_0000_0000 393: nop 0118 : 0000_0000_0000_0000_0000_0000 394: nop 0119 : 0000_0000_0000_0000_0000_0000 395: nop 011A : 0000_0000_0000_0000_0000_0000 396: nop 011B : 0000_0000_0000_0000_0000_0000 397: nop 011C : 0000_0000_0000_0000_0000_0000 398: nop 011D : 0000_0000_0000_0000_0000_0000 399: nop 011E : 0000_0000_0000_0000_0000_0000 400: jmpr cc_uncond, 0 011F : 0000_0100_0010_0011_1110_1111 401: nop 0120 : 0000_0000_0000_0000_0000_0000 402: 403: clr_bm_hcm: 404: #ifdef cpu1 405: mov c8, g0 ; flag to check if t 406: cmp r12, g0 ; r12=0, g0 is 0 (fi 407: jmp cc_neq, clr_endloop ; if r12 /= g0 - skip i 408: ; store 1 to c8 via GIO 409: mov 1, r0 410: sgio r0, 0xC08 411: ; init the privat counter/timer as counter/up/int/cont - 412: mov 0x640, r0 413: spio r0, CTPCTRL 414: spio r12, CTPDINI 415: #endif 416: 417: #ifdef cpu2 418: nop 0121 : 0000_0000_0000_0000_0000_0000 419: nop 0122 : 0000_0000_0000_0000_0000_0000 420: cmp r12, g0 ; r12 is 0, g0 is 0( 0123 : 1000_1000_1100_0010_0000_0000 421: jmp cc_neq clr_endloop 0124 : 0000_0100_0000_0000_0000_0001 422: ; init the privat counter/timer as counter/down/int/cont 423: mov 0xA40, r0 0125 : 1100_0111_0100_1000_0000_0000 424: spio r0, CTPCTRL 0126 : 0010_0000_0000_0010_0000_0001 425: mov 11, r0 0127 : 1100_0110_0000_0001_0110_0000 426: spio r0, CTPDINI 0128 : 0010_0000_0000_0010_0000_0000 427: #endif 428: 429: #ifdef cpu3 430: nop 431: ; switch off the NIICE lvds cells 432: mov 0, r0 433: sgio r0, NIICE 434: cmp r12, g0 435: jmp cc_neq, clr_endloop 436: ; init the privat counter/timer as counter/up/pre 437: mov 0x700, r0 438: spio r0, CTPCTRL 439: spio r12, CTPDINI 440: #endif 441: 442: jmp cc_uncond, clr_endloop 0129 : 0000_0100_0000_0000_0000_1111 443: nop 012A : 0000_0000_0000_0000_0000_0000 444: 445: 446: ;########################################################### 447: ;# 448: ;# 0x200: Interrupt Tracklet Processing Jump Address 449: ;# 450: ;########################################################### 451: 452: ORG 0x200; 453: 454: acq: 455: #ifdef TimerCPU 456: mov 0x640, r0 457: spio r0, CTPCTRL 458: mov 0, r0 459: spio r0, CTPDINI 460: #endif 461: 462: #ifndef testmode_t 463: ; by only one CPU! 464: #ifdef cpu0 465: shl nachkommast, c1, r13 466: neg r13, r13 ; load -2**nachk 467: nop 468: nop 469: ; switch on the NIICE lvds cells 470: mov 1, r0 471: sgio r0, NIICE 472: #endif 473: 474: #ifdef cpu1 475: shl nachkommast, c1, r13 476: neg r13, r13 ; load -2**nachk 477: mov 0x7F, mask_7F 478: ; copy the end signature words NES into GRF 479: mov 0xFF, mask_FF 480: iext 0x1FFF 481: mov 0x1FFF, mask_1FFF 482: #endif 483: 484: #ifdef cpu2 485: shl nachkommast, c1, r13 0200 : 1011_0010_0101_0110_0010_1101 486: neg r13, r13 ; load -2**nachk 0201 : 1010_1110_0000_0001_1010_1101 487: shl -11, h_0, func_code 0202 : 1011_0011_0101_0111_1111_1110 488: shl -11, func_code, func_code 0203 : 1011_0011_0101_0011_1101_1110 489: nop 0204 : 0000_0000_0000_0000_0000_0000 490: nop 0205 : 0000_0000_0000_0000_0000_0000 491: #endif 492: 493: #ifdef cpu3 494: lgio 0, NES 495: shl nachkommast, c1, r13 496: neg r13, r13 ; load -2**nachk 497: jmpr cc_busy, 0 498: lpio GBUSR0, r2 499: mov r2, endsig_rr_tr 500: #endif 501: 502: shlt TDISflag, func_code 0206 : 1011_0001_1011_0011_1100_0000 503: jmp cc_carry, acq_no_tr 0207 : 0000_0100_0000_0000_0001_0000 504: 505: shlt COSMflag, func_code 0208 : 1011_0001_1100_0011_1100_0000 506: jmp cc_carry, acq_cosmic 0209 : 0000_0100_0000_0000_0001_0000 507: 508: #ifdef AVOID_DTR 509: #ifdef FIT_READ 510: mov f00_value, adc_ch_msk 511: #else 512: mov f0, adc_ch_msk ; g[4+CPU#], same re 513: #endif 514: #endif 515: 516: 517: ;########################################### 518: ;# 519: ;# check for tracklets: CHANNEL !=31 520: ;# 521: ;########################################### 522: 523: #ifdef FIT_READ 524: mov f00_value, r8 525: cmp r8, 31 526: #else 527: cmp f0, 31 020A : 1100_1001_0000_0000_0001_1111 528: #endif 529: 530: jmp cc_eq, acq_no_tr ; if CHANNEL = 31 th 020B : 0000_0100_0000_0000_0001_0001 531: 532: #ifdef AVOID_DTR 533: #ifdef cpu1 534: #ifdef FIT_READ 535: sub r8, g4, r0 ; r0 = f0(CPU1) - f0 536: #else 537: sub f0, g4, r0 ; r0 = f0(CPU1) - f0 538: #endif 539: #endif 540: 541: #ifdef cpu2 542: #ifdef FIT_READ 543: sub r8, g5, r0 ; r0 = f0(CPU2) - f0 544: #else 545: sub f0, g5, r0 ; r0 = f0(CPU2) - f0 546: #endif 547: #endif 548: 549: #ifdef cpu3 550: #ifdef FIT_READ 551: sub r8, g6, r0 ; r0 = f0(CPU3) - f0 552: #else 553: sub f0, g6, r0 ; r0 = f0(CPU3) - f0 554: #endif 555: #endif 556: 557: #ifdef cpu0 558: nop 559: nop 560: nop 561: nop 562: nop 563: #else 564: cmp r0, c1 ; compare with 1 565: jmp cc_eq, acq_no_tr1 566: cmp r0, c7 ; compare with -1 567: jmp cc_eq, acq_no_tr2 568: #endif 569: #endif 570: 571: ;########################################### 572: ;# 573: ;# fit parameter calculation 574: ;# 575: ;# SLOPE = ( N * XY - X * Y ) / ( N * X 576: ;# OFFSET = ( XX * Y - X * XY ) / ( N * 577: ;# 578: ;########################################### 579: 580: #ifdef FIT_READ 581: mov f01_value, r15 ; f9_value is 0, f1 582: mov f03_value, r1 ; f3+f11, f11 is 0, 583: #else 584: add f1, f9, r15 ; N = N0 + N1 020C : 1000_0011_0001_0101_0010_1111 585: add f3, f11, r1 ; X = X0 + X1 020D : 1000_0011_0011_0101_0110_0001 586: #endif 587: mul32 r1, r1, r3 ; X * X 020E : 1001_0000_0001_0000_0010_1011 588: 589: #ifdef FIT_READ 590: iext f04_value 591: mov f04_value, r2 ; f4 is 14 bit, f12_ 592: #else 593: add f4, f12, r2 ; XX = XX0 + XX1 020F : 1000_0011_0100_0101_1000_0010 594: #endif 595: mul32 r15, r2, r4 ; N * XX 0210 : 1001_0000_1111_0000_0100_1100 596: 597: #ifdef FIT_READ 598: iext f02_value 599: mov f02_value, r7 600: #else 601: add f2, f10, r7 ; Q = Q0 + Q1 0211 : 1000_0011_0010_0101_0100_0111 602: #endif 603: sub r4, r3, r3 ; N * XX - X * 0212 : 1000_1010_0100_0000_0110_0011 604: 605: ; r12 = 0 in clear p 606: ; r13 = -4 in clear 607: 608: div r12, r3 ; 2**(32+nachkomma)/ 0213 : 1001_1000_1100_0000_0110_0000 609: 610: #ifdef FIT_READ 611: iext f05_value 612: mov f05_value, r5 613: #else 614: shl 8, f9, r5 ; 256 * N1 0214 : 1011_0010_1000_0101_0010_0101 615: add f13, r5, r5 ; Y1 + 256 * N1 0215 : 1000_0011_1101_0000_1010_0101 616: add f5, r5, r5 ; Y = Y0 + Y1 + 256 0216 : 1000_0011_0101_0000_1010_0101 617: #endif 618: 619: #ifdef FIT_READ 620: iext f06_value 621: mov f06_value, r6 622: #else 623: shl 8, f11, r6 ; 256 * X1 0217 : 1011_0010_1000_0101_0110_0110 624: add f14, r6, r6 ; XY1 + 256 * X 0218 : 1000_0011_1110_0000_1100_0110 625: add f6, r6, r6 ; XY = XY0 + XY1 + 2 0219 : 1000_0011_0110_0000_1100_0110 626: #endif 627: 628: mus32 r1, r5, r3 ; X * Y 021A : 1001_0100_0001_0000_1010_1011 629: mus32 r1, r6, r4 ; X * XY 021B : 1001_0100_0001_0000_1100_1100 630: mus32 r2, r5, r1 ; XX * Y 021C : 1001_0100_0010_0000_1010_1001 631: mus32 r15, r6, r2 ; N * XY 021D : 1001_0100_1111_0000_1100_1010 632: 633: sub r1, r4, r1 ; OF = XX * Y - X * 021E : 1000_1010_0001_0000_1000_0001 634: sub r2, r3, r2 ; SL = N * XY - X * 021F : 1000_1010_0010_0000_0110_0010 635: 636: shl 2, r15, r15 ; byte adressin 0220 : 1011_0010_0010_0001_1110_1111 637: 638: ; QA = low word of Q 639: shl -16, r7, r4 ; QB = high word of 0221 : 1011_0011_0000_0000_1110_0100 640: 641: lra rr_dword, r0 ; 2**31 / N 0222 : 1101_0010_0000_0000_0000_0000 642: lra rr_dword, r0 ; 2**31 / N 0223 : 1101_0010_0000_0000_0000_0000 643: 644: mul r0, r4, r0 ; QB * 2**31 / N 0224 : 1001_0000_0000_0000_1000_0000 645: nop ; do something usefu 0225 : 0000_0000_0000_0000_0000_0000 646: 647: and r13, mask_FF, r6 ; QB * 2**(-1) / N 0226 : 1010_0110_1101_0010_0100_0110 648: ; QB / N >= 2**10 no 649: shl 4, r6, r6 ; E.PROBABILITY & 0[ 0227 : 1011_0010_0100_0000_1100_0110 650: or r6, pad_row_n, r6 ; E.PROBABILITY & PA 0228 : 1010_1010_0110_0011_0000_0110 651: 652: die r7 ; get 2**(32+nachkom 0229 : 1001_1110_0000_0000_0000_0111 653: 654: mus r7, r1, r1 ; lower 32 bit word 022A : 1001_0100_0111_0000_0010_0001 655: mus r7, r2, r2 ; lower 32 bit word 022B : 1001_0100_0111_0000_0100_0010 656: 657: add r13, yoffs, r1 ; save the offset+ch 022C : 1000_0010_1101_0011_0010_0001 658: mus32 r13, ndrift, r2 ; save the slope * n 022D : 1001_0100_1101_0011_1010_1010 659: ; here we have: 660: ; offset in r1 (1 PAD = 256*2**nachkommast) 661: ; slope in r2 (1 PAD = 256*2**nachkommast) 662: 663: ; the deflection table is at address 0x0C0 in DMEM ( 664: 665: mov 0x0C0, r15 ; the start address 022E : 1100_0110_0001_1000_0000_1111 666: #ifdef FIT_READ 667: mov f00_value, r13 668: shl 3, r13, r13 669: #else 670: shl 3, f0, r13 ; 2**3 (=8) * ch - t 022F : 1011_0010_0011_0100_0000_1101 671: #endif 672: add r13, r15, r15 ; the address in DME 0230 : 1000_0010_1101_0001_1110_1111 673: 674: #ifdef FIT_READ 675: mov f00_value, r8 676: shl pad_ext, r8, r8 677: #else 678: shl pad_ext, f0, r8 ; 256*2**nachkomma 0231 : 1011_0010_1101_0100_0000_1000 679: #endif 680: sub r1, r8, r1 ; OFFSET [15] ( * 25 0232 : 1000_1010_0001_0001_0000_0001 681: add r2, defl_cor, r2 ; add the deflection 0233 : 1000_0010_0010_0011_0100_0010 682: 683: ; check if the deflection is in the proper range 684: lra rr_dword, r13 0234 : 1101_0010_0000_0000_0000_1101 685: lra+ rr_dword, r13 ; the min limit 0235 : 1111_0010_0000_0000_0000_1101 686: cmp r13, r2 0236 : 1000_1000_1101_0000_0100_0000 687: jmp cc_gts, acq_out_min ; jump if min > defl 0237 : 0000_0100_0000_0000_0000_1001 688: lra rr_dword, r13 0238 : 1101_0010_0000_0000_0000_1101 689: lra+ rr_dword, r13 ; the min limit 0239 : 1111_0010_0000_0000_0000_1101 690: cmp r2, r13 023A : 1000_1000_0010_0001_1010_0000 691: jmp cc_gts, acq_out_max ; jump if deflection 023B : 0000_0100_0000_0000_0000_1001 692: mov rounding_add, r8 ; prepare for the ro 023C : 1100_0110_0000_0010_0010_1000 693: mus r1, scale_y, r1 ; scale properly, th 023D : 1001_0100_0001_0011_0110_0001 694: mus r2, scale_d, r2 ; the result is in b 023E : 1001_0100_0010_0011_1000_0010 695: add r13, r8, r1 ; rounding, save the 023F : 1000_0010_1101_0001_0000_0001 696: add r13, r8, r2 0240 : 1000_0010_1101_0001_0000_0010 697: 698: sha minus_nachk, r1, r1 ; remove the 2 addit 0241 : 1011_0111_1011_0000_0010_0001 699: sha minus_nachk, r2, r2 0242 : 1011_0111_1011_0000_0100_0010 700: 701: and r1, mask_1FFF, r1 0243 : 1010_0110_0001_0010_0110_0001 702: and r2, mask_7F, r2 0244 : 1010_0110_0010_0010_0010_0010 703: 704: shl 7, r6, r6 ; prepare for OR wit 0245 : 1011_0010_0111_0000_1100_0110 705: or r6, r2, r6 ; put the deflection 0246 : 1010_1010_0110_0000_0100_0110 706: shl 13, r6, r6 ; prepare for OR wit 0247 : 1011_0010_1101_0000_1100_0110 707: or r6, r1, r6 ; the tracklet is re 0248 : 1010_1010_0110_0000_0010_0110 708: 709: ;########################################### 710: ;# 711: ;# tracklet synthesis and transmission 712: ;# Bits Name Size Type 1bit 713: ;# 12.. 0 OFFSET 13 signed 160u 714: ;# 19..13 DEFLECTION 7 signed 140u 715: ;# 23..20 PAD ROW 4 unsigned 1 716: ;# 31..24 QTOTAL 8 unsigned mea 717: ;# 718: ;########################################### 719: 720: acq_write_tr: 721: #ifdef trckl_delay 722: mov trckl_delay, r1 ; delay tra 0249 : 1100_0110_0000_0001_1010_0001 723: acq_tr_del: 724: sub r1, c1, r1 024A : 1000_1010_0001_0110_0010_0001 725: jmp cc_nzero, acq_tr_del 024B : 0000_0100_0000_0000_0000_0001 726: #endif 727: 728: #ifdef cpu0 729: mov b0000_0010_0000, r1 730: jmpr cc_busy, 0 731: sgio r1, SMOFF ; switch off clk_fil 732: #else 733: nop 024C : 0000_0000_0000_0000_0000_0000 734: nop 024D : 0000_0000_0000_0000_0000_0000 735: nop 024E : 0000_0000_0000_0000_0000_0000 736: #endif 737: 738: #ifdef set_NFSM_acq 739: #ifdef cpu0 740: lgio 0, NFSM 741: jmpr cc_busy, 0 742: lpio GBUSR0, r5 743: lgio 1, SMCMD 744: shl 12, r5, r5 745: jmpr cc_busy, 0 746: lpio GBUSR1, r4 747: or r5, r4, r5 748: sgio r5, 0xC02 749: #else 750: nop 751: nop 752: nop 753: nop 754: nop 755: nop 756: nop 757: nop 758: nop 759: #endif 760: #endif 761: acq_send_tr_mult: 762: #ifdef TimerCPU 763: lpio CTPDOUT, r5 ; the number of 764: #endif 765: spio r6, NODP 024F : 0010_0000_0110_0000_0000_0000 766: sra r6, TrcklDMEMa ; store in DMEM for debu 0250 : 0100_0000_0110_0101_0000_1000 767: #ifdef TimerCPU 768: sra r5, TimerCPU ; store in DMEM for debugg 769: #else 770: sra r6, TrcklDMEMa ; store in DMEM for debu 0251 : 0100_0000_0110_0101_0000_1000 771: #endif 772: ; spio r6, NODP ; second write to NI, n 773: jmp cc_uncond, clr_endloop 0252 : 0000_0100_0000_0000_0000_1111 774: nop 0253 : 0000_0000_0000_0000_0000_0000 775: 776: ;########################################### 777: ;# 778: ;# send end signature if there is no tr 779: ;# 780: ;# do any power management here (to be 781: ;# 782: ;########################################### 783: 784: acq_no_tr0: 785: nop 0254 : 0000_0000_0000_0000_0000_0000 786: nop 0255 : 0000_0000_0000_0000_0000_0000 787: nop 0256 : 0000_0000_0000_0000_0000_0000 788: nop 0257 : 0000_0000_0000_0000_0000_0000 789: acq_no_tr: 790: nop 0258 : 0000_0000_0000_0000_0000_0000 791: nop 0259 : 0000_0000_0000_0000_0000_0000 792: nop 025A : 0000_0000_0000_0000_0000_0000 793: acq_no_tr1: 794: nop 025B : 0000_0000_0000_0000_0000_0000 795: nop 025C : 0000_0000_0000_0000_0000_0000 796: nop 025D : 0000_0000_0000_0000_0000_0000 797: acq_no_tr2: 798: mov 16, r1 ; delay transmission 025E : 1100_0110_0000_0010_0000_0001 799: acq_nt_del: 800: sub r1, c1, r1 025F : 1000_1010_0001_0110_0010_0001 801: jmp cc_nzero, acq_nt_del 0260 : 0000_0100_0000_0000_0000_0001 802: acq_L1AnTRcnt: 803: mov L0AnTRcnt, r1 0261 : 1100_0010_0000_0111_0010_0001 804: add r1, c1, r1 0262 : 1000_0010_0001_0110_0010_0001 805: sgio r1, L0AnTRcntIO 0263 : 0010_1000_0001_1100_0001_0001 806: 807: mov endsig_rr_tr, r6 0264 : 1100_0010_0000_0011_1110_0110 808: jmp cc_uncond, acq_write_tr 0265 : 0000_0100_0000_0000_0000_1111 809: nop 0266 : 0000_0000_0000_0000_0000_0000 810: 811: acq_out_min: 812: nop 0267 : 0000_0000_0000_0000_0000_0000 813: nop 0268 : 0000_0000_0000_0000_0000_0000 814: nop 0269 : 0000_0000_0000_0000_0000_0000 815: nop 026A : 0000_0000_0000_0000_0000_0000 816: acq_out_max: 817: nop; 026B : 0000_0000_0000_0000_0000_0000 818: nop; 026C : 0000_0000_0000_0000_0000_0000 819: nop; 026D : 0000_0000_0000_0000_0000_0000 820: nop; 026E : 0000_0000_0000_0000_0000_0000 821: jmp cc_uncond, acq_L1AnTRcnt 026F : 0000_0100_0000_0000_0000_1111 822: nop 0270 : 0000_0000_0000_0000_0000_0000 823: 824: #else ; testmode_t=1 825: 826: ;########################################### 827: ;# 828: ;# Test mode, send tracklets from CPU0, 829: ;# 830: ;# depending on C14, C15 831: ;# 832: ;# The tracklet is composed so: 833: ;# 834: ;# [31..16] = c15[31..16] (ROC HEADER) 835: ;# [19..16] = bit mask, which CPU must 836: ;# [15.. 8] = c14[ 4.. 0] (MCM ID) 837: ;# [ 7.. 0] = C & CPU ID (c5) 838: ;# 839: ;########################################### 840: #ifdef cpu0 841: mov b0000_0010_0000, r1 842: jmpr cc_busy, 0 843: sgio r1, SMOFF ; switch off clk_fil 844: #else 845: nop ; could be omitted l 846: nop 847: nop 848: #endif 849: 850: 851: iext 0xFFFF 852: mov 0xFFFF, r0 853: swp r0, r0 854: and r0, c15, r0 855: mov 0x1F, r1 856: and r1, ChipPOS, r1 857: shl 8, r1, r1 858: or r1, r0, r0 859: mov 0xC0, r1 860: or r1, r0, r0 861: or r0, c5, r0 862: 863: shl -8, ChipPOS, r2 864: shl -8, r2, r2 865: neg c5, r3 866: shl r3, r2, r2 867: and r2, c1, r2 868: jmp cc_zero, acq_no_tr 869: shl 1, ChipPOS 870: jmp cc_nzero, acq_no_tr ; in case of BM or H 871: 872: 873: nop 874: mov 36, r1 ; delay transmission 875: acq_tr_del: 876: sub r1, c1, r1 877: jmp cc_nzero, acq_tr_del 878: nop 879: 880: spio r0, NODP 881: nop 882: 883: spio r0, NODP 884: jmpr cc_uncond, 0 885: nop 886: 887: acq_no_tr: 888: mov 36, r1 ; delay transmission 889: acq_nt_del: 890: sub r1, c1, r1 891: jmp cc_nzero, acq_nt_del 892: 893: mov endsig_rr_tr, r5 894: #ifdef cpu0 895: xor r5,c1,r5 ; emulate 1 bit erro 896: #else 897: nop 898: #endif 899: spio r5, NODP 900: nop 901: 902: spio r5, NODP 903: 904: jmpr cc_uncond, 0 905: nop 906: #endif 907: 908: 909: ;########################################### 910: ;# 911: ;# Test mode, send tracklets from CPU0, 912: ;# 913: ;# depending on C14, C15 914: ;# 915: ;# The tracklet is composed so: 916: ;# 917: ;# [31..16] = charge sum 918: ;# [15.. 0] = Hit Sum 919: ;# 920: ;########################################### 921: acq_cosmic: 922: SEM b1111_0000 0271 : 0001_0000_0000_0000_1111_0000 923: #ifdef cpu0 924: ; switch on the NIICE lvds cells 925: nop 926: nop 927: nop 928: mov 1, r0 929: sgio r0, NIICE 930: #endif 931: ; bypass the automatic selection of the fit-register 932: #ifdef cpu1 933: mov 0, r0 934: IEXT TPCBY 935: SGIO r0, TPCBY 936: nop 937: nop 938: #endif 939: #ifdef cpu2 940: nop 0272 : 0000_0000_0000_0000_0000_0000 941: nop 0273 : 0000_0000_0000_0000_0000_0000 942: nop 0274 : 0000_0000_0000_0000_0000_0000 943: nop 0275 : 0000_0000_0000_0000_0000_0000 944: nop 0276 : 0000_0000_0000_0000_0000_0000 945: #endif 946: #ifdef cpu3 947: iext TPFP 948: lgio 0, TPFP 949: jmpr cc_busy, 0 950: lpio GBUSR0, r5 951: mul32 r5, c3, r5 ; 3 channels in the 952: #endif 953: 954: #ifdef cpu0 955: iext TPCI0 956: mov TPCI0, r1 ; lower channel numb 957: mov 1, r2 ; start channel 958: add r2, c3, r3 ; end channel = star 959: mov 0x400, r15 ; start address in D 960: #endif 961: 962: #ifdef cpu1 963: iext TPCI1 964: mov TPCI1, r1 ; lower channel numb 965: mov 5, r2 ; start channel 966: add r2, c3, r3 ; end channel = star 967: mov 0x420, r15 ; start address in D 968: #endif 969: 970: #ifdef cpu2 971: iext TPCI2 0277 : 0101_0000_0000_0000_0000_0011 972: mov TPCI2, r1 ; lower channel numb 0278 : 1100_0110_0000_1001_0100_0001 973: mov 9, r2 ; start channel 0279 : 1100_0110_0000_0001_0010_0010 974: add r2, c4, r3 ; end channel = star 027A : 1000_0010_0010_0110_1000_0011 975: mov 0x440, r15 ; start address in D 027B : 1100_0110_1000_1000_0000_1111 976: #endif 977: 978: #ifdef cpu3 979: iext TPCI3 980: mov TPCI3, r1 ; lower channel numb 981: mov 14, r2 ; start channel 982: add r2, c4, r3 ; end channel = star 983: mov 0x468, r15 ; start address in D 984: #endif 985: sgio r2, r1 027C : 0010_0100_0010_0000_0010_0000 986: mov 0, r6 ; hit accu 027D : 1100_0110_0000_0000_0000_0110 987: mov 0, r7 ; charge accu 027E : 1100_0110_0000_0000_0000_0111 988: 989: acq_cosmic_next_ch: 990: jmpr cc_busy, 0 027F : 0000_0100_0100_1111_1111_0111 991: swp f8, r4 0280 : 0111_1010_0000_0101_0000_0100 992: or f9, r4, r4 0281 : 1010_1011_1001_0000_1000_0100 993: add r6, f9, r6 ; accumulate Nhits 0282 : 1000_0010_0110_0101_0010_0110 994: shl -16, f10, r4 0283 : 1011_0011_0000_0101_0100_0100 995: add r2, c1, r2 0284 : 1000_0010_0010_0110_0010_0010 996: sgio r2, r1 0285 : 0010_0100_0010_0000_0010_0000 997: add r7, r4, r7 ; accumulate Q 0286 : 1000_0010_0111_0000_1000_0111 998: cmp r2, r3 0287 : 1000_1000_0010_0000_0110_0000 999: jmp cc_leu, acq_cosmic_next_ch 0288 : 0000_0100_0000_0000_0001_1000 1000: 1001: ; here we have: 1002: ; the number of Hits in r6 1003: ; the accumulated charge (+ pedestal) in r7 1004: 1005: mov r6, adc_ch_msk 0289 : 1100_0010_0000_0000_1101_0110 1006: SYN 028A : 0000_1100_0000_0000_0000_0000 1007: SEM b1111_0000 028B : 0001_0000_0000_0000_1111_0000 1008: #ifdef cpu3 1009: add r6, g4, r6 1010: add r6, g5, r6 1011: add r6, g6, r6 1012: #else 1013: nop 028C : 0000_0000_0000_0000_0000_0000 1014: nop 028D : 0000_0000_0000_0000_0000_0000 1015: nop 028E : 0000_0000_0000_0000_0000_0000 1016: #endif 1017: mov r7, adc_ch_msk 028F : 1100_0010_0000_0000_1111_0110 1018: SYN 0290 : 0000_1100_0000_0000_0000_0000 1019: #ifdef cpu3 1020: add r7, g4, r7 1021: add r7, g5, r7 1022: add r7, g6, r7 1023: sra+ r7 1024: #else 1025: #ifdef cpu1 1026: mov 1, r0 ; switch back to aut 1027: IEXT TPCBY ; for the zero suppr 1028: SGIO r0, TPCBY 1029: nop 1030: #else 1031: nop 0291 : 0000_0000_0000_0000_0000_0000 1032: nop 0292 : 0000_0000_0000_0000_0000_0000 1033: nop 0293 : 0000_0000_0000_0000_0000_0000 1034: nop 0294 : 0000_0000_0000_0000_0000_0000 1035: #endif 1036: #endif 1037: 1038: #ifdef cpu3 1039: mul32 r5, r6, r5 ; the pedestal in th 1040: sra+ r5 1041: shl -2, r5, r5 ; the TPFP is with 2 1042: sub r7, r5, r7 ; the charge without 1043: sra+ r7 1044: #else 1045: mov 0, r6 0295 : 1100_0110_0000_0000_0000_0110 1046: mov 0, r7 0296 : 1100_0110_0000_0000_0000_0111 1047: nop 0297 : 0000_0000_0000_0000_0000_0000 1048: nop 0298 : 0000_0000_0000_0000_0000_0000 1049: nop 0299 : 0000_0000_0000_0000_0000_0000 1050: #endif 1051: 1052: mov 0x1F, r1 029A : 1100_0110_0000_0011_1110_0001 1053: shl -3, c10, r0 ; the min hits is in 029B : 1011_0011_1101_0111_0100_0000 1054: and r1, r0, r0 029C : 1010_0110_0001_0000_0000_0000 1055: cmp r6, r0 ; min number of hits 029D : 1000_1000_0110_0000_0000_0000 1056: jmp cc_leu, acqco_no_tr 029E : 0000_0100_0000_0000_0001_1000 1057: shl -8, c10, r1 ; the min cluster cha 029F : 1011_0011_1000_0111_0100_0001 1058: cmp r7, r1 02A0 : 1000_1000_0111_0000_0010_0000 1059: jmp cc_leu, acqco_no_tr 02A1 : 0000_0100_0000_0000_0001_1000 1060: mov 0x7, r0 02A2 : 1100_0110_0000_0000_1110_0000 1061: and r0, c10, r0 ; the shift (right) 02A3 : 1010_0110_0000_0111_0100_0000 1062: neg r0, r0 02A4 : 1010_1110_0000_0000_0000_0000 1063: shl r0, r7, r7 ; shift right the ch 02A5 : 0111_0010_0000_0000_1110_0111 1064: shl r0, r1, r1 ; shift right the th 02A6 : 0111_0010_0000_0000_0010_0001 1065: cmp r7, 0xFF ; check if Q > 255 02A7 : 1100_1000_0111_0000_1111_1111 1066: jmpr cc_leu, +2 02A8 : 0000_0100_0101_0101_0101_1000 1067: mov 0xFF, r7 ; clip to 255 02A9 : 1100_0110_0001_1111_1110_0111 1068: cmp r1, 0xFF ; check if Q > 255 02AA : 1100_1000_0001_0000_1111_1111 1069: jmpr cc_leu, +2 02AB : 0000_0100_0101_0101_1011_1000 1070: mov 0xFF, r1 ; clip to 255 02AC : 1100_0110_0001_1111_1110_0001 1071: shl 8, r7, r7 ; shift left 8 bits 02AD : 1011_0010_1000_0000_1110_0111 1072: or r7, r1, r7 ; add the threshold 02AE : 1010_1010_0111_0000_0010_0111 1073: shl 8, r7, r7 ; shift left 8 bits 02AF : 1011_0010_1000_0000_1110_0111 1074: or r7, r6, r6 ; add the Nhits 02B0 : 1010_1010_0111_0000_1100_0110 1075: shl 8, r6, r6 ; shift left 8 bits 02B1 : 1011_0010_1000_0000_1100_0110 1076: mov 0xFF, r1 ; 02B2 : 1100_0110_0001_1111_1110_0001 1077: and r1, c10, r1 ; lower 8 bits of c1 02B3 : 1010_0110_0001_0111_0100_0001 1078: or r1, r6, r6 ; COSMIC_Q_SHR | COS 02B4 : 1010_1010_0001_0000_1100_0110 1079: ; the tracklet is ready! 1080: 1081: jmp cc_uncond, acq_send_tr_mult 02B5 : 0000_0100_0000_0000_0000_1111 1082: nop 02B6 : 0000_0000_0000_0000_0000_0000 1083: 1084: acqco_no_tr: 1085: mov 6, r6 02B7 : 1100_0110_0000_0000_1100_0110 1086: sub r6, c1, r6 02B8 : 1000_1010_0110_0110_0010_0110 1087: jmpr cc_nzero, -1 02B9 : 0000_0100_0101_0111_0000_0001 1088: mov endsig_rr_tr, r6 02BA : 1100_0010_0000_0011_1110_0110 1089: jmp cc_uncond, acq_send_tr_mult 02BB : 0000_0100_0000_0000_0000_1111 1090: 1091: ;########################################################### 1092: ;# 1093: ;# 0x400: Interrupt Raw Data Transmission Jump Address 1094: ;# 1095: ;########################################################### 1096: 1097: ORG 0x400 1098: 1099: raw: 1100: 1101: #ifdef cpu0 1102: mov cmd_CPU_done r0 ; CPU0 indicates upc 1103: sgio r0 SMCMD; 1104: nop 1105: #endif 1106: #ifdef cpu1 1107: mov 1, r0 ; switch back to automat 1108: IEXT TPCBY ; for the zero suppressi 1109: SGIO r0, TPCBY ; already done in cosmic 1110: #endif 1111: #ifdef cpu3 1112: iext EBSIM 1113: lgio 1, EBSIM 1114: nop 1115: #endif 1116: #ifdef cpu2 1117: nop 0400 : 0000_0000_0000_0000_0000_0000 1118: nop 0401 : 0000_0000_0000_0000_0000_0000 1119: nop 0402 : 0000_0000_0000_0000_0000_0000 1120: #endif 1121: 1122: ;############################################## 1123: ;# Store Start addresses for SCSN transfer via Databank 1124: ;############################################## 1125: 1126: #ifdef DBANKscsn 1127: iext AddrSCdata 1128: mov AddrSCdata, rio 1129: #else 1130: mov AddrDMstat, r15 0403 : 1100_0110_0011_1011_0000_1111 1131: swp r15, r15 0404 : 0111_1010_0000_0001_1110_1111 1132: mov AddrDMdata, r2 0405 : 1100_0111_1100_0000_0000_0010 1133: or r15, r2, r15 0406 : 1010_1010_1111_0000_0100_1111 1134: #endif 1135: 1136: swp ChipPOS, r2 ; load NI&SCSN reado 0407 : 0111_1010_0000_0111_1100_0010 1137: 1138: shlt -3, r2 ; move bit 2 to C fl 0408 : 1011_0001_1101_0000_0100_0000 1139: jmp cc_carry, raw_hc0 ; bit 2=1 means addi 0409 : 0000_0100_0000_0000_0001_0000 1140: 1141: #ifdef DBANKscsn 1142: swp rio, rio ; swap DBANK address 1143: #endif 1144: andt r2, c3 040A : 1010_0100_0010_0110_0110_0000 1145: jmp cc_zero, raw_complete_ni_tmsn ; check for transmis 040B : 0000_0100_0000_0000_0001_0001 1146: 1147: #ifdef ConfigEvent 1148: mov EventCounter, r0 1149: cmp r0, ConfigEvent 1150: jmp cc_eq, raw_send_conf 1151: #endif 1152: 1153: #ifdef cpu0 1154: shl 7, c1, r0 1155: or r0, ChipPOS, r0 ; combine chip heade 1156: shl 12, r0, r0 1157: shl 12, r0, r0 ; 1 & ChipPOS(7) & 2 1158: mov 0xC, r1 1159: or r0, r1, r0 ; 1 & ChipPOS(7) & 2 1160: or r0, g5, r11 ; 1 & ChipPOS(7) & E 1161: ; do not send the MCM Header now 1162: #ifdef DBANKscsn 1163: swp rio, rio 1164: sgio+ r11 ; no busy flag check 1165: swp rio, rio ; till next access 1166: #else 1167: sra+ r11 1168: #endif 1169: #endif 1170: 1171: #ifdef cpu1 1172: ; this CPU helps to CPU0 to prepare the event counter fi 1173: iext 0xFFFFF ; 20 bits with 1 1174: mov 0xFFFFF, r0 ; mask for the event 1175: and r0, EventCounter, r0 ; event counter's 20 1176: shl 4, r0, g5 ; the lower 20 bits 1177: jmp cc_uncond raw_check_zs 1178: nop 1179: nop 1180: nop 1181: #ifdef DBANKscsn 1182: nop 1183: nop 1184: #endif 1185: #endif 1186: 1187: #ifdef cpu2 1188: nop 040C : 0000_0000_0000_0000_0000_0000 1189: nop 040D : 0000_0000_0000_0000_0000_0000 1190: nop 040E : 0000_0000_0000_0000_0000_0000 1191: nop 040F : 0000_0000_0000_0000_0000_0000 1192: nop 0410 : 0000_0000_0000_0000_0000_0000 1193: nop 0411 : 0000_0000_0000_0000_0000_0000 1194: nop 0412 : 0000_0000_0000_0000_0000_0000 1195: jmp cc_uncond raw_check_zs 0413 : 0000_0100_0000_0000_0000_1111 1196: #ifdef DBANKscsn 1197: nop 1198: nop 1199: #endif 1200: #endif 1201: 1202: #ifdef cpu3 1203: mov 1, r0 ; in case of simulat 1204: iext EBSIM ; the mode must be s 1205: sgio r0, EBSIM ; the event buffers 1206: jmp cc_uncond raw_check_zs 1207: nop 1208: nop 1209: nop 1210: nop 1211: #ifdef DBANKscsn 1212: nop 1213: nop 1214: #endif 1215: #endif 1216: 1217: raw_check_zs: 1218: 1219: #ifdef DBANKscsn 1220: iext 0xFFFF0000 ; high word mask for 1221: mov 0xFFFF0000, r15 ; Note: this works b 1222: #endif 1223: 1224: mov nsamples, r1 ; initially load num 0414 : 1100_0010_0000_0111_1010_0001 1225: cmp r1, 0 0415 : 1100_1000_0001_0000_0000_0000 1226: jmp cc_zero, raw_complete_ni_tmsn ; check for transmis 0416 : 0000_0100_0000_0000_0001_0001 1227: 1228: ; first check if the zero suppression is on 1229: shlt ZSflag, func_code 0417 : 1011_0001_1010_0011_1100_0000 1230: jmp cc_ncarry raw_no_zsup 0418 : 0000_0100_0000_0000_0000_0000 1231: 1232: ; ZERO SUPPRESSION case 1233: ; check if some events should be send without ZS 1234: SEM b1111_0000 ; sync mask for the 0419 : 0001_0000_0000_0000_1111_0000 1235: shl OPTs, func_code, r8 041A : 1011_0010_0000_0011_1100_1000 1236: shl -1, r8, r8 ; only bits 2..1 041B : 1011_0011_1111_0001_0000_1000 1237: and r8, c3, r8 041C : 1010_0110_1000_0110_0110_1000 1238: jmp cc_zero, raw_ebi_read ; 00 means normal ZS 041D : 0000_0100_0000_0000_0001_0001 1239: mov 0x07F, r9 ; in case of 01 041E : 1100_0110_0000_1111_1110_1001 1240: cmp r8, 2 041F : 1100_1000_1000_0000_0000_0010 1241: jmpr cc_neq, +2 0420 : 0000_0100_1000_0100_0100_0001 1242: mov 0x0FF, r9 ; in case of 10 0421 : 1100_0110_0001_1111_1110_1001 1243: cmp r8, 3 0422 : 1100_1000_1000_0000_0000_0011 1244: jmpr cc_neq, +2 0423 : 0000_0100_1000_0100_1010_0001 1245: mov 0x3FF, r9 ; in case of 11 0424 : 1100_0110_0111_1111_1110_1001 1246: and r9, EventCounter, r9 ; take the lower n-b 0425 : 1010_0110_1001_0111_1000_1001 1247: cmp r9, 1 ; and compare with 1 0426 : 1100_1000_1001_0000_0000_0001 1248: jmp cc_neq, raw_ebi_read ; normal ZS mode 0427 : 0000_0100_0000_0000_0000_0001 1249: #ifdef cpu3 1250: mov b11_1111, r6 ; set which channels 1251: #else 1252: mov b01_1111, r6 ; set which channels 0428 : 1100_0110_0000_0011_1110_0110 1253: #endif 1254: jmp cc_uncond, raw_ebiscan_done ; skip the reading o 0429 : 0000_0100_0000_0000_0000_1111 1255: 1256: ; now read the indicators and mark the ADC channels with 1257: raw_ebi_read: 1258: mov c1, r8 ; mask, will be shif 042A : 1100_0010_0000_0110_0010_1000 1259: mov EBI0, r9 ; address of the fir 042B : 1100_0111_0011_0000_0000_1001 1260: 1261: 1262: mov 15, r10 042C : 1100_0110_0000_0001_1110_1010 1263: mov nsamples, r0 042D : 1100_0010_0000_0111_1010_0000 1264: mov 1, r6 ; r6 = 1 042E : 1100_0110_0000_0000_0010_0110 1265: cmp r0, 15 ; if shift distance 042F : 1100_1000_0000_0000_0000_1111 1266: jmp cc_leu, raw_ebi_mask 0430 : 0000_0100_0000_0000_0001_1000 1267: sub r0, r10, r0 ; decrease the dista 0431 : 1000_1010_0000_0001_0100_0000 1268: shl 15, r6, r6 ; and shift the r6 t 0432 : 1011_0010_1111_0000_1100_0110 1269: 1270: cmp r0, 15 ; compare again the 0433 : 1100_1000_0000_0000_0000_1111 1271: jmp cc_leu, raw_ebi_mask ; and jump to shift 0434 : 0000_0100_0000_0000_0001_1000 1272: sub r0, r10, r0 ; decrease the dista 0435 : 1000_1010_0000_0001_0100_0000 1273: shl 15, r6, r6 ; and shift the r6 t 0436 : 1011_0010_1111_0000_1100_0110 1274: 1275: raw_ebi_mask: 1276: shl r0, r6, r6 ; r6 = r6 << r0 (rem 0437 : 0111_0010_0000_0000_1100_0110 1277: sub r6, c1, r10 ; r10 (mask) = r6 - 0438 : 1000_1010_0110_0110_0010_1010 1278: mov c0, r6 ; clear r6 0439 : 1100_0010_0000_0110_0000_0110 1279: 1280: raw_ebiscan: 1281: lpio r9, r0 ; read twice because 043A : 1110_0010_0000_0001_0010_0000 1282: lpio r9, r0 043B : 1110_0010_0000_0001_0010_0000 1283: not r0, r0 ; invert the mask, a 043C : 1011_1110_0000_0000_0000_0000 1284: and r0, r10, r0 ; mask the unused bi 043D : 1010_0110_0000_0001_0100_0000 1285: jmpr cc_zero, +2 043E : 0000_0100_1000_1000_0001_0001 1286: or r6, r8, r6 ; set the bit!!! 043F : 1010_1010_0110_0001_0000_0110 1287: add r9, c2, r9 ; increment the addr 0440 : 1000_0010_1001_0110_0100_1001 1288: shl 1, r8, r8 ; shift the mask lef 0441 : 1011_0010_0001_0001_0000_1000 1289: #ifdef cpu3 1290: cmp r8, b100_0000 ; check for last cha 1291: #else 1292: cmp r8, b010_0000 ; check for last cha 0442 : 1100_1000_1000_0000_0010_0000 1293: #endif 1294: jmp cc_neq, raw_ebiscan 0443 : 0000_0100_0000_0000_0000_0001 1295: 1296: ; the adc mask in r6 is not absolute, now shift properly 1297: raw_ebiscan_done: 1298: #ifdef cpu0 1299: nop ; cpu0 has channels 1300: #endif 1301: #ifdef cpu1 1302: shl 5, r6, r6 ; cpu1 has channels 1303: #endif 1304: #ifdef cpu2 1305: shl 10, r6, r6 ; cpu2 has channels 0444 : 1011_0010_1010_0000_1100_0110 1306: #endif 1307: #ifdef cpu3 1308: shl 15, r6, r6 ; cpu3 has channels 1309: #endif 1310: 1311: ; calculate the ADC mask for the zero suppression in cas 1312: cmp f8, 0 ; ch+1 is 0 if no tr 0445 : 1100_1001_1000_0000_0000_0000 1313: jmp cc_zero raw_notrack 0446 : 0000_0100_0000_0000_0001_0001 1314: mov 0xF, r0 ; 1111b, take the 4 0447 : 1100_0110_0000_0001_1110_0000 1315: cmp f9, 0 ; number of hits in 0448 : 1100_1001_1001_0000_0000_0000 1316: jmp cc_nzero raw_4pads 0449 : 0000_0100_0000_0000_0000_0001 1317: shl -1, r0, r0 ; 0111b but if ch+1 044A : 1011_0011_1111_0000_0000_0000 1318: raw_4pads: 1319: mov f0, r1 044B : 1100_0010_0000_0100_0000_0001 1320: cmp r1, 16 ; the max shift left 044C : 1100_1000_0001_0000_0001_0000 1321: jmpr cc_ltu, +3 044D : 0000_0100_1000_1010_0001_0000 1322: shl 4, r0, r0 044E : 1011_0010_0100_0000_0000_0000 1323: sub r1, c4, r1 044F : 1000_1010_0001_0110_1000_0001 1324: ; continue, r1 is < 16 here 1325: shl r1, r0, r0 ; X111b << f0, here 0450 : 0111_0010_0001_0000_0000_0000 1326: or r0, r6, r6 0451 : 1010_1010_0000_0000_1100_0110 1327: raw_notrack: 1328: mov r6, adc_ch_msk 0452 : 1100_0010_0000_0000_1101_0110 1329: SYN; 0453 : 0000_1100_0000_0000_0000_0000 1330: SEM b1111_0000 ; sync mask for the 0454 : 0001_0000_0000_0000_1111_0000 1331: ; here all CPUs start simultaneously 1332: 1333: or r6, g4, r6 ; CPU0 0455 : 1010_1010_0110_0010_1000_0110 1334: or r6, g5, r6 ; CPU1 0456 : 1010_1010_0110_0010_1010_0110 1335: or r6, g6, r6 ; CPU2 0457 : 1010_1010_0110_0010_1100_0110 1336: or r6, g7, r6 ; CPU3 0458 : 1010_1010_0110_0010_1110_0110 1337: 1338: ; shift back to the right to get the mask relative to th 1339: #ifdef cpu0 1340: nop 1341: #endif 1342: #ifdef cpu1 1343: shl -5, r6, r6 1344: #endif 1345: #ifdef cpu2 1346: shl -10, r6, r6 0459 : 1011_0011_0110_0000_1100_0110 1347: #endif 1348: #ifdef cpu3 1349: shl -15, r6, r6 1350: #endif 1351: 1352: ; count the number of 1 in r6 1353: mov 0, r7 ; clear the counter 045A : 1100_0110_0000_0000_0000_0111 1354: shlt -1, r6 ; copy bit 0 to carr 045B : 1011_0001_1111_0000_1100_0000 1355: adc r7, c0, r7 ; add the carry to r 045C : 1000_0110_0111_0110_0000_0111 1356: shlt -2, r6 ; copy bit 1 to carr 045D : 1011_0001_1110_0000_1100_0000 1357: adc r7, c0, r7 ; add the carry to r 045E : 1000_0110_0111_0110_0000_0111 1358: shlt -3, r6 ; copy bit 2 to carr 045F : 1011_0001_1101_0000_1100_0000 1359: adc r7, c0, r7 ; add the carry to r 0460 : 1000_0110_0111_0110_0000_0111 1360: shlt -4, r6 ; copy bit 3 to carr 0461 : 1011_0001_1100_0000_1100_0000 1361: adc r7, c0, r7 ; add the carry to r 0462 : 1000_0110_0111_0110_0000_0111 1362: shlt -5, r6 ; copy bit 4 to carr 0463 : 1011_0001_1011_0000_1100_0000 1363: adc r7, c0, r7 ; add the carry to r 0464 : 1000_0110_0111_0110_0000_0111 1364: #ifdef cpu3 1365: shlt -6, r6 ; copy bit 5 to carr 1366: adc r7, c0, r7 ; add the carry to r 1367: #else 1368: nop 0465 : 0000_0000_0000_0000_0000_0000 1369: nop 0466 : 0000_0000_0000_0000_0000_0000 1370: #endif 1371: 1372: mov r7, adc_ch_msk ; move to GRF 0467 : 1100_0010_0000_0000_1111_0110 1373: SYN 0468 : 0000_1100_0000_0000_0000_0000 1374: #ifdef cpu0 1375: add r7, g5, r7 ; accumulate all num 1376: add r7, g6, r7 ; accumulate all num 1377: add r7, g7, r7 ; accumulate all num 1378: #else 1379: nop 0469 : 0000_0000_0000_0000_0000_0000 1380: nop 046A : 0000_0000_0000_0000_0000_0000 1381: nop 046B : 0000_0000_0000_0000_0000_0000 1382: #endif 1383: nop 046C : 0000_0000_0000_0000_0000_0000 1384: mov r6, adc_ch_msk ; copy back the adc 046D : 1100_0010_0000_0000_1101_0110 1385: mov raw_ChTML_adc, r9 ; use the ADC transf 046E : 1100_0110_0000_0000_0000_1001 1386: #ifdef cpu0 1387: nop 1388: #else 1389: jmp cc_uncond, raw_transf_ch ; cpu0 must send the 046F : 0000_0100_0000_0000_0000_1111 1390: #endif; 1391: 1392: ; CPU0 only 1393: shlt ZS_no_empty, func_code 0470 : 1011_0001_1111_0011_1100_0000 1394: jmpr cc_ncarry +3 0471 : 0000_0100_1000_1110_1000_0000 1395: cmp r7, 0 0472 : 1100_1000_0111_0000_0000_0000 1396: jmp cc_eq raw_transf_ch ; skip sending of MC 0473 : 0000_0100_0000_0000_0001_0001 1397: ; start storing the 1398: 1399: spio r11 NODP ; NI transfer chip h 0474 : 0010_0000_1011_0000_0000_0000 1400: ; combine the full mask 1401: not r7, r7 ; the number of ADC 0475 : 1011_1110_0000_0000_1110_0111 1402: shl 13, r7, r7 0476 : 1011_0010_1101_0000_1110_0111 1403: shl 13, r7, r7 0477 : 1011_0010_1101_0000_1110_0111 1404: shl -1, r7, r7 0478 : 1011_0011_1111_0000_1110_0111 1405: shl 2, r6, r6 0479 : 1011_0010_0010_0000_1100_0110 1406: or r6, c3, r6 ; 11 047A : 1010_1010_0110_0110_0110_0110 1407: shl 2, r6, r6 ; 01 & not(ADC count 047B : 1011_0010_0010_0000_1100_0110 1408: or r7, r6, r6 047C : 1010_1010_0111_0000_1100_0110 1409: spio r6, NODP ; send the ADC mask 047D : 0010_0000_0110_0000_0000_0000 1410: 1411: jmp cc_uncond raw_transf_ch 047E : 0000_0100_0000_0000_0000_1111 1412: 1413: raw_no_zsup: 1414: 1415: #ifdef cpu0 1416: spio r11 NODP ; NI transfer chip h 1417: #else 1418: nop 047F : 0000_0000_0000_0000_0000_0000 1419: #endif 1420: 1421: #ifdef cpu3 1422: mov b11_1111, adc_ch_msk ; show which channel 1423: #else 1424: mov b01_1111, adc_ch_msk ; show which channel 0480 : 1100_0110_0000_0011_1111_0110 1425: #endif 1426: 1427: shlt TPATTflag, func_code 0481 : 1011_0001_1001_0011_1100_0000 1428: jmp cc_carry, raw_pattern_sel 0482 : 0000_0100_0000_0000_0001_0000 1429: 1430: mov raw_ChTML_adc, r9 ; use the ADC transf 0483 : 1100_0110_0000_0000_0000_1001 1431: shlt ZS_no_empty, func_code ; here used to selec 0484 : 1011_0001_1111_0011_1100_0000 1432: jmp cc_ncarry, raw_transf_ch 0485 : 0000_0100_0000_0000_0000_0000 1433: mov raw_ChTML_adcS, r9 ; use the ADC transf 0486 : 1100_0110_0000_0000_0000_1001 1434: jmp cc_uncond, raw_transf_ch ; 0487 : 0000_0100_0000_0000_0000_1111 1435: 1436: raw_pattern_sel: 1437: ; patterns 1438: shl OPTs, func_code, r9 0488 : 1011_0010_0000_0011_1100_1001 1439: mov 0x7, r6 ; 3 bit mask 0489 : 1100_0110_0000_0000_1110_0110 1440: and r6, r9, r6 ; the pattern is now 048A : 1010_0110_0110_0001_0010_0110 1441: mov raw_ChTML_p0, r9 ; pattern 0, default 048B : 1100_0110_0000_0000_0000_1001 1442: cmp r6, 2 048C : 1100_1000_0110_0000_0000_0010 1443: jmpr cc_neq, +3 048D : 0000_0100_1001_0010_0000_0001 1444: mov raw_ChTML_p2, r9 ; pattern 2 048E : 1100_0110_0000_0000_0000_1001 1445: jmp cc_uncond, raw_prepare_23 048F : 0000_0100_0000_0000_0000_1111 1446: cmp r6, 6 0490 : 1100_1000_0110_0000_0000_0110 1447: jmpr cc_neq, +3 0491 : 0000_0100_1001_0010_1000_0001 1448: mov raw_ChTML_p6, r9 ; pattern 6 0492 : 1100_0110_0000_0000_0000_1001 1449: jmp cc_uncond, raw_prepare_23 0493 : 0000_0100_0000_0000_0000_1111 1450: cmp r6, 3 0494 : 1100_1000_0110_0000_0000_0011 1451: jmp cc_neq, raw_check_psrg 0495 : 0000_0100_0000_0000_0000_0001 1452: mov raw_ChTML_p3, r9 ; pattern 3 0496 : 1100_0110_0000_0000_0000_1001 1453: 1454: raw_prepare_23: 1455: shl -1, h_0, r13 ; sector/plane/chamb 0497 : 1011_0011_1111_0111_1110_1101 1456: mov 0x7FF, r3 0498 : 1100_0110_1111_1111_1110_0011 1457: and r3, r13, r13 0499 : 1010_0110_0011_0001_1010_1101 1458: mov b100_1001, r3 049A : 1100_0110_0000_1001_0010_0011 1459: add r3, r13, r13 ; add 1 to sector, p 049B : 1000_0010_0011_0001_1010_1101 1460: mov ChipPos, r3 049C : 1100_0010_0000_0111_1100_0011 1461: and r3, mask_7F, r3 049D : 1010_0110_0011_0010_0010_0011 1462: shl 7, r13, r13 049E : 1011_0010_0111_0001_1010_1101 1463: or r13, r3, r13 ; sector(5)/plane(3) 049F : 1010_1010_1101_0000_0110_1101 1464: shl 2, r13, r13 04A0 : 1011_0010_0010_0001_1010_1101 1465: or r13, c5, r13 ; sector(5)/plane(3) 04A1 : 1010_1010_1101_0110_1010_1101 1466: 1467: jmp cc_neq, raw_transf_ch 04A2 : 0000_0100_0000_0000_0000_0001 1468: 1469: raw_check_psrg: 1470: cmp r6, 1 04A3 : 1100_1000_0110_0000_0000_0001 1471: jmp cc_neq, raw_transf_ch 04A4 : 0000_0100_0000_0000_0000_0001 1472: mov raw_ChTML_p1, r9 ; pattern 1, psrg10 04A5 : 1100_0110_0000_0000_0000_1001 1473: ; init the local counter 1474: mov b101001, r6 ; inc after read, 10 04A6 : 1100_0110_0000_0101_0010_0110 1475: spio r6, CTPCTRL 04A7 : 0010_0000_0110_0010_0000_0001 1476: shl 7, c1, r6 ; 1000 0000b 04A8 : 1011_0010_0111_0110_0010_0110 1477: add r6, ChipPOS, r6 ; 1rrr mmmmb rrr RO 04A9 : 1000_0010_0110_0111_1100_0110 1478: shl 2, r6, r6 ; 1r rrmm mm00b 04AA : 1011_0010_0010_0000_1100_0110 1479: or r6, c5, r6 ; 1r rrmm mmccb cc C 04AB : 1010_1010_0110_0110_1010_0110 1480: spio r6, CTPDINI 04AC : 0010_0000_0110_0010_0000_0000 1481: 1482: raw_transf_ch: 1483: 1484: ;############################################## 1485: ;# NI&SCSN transfer 1st channel 1486: ;############################################## 1487: 1488: mov LSBdata, r7 ; pass the two LSBs 04AD : 1100_0110_0000_0000_0110_0111 1489: mov 0, r3 ; used in testpatter 04AE : 1100_0110_0000_0000_0000_0011 1490: mov NODP, r6 ; the NI output port 04AF : 1100_0110_0000_0000_0000_0110 1491: shl -1, adc_ch_msk, adc_ch_msk ; check the flag 04B0 : 1011_0011_1111_0010_1101_0110 1492: jmpr cc_carry, +2 04B1 : 0000_0100_1001_0110_0111_0000 1493: mov GBUSR0, r6 ; dummy output port, 04B2 : 1100_0110_0110_0000_0000_0110 1494: 1495: #ifdef DBANKscsn 1496: mov EBR0, r0 ; address in LIO of 1497: or r0, rio, rio ; to low word of rio 1498: #else 1499: mov EBR0, rio 04B3 : 1100_0111_0000_0000_0000_1110 1500: #endif 1501: cmp r9, raw_ChTML_adcS ; check if ADC stati 04B4 : 1100_1000_1001_0000_0000_0000 1502: jmpr cc_neq, +3 04B5 : 0000_0100_1001_0111_0000_0001 1503: mov 0, r11 04B6 : 1100_0110_0000_0000_0000_1011 1504: mov 0, r13 04B7 : 1100_0110_0000_0000_0000_1101 1505: mov nsamples,r1 ; number of samples 04B8 : 1100_0010_0000_0111_1010_0001 1506: mvpcr +2, rstack 04B9 : 1100_0110_1001_0111_0110_1000 1507: jmp cc_uncond, r9; 04BA : 0000_1000_1001_0000_0000_1111 1508: 1509: ;############################################## 1510: ;# NI&SCSN transfer 2nd channel 1511: ;############################################## 1512: 1513: mov NODP, r6 ; the NI output port 04BB : 1100_0110_0000_0000_0000_0110 1514: shl -1, adc_ch_msk, adc_ch_msk ; check the flag 04BC : 1011_0011_1111_0010_1101_0110 1515: jmpr cc_carry, +2 04BD : 0000_0100_1001_0111_1111_0000 1516: mov GBUSR0, r6 ; dummy output port, 04BE : 1100_0110_0110_0000_0000_0110 1517: 1518: 1519: #ifdef DBANKscsn 1520: and r15, rio, rio 1521: mov EBR1, r0 ; address in LIO of 1522: or r0, rio, rio ; to low word of rio 1523: #else 1524: mov EBR1, rio 04BF : 1100_0111_0000_1000_0000_1110 1525: #endif 1526: cmp r9, raw_ChTML_adcS ; check if ADC stati 04C0 : 1100_1000_1001_0000_0000_0000 1527: jmpr cc_neq, +3 04C1 : 0000_0100_1001_1000_1000_0001 1528: mov 0, r11 04C2 : 1100_0110_0000_0000_0000_1011 1529: mov 0, r13 04C3 : 1100_0110_0000_0000_0000_1101 1530: mov nsamples,r1 ; number of samples 04C4 : 1100_0010_0000_0111_1010_0001 1531: mvpcr +2, rstack 04C5 : 1100_0110_1001_1000_1110_1000 1532: jmp cc_uncond, r9; 04C6 : 0000_1000_1001_0000_0000_1111 1533: 1534: 1535: ;############################################## 1536: ;# NI&SCSN transfer 3rd channel 1537: ;############################################## 1538: 1539: mov NODP, r6 ; the NI output port 04C7 : 1100_0110_0000_0000_0000_0110 1540: shl -1, adc_ch_msk, adc_ch_msk ; check the flag 04C8 : 1011_0011_1111_0010_1101_0110 1541: jmpr cc_carry, +2 04C9 : 0000_0100_1001_1001_0111_0000 1542: mov GBUSR0, r6 ; dummy output port, 04CA : 1100_0110_0110_0000_0000_0110 1543: 1544: #ifdef DBANKscsn 1545: and r15, rio, rio 1546: mov EBR2, r0 ; address in LIO of 1547: or r0, rio, rio ; to low word of rio 1548: #else 1549: mov EBR2, rio 04CB : 1100_0111_0001_0000_0000_1110 1550: #endif 1551: cmp r9, raw_ChTML_adcS ; check if ADC stati 04CC : 1100_1000_1001_0000_0000_0000 1552: jmpr cc_neq, +3 04CD : 0000_0100_1001_1010_0000_0001 1553: mov 0, r11 04CE : 1100_0110_0000_0000_0000_1011 1554: mov 0, r13 04CF : 1100_0110_0000_0000_0000_1101 1555: mov nsamples,r1 ; number of samples 04D0 : 1100_0010_0000_0111_1010_0001 1556: mvpcr +2, rstack 04D1 : 1100_0110_1001_1010_0110_1000 1557: jmp cc_uncond, r9; 04D2 : 0000_1000_1001_0000_0000_1111 1558: 1559: 1560: ;############################################## 1561: ;# NI&SCSN transfer 4th channel 1562: ;############################################## 1563: 1564: mov NODP, r6 ; the NI output port 04D3 : 1100_0110_0000_0000_0000_0110 1565: shl -1, adc_ch_msk, adc_ch_msk ; check the flag 04D4 : 1011_0011_1111_0010_1101_0110 1566: jmpr cc_carry, +2 04D5 : 0000_0100_1001_1010_1111_0000 1567: mov GBUSR0, r6 ; dummy output port, 04D6 : 1100_0110_0110_0000_0000_0110 1568: 1569: #ifdef DBANKscsn 1570: and r15, rio, rio 1571: mov EBR3, r0 ; address in LIO of 1572: or r0, rio, rio ; to low word of rio 1573: #else 1574: mov EBR3, rio 04D7 : 1100_0111_0001_1000_0000_1110 1575: #endif 1576: cmp r9, raw_ChTML_adcS ; check if ADC stati 04D8 : 1100_1000_1001_0000_0000_0000 1577: jmpr cc_neq, +3 04D9 : 0000_0100_1001_1011_1000_0001 1578: mov 0, r11 04DA : 1100_0110_0000_0000_0000_1011 1579: mov 0, r13 04DB : 1100_0110_0000_0000_0000_1101 1580: mov nsamples,r1 ; number of samples 04DC : 1100_0010_0000_0111_1010_0001 1581: mvpcr +2, rstack 04DD : 1100_0110_1001_1011_1110_1000 1582: jmp cc_uncond, r9; 04DE : 0000_1000_1001_0000_0000_1111 1583: 1584: 1585: ;############################################## 1586: ;# NI&SCSN transfer 5th channel 1587: ;############################################## 1588: 1589: mov NODP, r6 ; the NI output port 04DF : 1100_0110_0000_0000_0000_0110 1590: shl -1, adc_ch_msk, adc_ch_msk ; check the flag 04E0 : 1011_0011_1111_0010_1101_0110 1591: jmpr cc_carry, +2 04E1 : 0000_0100_1001_1100_0111_0000 1592: mov GBUSR0, r6 ; dummy output port, 04E2 : 1100_0110_0110_0000_0000_0110 1593: 1594: #ifdef DBANKscsn 1595: and r15, rio, rio 1596: mov EBR4, r0 ; address in LIO of 1597: or r0, rio, rio ; to low word of rio 1598: #else 1599: mov EBR4, rio 04E3 : 1100_0111_0010_0000_0000_1110 1600: #endif 1601: cmp r9, raw_ChTML_adcS ; check if ADC stati 04E4 : 1100_1000_1001_0000_0000_0000 1602: jmpr cc_neq, +3 04E5 : 0000_0100_1001_1101_0000_0001 1603: mov 0, r11 04E6 : 1100_0110_0000_0000_0000_1011 1604: mov 0, r13 04E7 : 1100_0110_0000_0000_0000_1101 1605: mov nsamples,r1 ; number of samples 04E8 : 1100_0010_0000_0111_1010_0001 1606: mvpcr +2, rstack 04E9 : 1100_0110_1001_1101_0110_1000 1607: jmp cc_uncond, r9; 04EA : 0000_1000_1001_0000_0000_1111 1608: 1609: 1610: ;############################################## 1611: ;# NI&SCSN transfer 6th channel (CPU3 only) 1612: ;############################################## 1613: 1614: #ifdef cpu3 1615: mov NODP, r6 ; the NI output port 1616: shl -1, adc_ch_msk, adc_ch_msk ; check the flag 1617: jmpr cc_carry, +2 1618: mov GBUSR0, r6 ; dummy output port, 1619: 1620: #ifdef DBANKscsn 1621: and r15, rio, rio 1622: mov EBR5, r0 ; address in LIO of 1623: or r0, rio, rio ; to low word of rio 1624: #else 1625: mov EBR5, rio 1626: #endif 1627: cmp r9, raw_ChTML_adcS ; check if ADC stati 1628: jmpr cc_neq, +3 1629: mov 0, r11 1630: mov 0, r13 1631: mov nsamples,r1 ; number of samples 1632: mvpcr +2, rstack 1633: jmp cc_uncond, r9; 1634: #else 1635: nop 04EB : 0000_0000_0000_0000_0000_0000 1636: nop 04EC : 0000_0000_0000_0000_0000_0000 1637: nop 04ED : 0000_0000_0000_0000_0000_0000 1638: nop 04EE : 0000_0000_0000_0000_0000_0000 1639: nop 04EF : 0000_0000_0000_0000_0000_0000 1640: nop 04F0 : 0000_0000_0000_0000_0000_0000 1641: nop 04F1 : 0000_0000_0000_0000_0000_0000 1642: nop 04F2 : 0000_0000_0000_0000_0000_0000 1643: nop 04F3 : 0000_0000_0000_0000_0000_0000 1644: nop 04F4 : 0000_0000_0000_0000_0000_0000 1645: nop 04F5 : 0000_0000_0000_0000_0000_0000 1646: nop 04F6 : 0000_0000_0000_0000_0000_0000 1647: #ifdef DBANKscsn 1648: nop 1649: nop 1650: #endif; 1651: #endif; 1652: 1653: ; save the fit register pairs in DMEM 1654: 1655: #ifdef FIT2DM 1656: mov r15, r2 1657: mov 0x400, r15; DMEM pointer 1658: shl 6, c5, r1 ; 16 * 4 * CPUid 1659: add r1, r15, r15 1660: mov f0, r1 1661: sra+ r1 1662: mov f1, r1 1663: sra+ r1 1664: mov f2, r1 1665: sra+ r1 1666: mov f3, r1 1667: sra+ r1 1668: mov f4, r1 1669: sra+ r1 1670: mov f5, r1 1671: sra+ r1 1672: mov f6, r1 1673: sra+ r1 1674: mov f7, r1 1675: sra+ r1 1676: mov f8, r1 1677: sra+ r1 1678: mov f9, r1 1679: sra+ r1 1680: mov f10, r1 1681: sra+ r1 1682: mov f11, r1 1683: sra+ r1 1684: mov f12, r1 1685: sra+ r1 1686: mov f13, r1 1687: sra+ r1 1688: mov f14, r1 1689: sra+ r1 1690: mov f15, r1 1691: sra+ r1 1692: mov r2, r15 1693: 1694: #endif 1695: 1696: 1697: ;############################################## 1698: ;# Slow down NI transmission if NI_tmsn_delay != 0 1699: ;############################################## 1700: 1701: raw_complete_ni_tmsn: 1702: #ifdef cpu3 1703: mov NI_tmsn_delay, r1 ; mov doesn't set th 1704: andt r1, r1 1705: jmp cc_zero, raw_end_ni_tmsn 1706: cli 1707: lgio 0, IRQHW3 1708: jmpr cc_busy, 0 1709: lpio 0x300, r11 1710: mov 0x415, r0 ; the new IRQ mask, 1711: sgio r0, IRQHW3 ; modify the IVT 1712: jmpr cc_busy, 0 1713: sgio r0, IRQHL3 1714: jmpr cc_busy, 0 1715: jmp cc_uncond, raw_coff 1716: #else 1717: nop 04F7 : 0000_0000_0000_0000_0000_0000 1718: nop 04F8 : 0000_0000_0000_0000_0000_0000 1719: nop 04F9 : 0000_0000_0000_0000_0000_0000 1720: nop 04FA : 0000_0000_0000_0000_0000_0000 1721: nop 04FB : 0000_0000_0000_0000_0000_0000 1722: nop 04FC : 0000_0000_0000_0000_0000_0000 1723: nop 04FD : 0000_0000_0000_0000_0000_0000 1724: nop 04FE : 0000_0000_0000_0000_0000_0000 1725: nop 04FF : 0000_0000_0000_0000_0000_0000 1726: nop 0500 : 0000_0000_0000_0000_0000_0000 1727: nop 0501 : 0000_0000_0000_0000_0000_0000 1728: nop 0502 : 0000_0000_0000_0000_0000_0000 1729: nop 0503 : 0000_0000_0000_0000_0000_0000 1730: #endif 1731: 1732: ;############################################## 1733: ;# CPU0, CPU1: start CPU2 and CPU3 for delayed transfer 1734: ;############################################## 1735: 1736: raw_end_ni_tmsn: 1737: 1738: ;############################################## 1739: ;# CPU3: Increment Event Counter 1740: ;############################################## 1741: 1742: #ifdef cpu3 1743: 1744: mov EventCounter, r0 1745: add r0, c1, r0 1746: jmpr cc_busy, 0 1747: sgio r0 EvtCtrGIOAdr 1748: lpio GBUSR1, r0 ; restore the EBSIM 1749: jmpr cc_busy, 0 ; added by Tom 2008-10-09 1750: iext EBSIM ; which was switched off (1 1751: sgio r0, EBSIM ; in order to read the even 1752: #else 1753: nop 0504 : 0000_0000_0000_0000_0000_0000 1754: nop 0505 : 0000_0000_0000_0000_0000_0000 1755: nop 0506 : 0000_0000_0000_0000_0000_0000 1756: nop 0507 : 0000_0000_0000_0000_0000_0000 1757: nop 0508 : 0000_0000_0000_0000_0000_0000 1758: nop 0509 : 0000_0000_0000_0000_0000_0000 1759: nop 050A : 0000_0000_0000_0000_0000_0000 1760: #endif 1761: 1762: ;############################################## 1763: ;# NI&SCSN transfer end marker 1764: ;############################################## 1765: 1766: 1767: swp endsig_rr_tr, r0 ; the upper 16 bits 050B : 0111_1010_0000_0011_1110_0000 1768: spio r0 NODP 050C : 0010_0000_0000_0000_0000_0000 1769: #ifdef DBANKscsn 1770: swp rio, rio 1771: jmpr cc_busy, 0 1772: sgio+ r0 1773: swp rio, rio 1774: #else 1775: sra+ r0 050D : 0011_1000_0000_0000_0000_0000 1776: #endif 1777: 1778: 1779: ;############################################## 1780: ;# switch off own clock after transfer 1781: ;############################################## 1782: 1783: raw_coff: 1784: mov 0, r0 050E : 1100_0110_0000_0000_0000_0000 1785: 1786: jmpr cc_busy, 0 050F : 0000_0100_1010_0001_1111_0111 1787: sgio r0 clk_onoff 0510 : 0010_1000_0000_1010_0010_0101 1788: jmpr cc_busy, 0 0511 : 0000_0100_1010_0010_0011_0111 1789: 1790: jmp cc_uncond, clr_endloop 0512 : 0000_0100_0000_0000_0000_1111 1791: nop 0513 : 0000_0000_0000_0000_0000_0000 1792: nop 0514 : 0000_0000_0000_0000_0000_0000 1793: nop 0515 : 0000_0000_0000_0000_0000_0000 1794: nop 0516 : 0000_0000_0000_0000_0000_0000 1795: nop 0517 : 0000_0000_0000_0000_0000_0000 1796: nop 0518 : 0000_0000_0000_0000_0000_0000 1797: nop 0519 : 0000_0000_0000_0000_0000_0000 1798: nop 051A : 0000_0000_0000_0000_0000_0000 1799: nop 051B : 0000_0000_0000_0000_0000_0000 1800: nop 051C : 0000_0000_0000_0000_0000_0000 1801: nop 051D : 0000_0000_0000_0000_0000_0000 1802: nop 051E : 0000_0000_0000_0000_0000_0000 1803: nop 051F : 0000_0000_0000_0000_0000_0000 1804: nop 0520 : 0000_0000_0000_0000_0000_0000 1805: nop 0521 : 0000_0000_0000_0000_0000_0000 1806: nop 0522 : 0000_0000_0000_0000_0000_0000 1807: nop 0523 : 0000_0000_0000_0000_0000_0000 1808: nop 0524 : 0000_0000_0000_0000_0000_0000 1809: nop 0525 : 0000_0000_0000_0000_0000_0000 1810: #ifdef cpu3 1811: jmp cc_uncond, clr_endloop 1812: #else 1813: jmp cc_uncond, raw_coff 0526 : 0000_0100_0000_0000_0000_1111 1814: #endif 1815: nop 0527 : 0000_0000_0000_0000_0000_0000 1816: 1817: 1818: ;########################################################### 1819: ;# 1820: ;# NI transmission of one channel 1821: ;# 1822: ;########################################################### 1823: ;# 1824: ;# Interface: 1825: ;# 1826: ;# Input: r14 start address of event buffer in LIO 1827: ;# r1 number of time bins to read (>0, mul 1828: ;# r7 OR mask for the 32 bit word 1829: ;# r2 Readout Flags 1830: ;# r6 address in LIO of the output port, e 1831: ;# r8 rstack, return address 1832: ;# r9 the begin address of the procedure, 1833: ;# 1834: ;# Output: sends data to the NI output port 1835: ;# Modifies: r3, r4, r5, r14, r1, r13 1836: ;# 1837: ;########################################################### 1838: 1839: ;########################### 1840: ;# BEGIN data transfer loop 1841: 1842: raw_ChTML_p0: ; (0x0800+i) << 16 | 0rr 1843: mov 0xFF, r3 0528 : 1100_0110_0001_1111_1110_0011 1844: and r3, ChipPOS, r3 ; for mode 0 0529 : 1010_0110_0011_0111_1100_0011 1845: shl 8, rio, r5 052A : 1011_0010_1000_0001_1100_0101 1846: or r3, r5, r5 052B : 1010_1010_0011_0000_1010_0101 1847: shl 8, r5, r5 052C : 1011_0010_1000_0000_1010_0101 1848: or r5, c5, r5 052D : 1010_1010_0101_0110_1010_0101 1849: add r5, c1, r5 052E : 1000_0010_0101_0110_0010_0101 1850: add rio, c1, rio 052F : 1000_0010_1110_0110_0010_1110 1851: jmp cc_uncond, raw_wadc 0530 : 0000_0100_0000_0000_0000_1111 1852: 1853: raw_ChTML_p1: ; ADCs replaced by 10 bi 1854: lpio CTPDOUT, r3 0531 : 1110_0110_0100_0000_0100_0011 1855: mov 0x3FF, r5 ; mask for 10 bit psrg 0532 : 1100_0110_0111_1111_1110_0101 1856: and r3, r5, r3 0533 : 1010_0110_0011_0000_1010_0011 1857: lpio CTPDOUT, r4 0534 : 1110_0110_0100_0000_0100_0100 1858: and r4, r5, r4 0535 : 1010_0110_0100_0000_1010_0100 1859: shl 10, r4, r4 0536 : 1011_0010_1010_0000_1000_0100 1860: or r4, r3, r3 0537 : 1010_1010_0100_0000_0110_0011 1861: lpio CTPDOUT, r5 0538 : 1110_0110_0100_0000_0100_0101 1862: shl 10, r5, r5 0539 : 1011_0010_1010_0000_1010_0101 1863: jmp cc_uncond, raw_ADCcor 053A : 0000_0100_0000_0000_0000_1111 1864: 1865: raw_ChTML_p2: 1866: shl 10, EventCounter, r5 053B : 1011_0010_1010_0111_1000_0101 1867: shl 10, r5, r5 053C : 1011_0010_1010_0000_1010_0101 1868: or r5, r13, r5 ; evncnt(6)/sector(5)/pl 053D : 1010_1010_0101_0001_1010_0101 1869: shl 6, r5, r5 053E : 1011_0010_0110_0000_1010_0101 1870: add r3, c1, r3 ; counter++, for 1 CPU 6 053F : 1000_0010_0011_0110_0010_0011 1871: or r5, r3, r5 ; ... counter(6) 0540 : 1010_1010_0101_0000_0110_0101 1872: jmp cc_uncond, raw_wadc 0541 : 0000_0100_0000_0000_0000_1111 1873: 1874: raw_ChTML_p6: 1875: shl 10, EventCounter, r5 0542 : 1011_0010_1010_0111_1000_0101 1876: shl 10, r5, r5 0543 : 1011_0010_1010_0000_1010_0101 1877: or r5, r13, r5 ; evncnt(6)/sector(5)/pl 0544 : 1010_1010_0101_0001_1010_0101 1878: shl 6, r5, r5 0545 : 1011_0010_0110_0000_1010_0101 1879: add r3, c1, r3 ; counter++, for 1 CPU 6 0546 : 1000_0010_0011_0110_0010_0011 1880: or r5, r3, r5 ; ... counter(6) 0547 : 1010_1010_0101_0000_0110_0101 1881: shl 2, r5, r5 ; add the two LSB as in 0548 : 1011_0010_0010_0000_1010_0101 1882: or r5, r7, r5 0549 : 1010_1010_0101_0000_1110_0101 1883: jmp cc_uncond, raw_wadc 054A : 0000_0100_0000_0000_0000_1111 1884: 1885: raw_ChTML_p3: 1886: shl 10, EventCounter, r5 054B : 1011_0010_1010_0111_1000_0101 1887: shl 10, r5, r5 054C : 1011_0010_1010_0000_1010_0101 1888: or r5, r13, r5 ; evncnt(12)/sector(5)/p 054D : 1010_1010_0101_0001_1010_0101 1889: jmp cc_uncond, raw_wadc 054E : 0000_0100_0000_0000_0000_1111 1890: 1891: raw_ChTML_adcS: 1892: lpio+ r3 ; initial read has t 054F : 1110_1110_0000_0000_0000_0011 1893: lpio+ r3 ; memory delay (sync 0550 : 1110_1110_0000_0000_0000_0011 1894: lpio+ r4 0551 : 1110_1110_0000_0000_0000_0100 1895: lpio rio, r5 0552 : 1110_0010_0000_0001_1100_0101 1896: mul32 r3, r3, r0 ; calculate ADC**2 0553 : 1001_0000_0011_0000_0110_1000 1897: add r11, r3, r11 ; accumulate sum(ADC 0554 : 1000_0010_1011_0000_0110_1011 1898: add r13, r0, r13 ; accumulate sum(ADC 0555 : 1000_0010_1101_0000_0000_1101 1899: mul32 r4, r4, r0 ; calculate ADC**2 0556 : 1001_0000_0100_0000_1000_1000 1900: add r11, r4, r11 ; accumulate sum(ADC 0557 : 1000_0010_1011_0000_1000_1011 1901: add r13, r0, r13 ; accumulate sum(ADC 0558 : 1000_0010_1101_0000_0000_1101 1902: mul32 r5, r5, r0 ; calculate ADC**2 0559 : 1001_0000_0101_0000_1010_1000 1903: add r11, r5, r11 ; accumulate sum(ADC 055A : 1000_0010_1011_0000_1010_1011 1904: add r13, r0, r13 ; accumulate sum(ADC 055B : 1000_0010_1101_0000_0000_1101 1905: jmp cc_uncond, raw_ChTML_shift 055C : 0000_0100_0000_0000_0000_1111 1906: 1907: raw_ChTML_adc: 1908: lpio+ r3 ; initial read has t 055D : 1110_1110_0000_0000_0000_0011 1909: lpio+ r3 ; memory delay (sync 055E : 1110_1110_0000_0000_0000_0011 1910: lpio+ r4 055F : 1110_1110_0000_0000_0000_0100 1911: lpio rio, r5 0560 : 1110_0010_0000_0001_1100_0101 1912: 1913: raw_ChTML_shift: 1914: shl 10, r5, r5 ; combine three 10 b 0561 : 1011_0010_1010_0000_1010_0101 1915: or r5, r4, r5 ; to one (32=10+10+1 0562 : 1010_1010_0101_0000_1000_0101 1916: jmp cc_zero, raw_ADCzero ; correct data if th 0563 : 0000_0100_0000_0000_0001_0001 1917: 1918: raw_ADCcor: 1919: shl 10, r5, r5 0564 : 1011_0010_1010_0000_1010_0101 1920: or r5, r3, r5 0565 : 1010_1010_0101_0000_0110_0101 1921: shl 2, r5, r5 0566 : 1011_0010_0010_0000_1010_0101 1922: or r5, r7, r5 ; set the two LSBs 0567 : 1010_1010_0101_0000_1110_0101 1923: 1924: raw_wadc: 1925: spio r5, r6 ; write to NI or dum 0568 : 0100_0100_0101_0000_1100_0000 1926: 1927: ;raw_scsn_readout: 1928: #ifdef DBANKscsn 1929: swp rio, rio ; switch to SCSN sto 1930: jmpr cc_busy, 0 1931: sgio+ r5 ; write to DBANK for 1932: swp rio, rio ; switch back to eve 1933: #else 1934: sra+ r5 0569 : 0011_1000_0101_0000_0000_0000 1935: #endif 1936: 1937: sub r1, c3, r1 ; decrease number of 056A : 1000_1010_0001_0110_0110_0001 1938: jmp cc_gtu, r9 ; loop, the start ad 056B : 0000_1000_1001_0000_0000_1000 1939: 1940: xor r7, c1, r7 ; turn the LSB 056C : 1010_0010_0111_0110_0010_0111 1941: cmp r9, raw_ChTML_adcS ; check if ADC stati 056D : 1100_1000_1001_0000_0000_0000 1942: jmp cc_neq, rstack ; return from subrou 056E : 0000_1000_1000_0000_0000_0001 1943: swp r15, r15 ; swap the two DMEM 056F : 0111_1010_0000_0001_1110_1111 1944: nop 0570 : 0000_0000_0000_0000_0000_0000 1945: lra4 r4 ; read the old sum(A 0571 : 1101_0010_0000_0000_0000_0100 1946: lra4 r4 0572 : 1101_0010_0000_0000_0000_0100 1947: add r11, r4, r11 ; add the current su 0573 : 1000_0010_1011_0000_1000_1011 1948: sra+ r11 ; and write back 0574 : 0011_1000_1011_0000_0000_0000 1949: nop ; the reg r15 should 0575 : 0000_0000_0000_0000_0000_0000 1950: lra4 r4 ; read the old sum(A 0576 : 1101_0010_0000_0000_0000_0100 1951: lra4 r4 0577 : 1101_0010_0000_0000_0000_0100 1952: add r13, r4, r13 ; add the current su 0578 : 1000_0010_1101_0000_1000_1101 1953: sra+ r13 ; and store back 0579 : 0011_1000_1101_0000_0000_0000 1954: nop 057A : 0000_0000_0000_0000_0000_0000 1955: lra4 r4 ; load the upper 32 057B : 1101_0010_0000_0000_0000_0100 1956: lra4 r4 057C : 1101_0010_0000_0000_0000_0100 1957: adc r4, c0, r4 ; add the carry, sra 057D : 1000_0110_0100_0110_0000_0100 1958: sra+ r4 ; and write back 057E : 0011_1000_0100_0000_0000_0000 1959: swp r15, r15 ; swap the two DMEM 057F : 0111_1010_0000_0001_1110_1111 1960: jmp cc_uncond, rstack ; return from subrou 0580 : 0000_1000_1000_0000_0000_1111 1961: 1962: raw_ADCzero: 1963: mov 0x400, r4 ; set the LSB of the 0581 : 1100_0110_1000_0000_0000_0100 1964: or r5, r4, r5 ; to prevent sending 0582 : 1010_1010_0101_0000_1000_0101 1965: jmp cc_uncond, raw_ADCcor 0583 : 0000_0100_0000_0000_0000_1111 1966: ;########################### 1967: ;# END data transfer loop 1968: ;########################### 1969: 1970: nop 0584 : 0000_0000_0000_0000_0000_0000 1971: 1972: 1973: ;############################################## 1974: ;# This is our HCM header[0], stored always in DBANK 1975: ;############################################## 1976: 1977: raw_hc0: 1978: #ifdef cpu0 1979: iext 0xF0F0 1980: mov 0xF0F0, rio ; the HC headers are 1981: shl 2, h_0, r0 ; the header itself 1982: or r0, c1, r4 ; last two bits 01 1983: 1984: 1985: #ifdef ConfigEvent 1986: mov EventCounter, r0 1987: cmp r0, ConfigEvent 1988: jmp cc_neq, raw_hc0_cont 1989: iext 0x1FFFF 1990: mov 0x1FFFF, r0 ; 17 bits mask 1991: and r0, r4, r4 ; mask the upper bit 1992: mov 0xC7, r0 ; TP=1, pattern=7 1993: shl 12, r0, r0 1994: shl 12, r0, r0 1995: or r0, r4, r4 ; new header, TP=1, 1996: #endif 1997: raw_hc0_cont: 1998: sgio+ r4 1999: ; spio r4 NODP ; NI transfer heade 2000: ; r4 contains the h[0], postpone sending 2001: 2002: ; prepare h[1] 2003: shl 8, nsamples, r0 ; timebins 2004: shl 8, r0, r0 2005: 2006: or r0, g5, r0 ; timebins & BC(16 b 2007: shl 4, r0, r0 2008: 2009: or r0, g7, r0 ; timebins & BC & pr 2010: shl 4, r0, r0 2011: 2012: or r0, g6, r0 ; timebins & BC & pr 2013: shl 2, r0, r5 2014: or r5, c1, r5 ; timebins & BC & pr 2015: sgio+ r5 2016: 2017: ; SVN revisions header h[3] 2018: mov FIT_SVN_REV, r0 2019: shl 13, r0, r0 2020: mov ASM_SVN_REV, r1 2021: or r0, r1, r0 2022: shl 6, r0, r0 2023: mov 0x35, r1 2024: or r0, r1, r6 2025: sgio+ r6 ; h[3] 2026: 2027: ; h[0] is in r4 2028: ; h[1] is in r5 2029: ; h[3] is in r6 2030: 2031: ; now wait until CPU0 of the first MCM with ADC data has 2032: #ifdef delay_hcm 2033: mov delay_hcm, r0 2034: sub r0, c1, r0 2035: jmpr cc_nzero, -1 2036: #endif 2037: 2038: 2039: mov 0x7, r1 ; prepare a mask 2040: shl -12, h_0, r0 ; the number of add. 2041: and r0, r1, r1 2042: 2043: spio r4 NODP ; NI transfer header 2044: jmp cc_zero, raw_no_add_header 2045: spio r5 NODP ; NI transfer header 2046: cmp r1, 2 2047: jmp cc_ltu, raw_no_add_header 2048: spio r6 NODP ; NI transfer header 2049: 2050: raw_no_add_header: 2051: nop 2052: #endif 2053: 2054: #ifdef cpu1 2055: ; prepare the BC counter 2056: lpio CTPDOUT, r0 2057: iext 0xFFFF 2058: mov 0xFFFF, r1 2059: and r0, r1, g5 2060: #endif 2061: 2062: #ifdef cpu2 2063: ; prepare the pretrigger phase 2064: lpio CTPDOUT, r0 0585 : 1110_0110_0100_0000_0100_0000 2065: mov 0xF, r1 0586 : 1100_0110_0000_0001_1110_0001 2066: and r0, r1, g6 0587 : 1010_0110_0000_0000_0011_0110 2067: #endif 2068: 2069: #ifdef cpu3 2070: ; prepare the pretrigger counter 2071: lpio CTPDOUT, r0 2072: mov 0xF, r1 2073: and r0, r1, g7 2074: #endif 2075: 2076: #ifdef DBANKscsn 2077: swp rio, rio ; swap DBANK address 2078: #endif 2079: andt r2, c3 0588 : 1010_0100_0010_0110_0110_0000 2080: jmp cc_zero, raw_end_ni_tmsn ; do not check for t 0589 : 0000_0100_0000_0000_0001_0001 2081: 2082: 2083: ;########################################################### 2084: ;# 2085: ;# 0x600 Interrupt NI FIFO empty, irq10 2086: ;# 2087: ;########################################################### 2088: 2089: ORG 0x600 2090: 2091: #ifdef cpu3 2092: nififoe: 2093: 2094: sgio r11, IRQHL3 2095: jmpr cc_busy, 0 2096: sgio r11, IRQHW3 2097: jmpr cc_busy, 0 2098: 2099: ; program the delay 2100: mov NI_tmsn_delay, r1 2101: spio r1, 0x200 2102: mov b1010_0101_1111, r1 ; counter, down, irq 2103: spio r1, 0x201 2104: ; enable IRQ local timer 2105: mov b0101_0101, r1 2106: sgio r1, IRQHL3 2107: jmpr cc_busy, 0 2108: sgio r1, IRQHW3 2109: jmpr cc_busy, 0 2110: jmp cc_uncond, raw_coff 2111: #else 2112: nop 0600 : 0000_0000_0000_0000_0000_0000 2113: #endif 2114: 2115: ORG 0x640 2116: ;raw_send_cnf: 2117: ; NOT USED NOW! 2118: #ifdef TimerCPUsendc 2119: mov 0x640, r0 2120: spio r0, CTPCTRL 2121: mov 0, r0 2122: spio r0, CTPDINI 2123: #endif 2124: mov 0x34, r0 0640 : 1100_0110_0000_0110_1000_0000 2125: mul32 r0, c5, r1 0641 : 1001_0000_0000_0110_1010_1001 2126: iext 0xF000 0642 : 0101_0000_0000_0000_0000_1111 2127: mov 0xF000, r13 0643 : 1100_0110_0000_0000_0000_1101 2128: add r13, r1, r14 ; start address 0644 : 1000_0010_1101_0000_0010_1110 2129: #ifdef cpu3 2130: swp g4, r2 ; the number of conf.words is st 2131: mov 0xFF, r3 2132: and r2, r3 2133: add r13, r3, r15 ; end address+1 2134: iext 0xf0d0 2135: mov 0xf0d0, r15 2136: #else 2137: add r14, r0, r15 ; end address+1 0645 : 1000_0010_1110_0000_0000_1111 2138: nop 0646 : 0000_0000_0000_0000_0000_0000 2139: nop 0647 : 0000_0000_0000_0000_0000_0000 2140: nop 0648 : 0000_0000_0000_0000_0000_0000 2141: #endif 2142: raw_send_cnf_a: 2143: lgio+ 0 0649 : 1111_0100_0000_0000_0000_0000 2144: jmpr cc_busy, 0 064A : 0000_0100_1100_1001_0101_0111 2145: lpio GBUSR0, r0 064B : 1110_0110_0110_0000_0000_0000 2146: spio r0, NODP 064C : 0010_0000_0000_0000_0000_0000 2147: cmp r14, r15 064D : 1000_1000_1110_0001_1110_0000 2148: jmp cc_ltu, raw_send_cnf_a 064E : 0000_0100_0000_0000_0001_0000 2149: 2150: #ifdef cpu3 2151: iext 0x00FF7FFF 2152: mov 0x00FF7FFF, r0 2153: swp r0, r0 2154: spio r0, NODP ; end marker for con 2155: #endif 2156: 2157: #ifdef TimerCPUsendc 2158: lpio CTPDOUT, r0 ; the number of CPU 2159: sra r0, TimerCPUsendc ; store in DMEM for debugging 2160: #else 2161: 2162: jmp cc_uncond, raw_complete_ni_tmsn 064F : 0000_0100_0000_0000_0000_1111 2163: 2164: 2165: ;########################################################### 2166: ;# 2167: ;# 0x6E0 Interrupt Local Counter/Timer 2168: ;# 2169: ;########################################################### 2170: 2171: ORG 0x6E0 2172: 2173: localtm: 2174: 2175: ; restore the interrupt mask 2176: sgio r11, IRQHL3 06E0 : 0010_1000_1011_1011_0110_1111 2177: jmpr cc_busy, 0 06E1 : 0000_0100_1101_1100_0011_0111 2178: sgio r11, IRQHW3 06E2 : 0010_1000_1011_1011_0110_1110 2179: jmpr cc_busy, 0 06E3 : 0000_0100_1101_1100_0111_0111 2180: 2181: ; send end signature 2182: jmp cc_uncond, raw_end_ni_tmsn 06E4 : 0000_0100_0000_0000_0000_1111 2183: nop 06E5 : 0000_0000_0000_0000_0000_0000 2184: 2185: ORG 0x700 2186: ; Style recommendations 2187: ; 2188: ; 1) use include for the different parts of the CPU program 2189: ; 2190: ; 2) use prefix in the labels, e.g. 2191: ; 2192: ; -- start of the acq subroutine 2193: ; acq: ... 2194: ; ... 2195: ; acq_store: 2196: ; ... 2197: ; acq_delay: 2198: ; ... 2199: ; -- end of the acq subroutine 2200: 2201: ; ADDITIONAL PROGRAMS 2202: ; 2203: ; GENERAL RULES 2204: ; 2205: ; 1) The programs do not use any programmable constants 2206: ; 2) CPU3 is never used 2207: ; 3) The programs use for data exchange a small region in th 2208: ; or DMEM or IMEM3, accessible through GIO. The start add 2209: ; must be defined in the main program as follows: 2210: ; 2211: ; srv_command - command from the SCSN master, code of th 2212: ; srv_indata - input data, stored by the SCSN master 2213: ; srv_outdata - output data, stored by the TRAP CPU 2214: ; 2215: ; 4) The programs may modify all registers (privat and globa 2216: ; 2217: ; 5) The programs end with command low power to the global s 2218: ; This can be changed later - may be is reasonable to hav 2219: ; IRT (interrupt return) or just jump to some address. 2220: ; 2221: ; 6) By default the configuration of the main program enable 2222: ; but sets the start address to a small assembler code to 2223: ; 2224: ; 7) When the SCSN master wants to start some service progra 2225: ; TRAP to the low power state, then modify the IVT (inter 2226: ; - store the correct start address of the service progra 2227: ; stores its request at srv_command and activates IRQ TST 2228: ; the state of the TRAP and sends it to low power state i 2229: ; After finishing the service operation (which can consis 2230: ; the SCSN master restores the IVT to the original. 2231: 2232: 2233: ; J2C 2234: #ifdef cpu0 2235: #inc "j2c.asm" 2236: #endif 2237: 2238: #ifdef cpu1 2239: #inc "I2C.asm" 2240: #endif 2241: 2242: org 0xB00 2243: ; send the MCM header 2244: raw_send_conf: 2245: #ifdef cpu0 2246: iext CHIPID 2247: lgio 0, CHIPID 2248: shl 7, c1, r0 2249: or r0, ChipPOS, r0 ; combine chip heade 2250: shl 10, r0, r0 2251: shl 10, r0, r0 ; 1 & ChipPOS(7) & 2 2252: mov 0xC, r1 2253: jmpr cc_busy, 0 2254: lpio GBUSR0, r2 2255: or r0, r2, r0 ; 1 & ChipPOS(7) & C 2256: shl 4, r0, r0 2257: or r0, r1, r0 ; 1 & ChipPOS(7) & C 2258: spio r0, NODP 2259: #endif 2260: jmp cc_uncond, raw_send_cnf 0B00 : 0000_0100_0000_0000_0000_1111 *** Include file "pack_conf.asm" 1: ; program to pack the configuration in the TRAP chip and sen 2: ; 3: ; by V.Angelov 4: ; 5: ; $Id: pack_conf.asm 2444 2008-11-12 08:27:09Z angelov $: 6: 7: #def cpu_clocks_pk = 0xF0F0 ; number of clocks f 8: 9: #def mask_data = r12 ; data bit mask 10: #def ret_addr = r7 ; return address 11: 12: ; write and exit 13: cm_pk_wr: 14: shl 1, r5, r5 ; r5 = (r5 << 1) | 1 0B01 : 1011_0010_0001_0000_1010_0101 15: or r5, c1, r5 0B02 : 1010_1010_0101_0110_0010_0101 16: spio r5, NODP 0B03 : 0010_0000_0101_0000_0000_0000 17: jmp cc_uncond, ret_addr ; exit 0B04 : 0000_1000_0111_0000_0000_1111 18: 19: cm_pack_5: 20: ; address in r14 21: ; number of words in r1 22: ; step in r3 23: 24: ; first build the header 25: lgio 0, r14 ; request the 1st da 0B05 : 1110_1000_0000_0001_1100_0000 26: shl 8, r14, r5 0B06 : 1011_0010_1000_0001_1100_0101 27: add r14, r3, r14 ; increment the read 0B07 : 1000_0010_1110_0000_0110_1110 28: or r5, r1, r5 ; r5 = (addr << 8) | 0B08 : 1010_1010_0101_0000_0010_0101 29: shl 7, r5, r5 0B09 : 1011_0010_0111_0000_1010_0101 30: mov 0x10, r2 0B0A : 1100_0110_0000_0010_0000_0010 31: or r5, r2, r5 ; r5 = (addr << 16) 0B0B : 1010_1010_0101_0000_0100_0101 32: or r5, r3, r5 0B0C : 1010_1010_0101_0000_0110_0101 33: shl 1, r5, r5 0B0D : 1011_0010_0001_0000_1010_0101 34: spio r5, NODP ; store the header 0B0E : 0010_0000_0101_0000_0000_0000 35: 36: mov 0x1F, mask_data ; the mask for the d 0B0F : 1100_0110_0000_0011_1110_1100 37: cm_pk_rp5: 38: jmpr cc_busy, 0 ; may be not needed! 0B10 : 0000_0101_0110_0010_0001_0111 39: lgio 0, r14 ; request the 2nd da 0B11 : 1110_1000_0000_0001_1100_0000 40: lpio GBUSR0, r5 ; read data into pac 0B12 : 1110_0110_0110_0000_0000_0101 41: and r5, mask_data, r5 0B13 : 1010_0110_0101_0001_1000_0101 42: sub r1, c1, r1 ; remaining number o 0B14 : 1000_1010_0001_0110_0010_0001 43: jmp cc_zero, cm_pk_wr ; no more registers 0B15 : 0000_0100_0000_0000_0001_0001 44: 45: add r14, r3, r14 ; increment the read 0B16 : 1000_0010_1110_0000_0110_1110 46: jmpr cc_busy, 0 ; may be not needed! 0B17 : 0000_0101_0110_0010_1111_0111 47: lgio 0, r14 ; request the 3th da 0B18 : 1110_1000_0000_0001_1100_0000 48: lpio GBUSR0, r4 ; read data 0B19 : 1110_0110_0110_0000_0000_0100 49: and r4, mask_data, r4 0B1A : 1010_0110_0100_0001_1000_0100 50: shl 5, r4, r4 0B1B : 1011_0010_0101_0000_1000_0100 51: or r5, r4, r5 0B1C : 1010_1010_0101_0000_1000_0101 52: sub r1, c1, r1 ; remaining number o 0B1D : 1000_1010_0001_0110_0010_0001 53: jmp cc_zero, cm_pk_wr ; no more registers 0B1E : 0000_0100_0000_0000_0001_0001 54: 55: add r14, r3, r14 ; increment the read 0B1F : 1000_0010_1110_0000_0110_1110 56: jmpr cc_busy, 0 ; may be not needed! 0B20 : 0000_0101_0110_0100_0001_0111 57: lgio 0, r14 ; request the 4th da 0B21 : 1110_1000_0000_0001_1100_0000 58: lpio GBUSR0, r4 ; read data 0B22 : 1110_0110_0110_0000_0000_0100 59: and r4, mask_data, r4 0B23 : 1010_0110_0100_0001_1000_0100 60: shl 10, r4, r4 0B24 : 1011_0010_1010_0000_1000_0100 61: or r5, r4, r5 0B25 : 1010_1010_0101_0000_1000_0101 62: sub r1, c1, r1 ; remaining number o 0B26 : 1000_1010_0001_0110_0010_0001 63: jmp cc_zero, cm_pk_wr ; no more registers 0B27 : 0000_0100_0000_0000_0001_0001 64: 65: add r14, r3, r14 ; increment the read 0B28 : 1000_0010_1110_0000_0110_1110 66: jmpr cc_busy, 0 ; may be not needed! 0B29 : 0000_0101_0110_0101_0011_0111 67: lgio 0, r14 ; request the 5th da 0B2A : 1110_1000_0000_0001_1100_0000 68: lpio GBUSR0, r4 ; read data 0B2B : 1110_0110_0110_0000_0000_0100 69: and r4, mask_data, r4 0B2C : 1010_0110_0100_0001_1000_0100 70: shl 15, r4, r4 0B2D : 1011_0010_1111_0000_1000_0100 71: or r5, r4, r5 0B2E : 1010_1010_0101_0000_1000_0101 72: sub r1, c1, r1 ; remaining number o 0B2F : 1000_1010_0001_0110_0010_0001 73: jmp cc_zero, cm_pk_wr ; no more registers 0B30 : 0000_0100_0000_0000_0001_0001 74: 75: add r14, r3, r14 ; increment the read 0B31 : 1000_0010_1110_0000_0110_1110 76: jmpr cc_busy, 0 ; may be not needed! 0B32 : 0000_0101_0110_0110_0101_0111 77: lgio 0, r14 ; request the 2nd da 0B33 : 1110_1000_0000_0001_1100_0000 78: lpio GBUSR0, r4 ; read data 0B34 : 1110_0110_0110_0000_0000_0100 79: and r4, mask_data, r4 0B35 : 1010_0110_0100_0001_1000_0100 80: shl 15, r4, r4 0B36 : 1011_0010_1111_0000_1000_0100 81: shl 5, r4, r4 0B37 : 1011_0010_0101_0000_1000_0100 82: or r5, r4, r5 0B38 : 1010_1010_0101_0000_1000_0101 83: sub r1, c1, r1 ; remaining number o 0B39 : 1000_1010_0001_0110_0010_0001 84: jmp cc_zero, cm_pk_wr ; no more registers 0B3A : 0000_0100_0000_0000_0001_0001 85: 86: add r14, r3, r14 ; increment the read 0B3B : 1000_0010_1110_0000_0110_1110 87: jmpr cc_busy, 0 ; may be not needed! 0B3C : 0000_0101_0110_0111_1001_0111 88: lgio 0, r14 ; request the 1st da 0B3D : 1110_1000_0000_0001_1100_0000 89: lpio GBUSR0, r4 ; read data 0B3E : 1110_0110_0110_0000_0000_0100 90: ; and r4, mask_data, r4 ; last time not nec 91: shl 15, r4, r4 0B3F : 1011_0010_1111_0000_1000_0100 92: shl 10, r4, r4 0B40 : 1011_0010_1010_0000_1000_0100 93: or r5, r4, r5 0B41 : 1010_1010_0101_0000_1000_0101 94: sub r1, c1, r1 ; remaining number o 0B42 : 1000_1010_0001_0110_0010_0001 95: jmp cc_zero, cm_pk_wr ; no more registers 0B43 : 0000_0100_0000_0000_0001_0001 96: 97: ; no more bits, write the packed registers 98: add r14, r3, r14 ; increment the read 0B44 : 1000_0010_1110_0000_0110_1110 99: shl 1, r5, r5 ; r5 = (r5 << 1) | 1 0B45 : 1011_0010_0001_0000_1010_0101 100: or r5, c1, r5 0B46 : 1010_1010_0101_0110_0010_0101 101: spio r5, NODP ; store 0B47 : 0010_0000_0101_0000_0000_0000 102: jmp cc_uncond, cm_pk_rp5 ; read next group of 0B48 : 0000_0100_0000_0000_0000_1111 103: 104: cm_pack_6: 105: ; address in r14 106: ; number of words in r1 107: 108: ; first build the header 109: shl 8, r14, r5 0B49 : 1011_0010_1000_0001_1100_0101 110: lgio+ 0 ; request the 1st da 0B4A : 1111_0100_0000_0000_0000_0000 111: or r5, r1, r5 ; r5 = (addr << 8) | 0B4B : 1010_1010_0101_0000_0010_0101 112: shl 8, r5, r5 0B4C : 1011_0010_1000_0000_1010_0101 113: mov 0x2A, r2 0B4D : 1100_0110_0000_0101_0100_0010 114: or r5, r2, r5 ; r5 = (addr << 16) 0B4E : 1010_1010_0101_0000_0100_0101 115: spio r5, NODP ; store the header 0B4F : 0010_0000_0101_0000_0000_0000 116: 117: mov 0x3F, mask_data ; the mask for the d 0B50 : 1100_0110_0000_0111_1110_1100 118: cm_pk_rp6: 119: jmpr cc_busy, 0 ; may be not needed! 0B51 : 0000_0101_0110_1010_0011_0111 120: lgio+ 0 ; request the next d 0B52 : 1111_0100_0000_0000_0000_0000 121: lpio GBUSR0, r5 ; read data into pac 0B53 : 1110_0110_0110_0000_0000_0101 122: and r5, mask_data, r5 0B54 : 1010_0110_0101_0001_1000_0101 123: sub r1, c1, r1 ; remaining number o 0B55 : 1000_1010_0001_0110_0010_0001 124: jmp cc_zero, cm_pk_wr ; no more registers 0B56 : 0000_0100_0000_0000_0001_0001 125: 126: jmpr cc_busy, 0 ; may be not needed! 0B57 : 0000_0101_0110_1010_1111_0111 127: lgio+ 0 ; request the next d 0B58 : 1111_0100_0000_0000_0000_0000 128: lpio GBUSR0, r4 ; read data 0B59 : 1110_0110_0110_0000_0000_0100 129: and r4, mask_data, r4 0B5A : 1010_0110_0100_0001_1000_0100 130: shl 6, r4, r4 0B5B : 1011_0010_0110_0000_1000_0100 131: or r5, r4, r5 0B5C : 1010_1010_0101_0000_1000_0101 132: sub r1, c1, r1 ; remaining number o 0B5D : 1000_1010_0001_0110_0010_0001 133: jmp cc_zero, cm_pk_wr ; no more registers 0B5E : 0000_0100_0000_0000_0001_0001 134: 135: jmpr cc_busy, 0 ; may be not needed! 0B5F : 0000_0101_0110_1011_1111_0111 136: lgio+ 0 ; request the next d 0B60 : 1111_0100_0000_0000_0000_0000 137: lpio GBUSR0, r4 ; read data 0B61 : 1110_0110_0110_0000_0000_0100 138: and r4, mask_data, r4 0B62 : 1010_0110_0100_0001_1000_0100 139: shl 12, r4, r4 0B63 : 1011_0010_1100_0000_1000_0100 140: or r5, r4, r5 0B64 : 1010_1010_0101_0000_1000_0101 141: sub r1, c1, r1 ; remaining number o 0B65 : 1000_1010_0001_0110_0010_0001 142: jmp cc_zero, cm_pk_wr ; no more registers 0B66 : 0000_0100_0000_0000_0001_0001 143: 144: jmpr cc_busy, 0 ; may be not needed! 0B67 : 0000_0101_0110_1100_1111_0111 145: lgio+ 0 ; request the next d 0B68 : 1111_0100_0000_0000_0000_0000 146: lpio GBUSR0, r4 ; read data 0B69 : 1110_0110_0110_0000_0000_0100 147: and r4, mask_data, r4 0B6A : 1010_0110_0100_0001_1000_0100 148: shl 12, r4, r4 0B6B : 1011_0010_1100_0000_1000_0100 149: shl 6, r4, r4 0B6C : 1011_0010_0110_0000_1000_0100 150: or r5, r4, r5 0B6D : 1010_1010_0101_0000_1000_0101 151: sub r1, c1, r1 ; remaining number o 0B6E : 1000_1010_0001_0110_0010_0001 152: jmp cc_zero, cm_pk_wr ; no more registers 0B6F : 0000_0100_0000_0000_0001_0001 153: 154: jmpr cc_busy, 0 ; may be not needed! 0B70 : 0000_0101_0110_1110_0001_0111 155: lgio+ 0 ; request the next d 0B71 : 1111_0100_0000_0000_0000_0000 156: lpio GBUSR0, r4 ; read data 0B72 : 1110_0110_0110_0000_0000_0100 157: ; and r4, mask_data, r4 ; last time not nec 158: shl 12, r4, r4 0B73 : 1011_0010_1100_0000_1000_0100 159: shl 12, r4, r4 0B74 : 1011_0010_1100_0000_1000_0100 160: or r5, r4, r5 0B75 : 1010_1010_0101_0000_1000_0101 161: sub r1, c1, r1 ; remaining number o 0B76 : 1000_1010_0001_0110_0010_0001 162: jmp cc_zero, cm_pk_wr ; no more registers 0B77 : 0000_0100_0000_0000_0001_0001 163: 164: ; no more bits, write the packed registers 165: shl 1, r5, r5 ; r5 = (r5 << 1) | 1 0B78 : 1011_0010_0001_0000_1010_0101 166: or r5, c1, r5 0B79 : 1010_1010_0101_0110_0010_0101 167: spio r5, NODP ; store 0B7A : 0010_0000_0101_0000_0000_0000 168: jmp cc_uncond, cm_pk_rp6 ; read next group of 0B7B : 0000_0100_0000_0000_0000_1111 169: 170: 171: cm_pack_7: 172: ; address in r14 173: ; number of words in r1 174: 175: ; first build the header 176: shl 8, r14, r5 0B7C : 1011_0010_1000_0001_1100_0101 177: lgio+ 0 ; request the 1st da 0B7D : 1111_0100_0000_0000_0000_0000 178: or r5, r1, r5 ; r5 = (addr << 8) | 0B7E : 1010_1010_0101_0000_0010_0101 179: shl 8, r5, r5 0B7F : 1011_0010_1000_0000_1010_0101 180: mov 0x32, r2 0B80 : 1100_0110_0000_0110_0100_0010 181: or r5, r2, r5 ; r5 = (addr << 16) 0B81 : 1010_1010_0101_0000_0100_0101 182: spio r5, NODP ; store the header 0B82 : 0010_0000_0101_0000_0000_0000 183: 184: mov 0x7F, mask_data ; the mask for the d 0B83 : 1100_0110_0000_1111_1110_1100 185: cm_pk_rp7: 186: jmpr cc_busy, 0 ; may be not needed! 0B84 : 0000_0101_0111_0000_1001_0111 187: lgio+ 0 ; request the next d 0B85 : 1111_0100_0000_0000_0000_0000 188: lpio GBUSR0, r5 ; read data into pac 0B86 : 1110_0110_0110_0000_0000_0101 189: and r5, mask_data, r5 0B87 : 1010_0110_0101_0001_1000_0101 190: sub r1, c1, r1 ; remaining number o 0B88 : 1000_1010_0001_0110_0010_0001 191: jmp cc_zero, cm_pk_wr ; no more registers 0B89 : 0000_0100_0000_0000_0001_0001 192: 193: jmpr cc_busy, 0 ; may be not needed! 0B8A : 0000_0101_0111_0001_0101_0111 194: lgio+ 0 ; request the next d 0B8B : 1111_0100_0000_0000_0000_0000 195: lpio GBUSR0, r4 ; read data 0B8C : 1110_0110_0110_0000_0000_0100 196: and r4, mask_data, r4 0B8D : 1010_0110_0100_0001_1000_0100 197: shl 7, r4, r4 0B8E : 1011_0010_0111_0000_1000_0100 198: or r5, r4, r5 0B8F : 1010_1010_0101_0000_1000_0101 199: sub r1, c1, r1 ; remaining number o 0B90 : 1000_1010_0001_0110_0010_0001 200: jmp cc_zero, cm_pk_wr ; no more registers 0B91 : 0000_0100_0000_0000_0001_0001 201: 202: jmpr cc_busy, 0 ; may be not needed! 0B92 : 0000_0101_0111_0010_0101_0111 203: lgio+ 0 ; request the next d 0B93 : 1111_0100_0000_0000_0000_0000 204: lpio GBUSR0, r4 ; read data 0B94 : 1110_0110_0110_0000_0000_0100 205: and r4, mask_data, r4 0B95 : 1010_0110_0100_0001_1000_0100 206: shl 14, r4, r4 0B96 : 1011_0010_1110_0000_1000_0100 207: or r5, r4, r5 0B97 : 1010_1010_0101_0000_1000_0101 208: sub r1, c1, r1 ; remaining number o 0B98 : 1000_1010_0001_0110_0010_0001 209: jmp cc_zero, cm_pk_wr ; no more registers 0B99 : 0000_0100_0000_0000_0001_0001 210: 211: jmpr cc_busy, 0 ; may be not needed! 0B9A : 0000_0101_0111_0011_0101_0111 212: lgio+ 0 ; request the next d 0B9B : 1111_0100_0000_0000_0000_0000 213: lpio GBUSR0, r4 ; read data 0B9C : 1110_0110_0110_0000_0000_0100 214: ; and r4, mask_data, r4 ; last time not nec 215: shl 14, r4, r4 0B9D : 1011_0010_1110_0000_1000_0100 216: shl 7, r4, r4 0B9E : 1011_0010_0111_0000_1000_0100 217: or r5, r4, r5 0B9F : 1010_1010_0101_0000_1000_0101 218: sub r1, c1, r1 ; remaining number o 0BA0 : 1000_1010_0001_0110_0010_0001 219: jmp cc_zero, cm_pk_wr ; no more registers 0BA1 : 0000_0100_0000_0000_0001_0001 220: 221: ; no more bits, write the packed registers 222: shl 1, r5, r5 ; r5 = (r5 << 1) | 1 0BA2 : 1011_0010_0001_0000_1010_0101 223: or r5, c1, r5 0BA3 : 1010_1010_0101_0110_0010_0101 224: spio r5, NODP ; store 0BA4 : 0010_0000_0101_0000_0000_0000 225: jmp cc_uncond, cm_pk_rp7 ; read next group of 0BA5 : 0000_0100_0000_0000_0000_1111 226: 227: cm_pack_10: 228: ; address in r14 229: ; number of words in r1 230: 231: ; first build the header 232: shl 8, r14, r5 0BA6 : 1011_0010_1000_0001_1100_0101 233: lgio+ 0 ; request the 1st da 0BA7 : 1111_0100_0000_0000_0000_0000 234: or r5, r1, r5 ; r5 = (addr << 8) | 0BA8 : 1010_1010_0101_0000_0010_0101 235: shl 8, r5, r5 0BA9 : 1011_0010_1000_0000_1010_0101 236: mov 0x4A, r2 0BAA : 1100_0110_0000_1001_0100_0010 237: or r5, r2, r5 ; r5 = (addr << 16) 0BAB : 1010_1010_0101_0000_0100_0101 238: spio r5, NODP ; store the header 0BAC : 0010_0000_0101_0000_0000_0000 239: 240: mov 0x3FF, mask_data ; the mask for the d 0BAD : 1100_0110_0111_1111_1110_1100 241: cm_pk_rp10: 242: jmpr cc_busy, 0 ; may be not needed! 0BAE : 0000_0101_0111_0101_1101_0111 243: lgio+ 0 ; request the next d 0BAF : 1111_0100_0000_0000_0000_0000 244: lpio GBUSR0, r5 ; read data into pac 0BB0 : 1110_0110_0110_0000_0000_0101 245: and r5, mask_data, r5 0BB1 : 1010_0110_0101_0001_1000_0101 246: sub r1, c1, r1 ; remaining number o 0BB2 : 1000_1010_0001_0110_0010_0001 247: jmp cc_zero, cm_pk_wr ; no more registers 0BB3 : 0000_0100_0000_0000_0001_0001 248: 249: jmpr cc_busy, 0 ; may be not needed! 0BB4 : 0000_0101_0111_0110_1001_0111 250: lgio+ 0 ; request the next d 0BB5 : 1111_0100_0000_0000_0000_0000 251: lpio GBUSR0, r4 ; read data 0BB6 : 1110_0110_0110_0000_0000_0100 252: and r4, mask_data, r4 0BB7 : 1010_0110_0100_0001_1000_0100 253: shl 10, r4, r4 0BB8 : 1011_0010_1010_0000_1000_0100 254: or r5, r4, r5 0BB9 : 1010_1010_0101_0000_1000_0101 255: sub r1, c1, r1 ; remaining number o 0BBA : 1000_1010_0001_0110_0010_0001 256: jmp cc_zero, cm_pk_wr ; no more registers 0BBB : 0000_0100_0000_0000_0001_0001 257: 258: jmpr cc_busy, 0 ; may be not needed! 0BBC : 0000_0101_0111_0111_1001_0111 259: lgio+ 0 ; request the next d 0BBD : 1111_0100_0000_0000_0000_0000 260: lpio GBUSR0, r4 ; read data 0BBE : 1110_0110_0110_0000_0000_0100 261: ; and r4, mask_data, r4 ; last time not nec 262: shl 10, r4, r4 0BBF : 1011_0010_1010_0000_1000_0100 263: shl 10, r4, r4 0BC0 : 1011_0010_1010_0000_1000_0100 264: or r5, r4, r5 0BC1 : 1010_1010_0101_0000_1000_0101 265: sub r1, c1, r1 ; remaining number o 0BC2 : 1000_1010_0001_0110_0010_0001 266: jmp cc_zero, cm_pk_wr ; no more registers 0BC3 : 0000_0100_0000_0000_0001_0001 267: 268: ; no more bits, write the packed registers 269: shl 1, r5, r5 ; r5 = (r5 << 1) | 1 0BC4 : 1011_0010_0001_0000_1010_0101 270: or r5, c1, r5 0BC5 : 1010_1010_0101_0110_0010_0101 271: spio r5, NODP ; store 0BC6 : 0010_0000_0101_0000_0000_0000 272: jmp cc_uncond, cm_pk_rp10 ; read next group of 0BC7 : 0000_0100_0000_0000_0000_1111 273: 274: cm_pack_15: 275: ; address in r14 276: ; number of words in r1 277: 278: ; first build the header 279: shl 8, r14, r5 0BC8 : 1011_0010_1000_0001_1100_0101 280: lgio+ 0 ; request the 1st da 0BC9 : 1111_0100_0000_0000_0000_0000 281: or r5, r1, r5 ; r5 = (addr << 8) | 0BCA : 1010_1010_0101_0000_0010_0101 282: shl 8, r5, r5 0BCB : 1011_0010_1000_0000_1010_0101 283: mov 0x72, r2 0BCC : 1100_0110_0000_1110_0100_0010 284: or r5, r2, r5 ; r5 = (addr << 16) 0BCD : 1010_1010_0101_0000_0100_0101 285: spio r5, NODP ; store the header 0BCE : 0010_0000_0101_0000_0000_0000 286: iext 0x7FFF 0BCF : 0101_0000_0000_0000_0000_0111 287: mov 0x7FFF, mask_data ; the mask for the d 0BD0 : 1100_0111_1111_1111_1110_1100 288: cm_pk_rp15: 289: jmpr cc_busy, 0 ; may be not needed! 0BD1 : 0000_0101_0111_1010_0011_0111 290: lgio+ 0 ; request the next d 0BD2 : 1111_0100_0000_0000_0000_0000 291: lpio GBUSR0, r5 ; read data into pac 0BD3 : 1110_0110_0110_0000_0000_0101 292: and r5, mask_data, r5 0BD4 : 1010_0110_0101_0001_1000_0101 293: sub r1, c1, r1 ; remaining number o 0BD5 : 1000_1010_0001_0110_0010_0001 294: jmp cc_zero, cm_pk_wr ; no more registers 0BD6 : 0000_0100_0000_0000_0001_0001 295: 296: jmpr cc_busy, 0 ; may be not needed! 0BD7 : 0000_0101_0111_1010_1111_0111 297: lgio+ 0 ; request the next d 0BD8 : 1111_0100_0000_0000_0000_0000 298: lpio GBUSR0, r4 ; read data 0BD9 : 1110_0110_0110_0000_0000_0100 299: ; and r4, mask_data, r4 ; last time not nec 300: shl 15, r4, r4 0BDA : 1011_0010_1111_0000_1000_0100 301: or r5, r4, r5 0BDB : 1010_1010_0101_0000_1000_0101 302: sub r1, c1, r1 ; remaining number o 0BDC : 1000_1010_0001_0110_0010_0001 303: jmp cc_zero, cm_pk_wr ; no more registers 0BDD : 0000_0100_0000_0000_0001_0001 304: 305: ; no more bits, write the packed registers 306: shl 1, r5, r5 ; r5 = (r5 << 1) | 1 0BDE : 1011_0010_0001_0000_1010_0101 307: or r5, c1, r5 0BDF : 1010_1010_0101_0110_0010_0101 308: spio r5, NODP ; store 0BE0 : 0010_0000_0101_0000_0000_0000 309: jmp cc_uncond, cm_pk_rp15 ; read next group of 0BE1 : 0000_0100_0000_0000_0000_1111 310: 311: ; 31 bit case 312: cm_pack_31: 313: ; step is always 1 314: ; address in r14 315: ; number of words in r1 316: 317: ; first build the header 318: shl 8, r14, r5 0BE2 : 1011_0010_1000_0001_1100_0101 319: or r5, r1, r5 ; r5 = (addr << 8) | 0BE3 : 1010_1010_0101_0000_0010_0101 320: shl 8, r5, r5 ; r5 = (addr << 16) 0BE4 : 1011_0010_1000_0000_1010_0101 321: mov 0xF2, r2 0BE5 : 1100_0110_0001_1110_0100_0010 322: or r5, r2, r5 ; r5 = (addr << 16) 0BE6 : 1010_1010_0101_0000_0100_0101 323: spio r5, NODP ; store the header 0BE7 : 0010_0000_0101_0000_0000_0000 324: cm_pk_31n: 325: lgio+ 0 ; request the next d 0BE8 : 1111_0100_0000_0000_0000_0000 326: jmpr cc_busy, 0 0BE9 : 0000_0101_0111_1101_0011_0111 327: lpio GBUSR0, r4 ; read data 0BEA : 1110_0110_0110_0000_0000_0100 328: shl 1, r4, r4 ; shift left 0BEB : 1011_0010_0001_0000_1000_0100 329: or r4, c1, r4 ; set the LSB 0BEC : 1010_1010_0100_0110_0010_0100 330: spio r4, NODP 0BED : 0010_0000_0100_0000_0000_0000 331: sub r1, c1, r1 ; decrement the numb 0BEE : 1000_1010_0001_0110_0010_0001 332: jmp cc_nzero, cm_pk_31n ; next 32 bit word 0BEF : 0000_0100_0000_0000_0000_0001 333: jmp cc_uncond, ret_addr ; exit 0BF0 : 0000_1000_0111_0000_0000_1111 334: 335: ; single case 336: cm_pack_s16: 337: ; here we have in r14 the address 338: lgio 0, r14 0BF1 : 1110_1000_0000_0001_1100_0000 339: swp r14, r5 ; r5 = (addr << 16) 0BF2 : 0111_1010_0000_0001_1100_0101 340: iext 0xFFFF 0BF3 : 0101_0000_0000_0000_0000_1111 341: mov 0xFFFF, r2 0BF4 : 1100_0111_1111_1111_1110_0010 342: jmpr cc_busy, 0 0BF5 : 0000_0101_0111_1110_1011_0111 343: lpio GBUSR0, r4 ; read data 0BF6 : 1110_0110_0110_0000_0000_0100 344: and r4, r2, r4 ; data = (data & 0xF 0BF7 : 1010_0110_0100_0000_0100_0100 345: or r5, r4, r5 ; (addr << 16) | dat 0BF8 : 1010_1010_0101_0000_1000_0101 346: shl 2, r5, r5 0BF9 : 1011_0010_0010_0000_1010_0101 347: or r5, c1, r5 ; (addr << 18) | (da 0BFA : 1010_1010_0101_0110_0010_0101 348: spio r5, NODP 0BFB : 0010_0000_0101_0000_0000_0000 349: jmp cc_uncond, ret_addr ; exit 0BFC : 0000_1000_0111_0000_0000_1111 350: 351: cm_pack_s32: 352: ; here we have in r14 the address 353: lgio 0, r14 0BFD : 1110_1000_0000_0001_1100_0000 354: swp r14, r5 ; r5 = (addr << 16) 0BFE : 0111_1010_0000_0001_1100_0101 355: iext 0xFFFF 0BFF : 0101_0000_0000_0000_0000_1111 356: mov 0xFFFF, r2 0C00 : 1100_0111_1111_1111_1110_0010 357: jmpr cc_busy, 0 0C01 : 0000_0101_1000_0000_0011_0111 358: lpio GBUSR0, r4 ; read data 0C02 : 1110_0110_0110_0000_0000_0100 359: and r4, r2, r3 ; dataLo = data & 0x 0C03 : 1010_0110_0100_0000_0100_0011 360: or r5, r3, r5 ; (addr << 16) | dat 0C04 : 1010_1010_0101_0000_0110_0101 361: shl 2, r5, r5 0C05 : 1011_0010_0010_0000_1010_0101 362: or r5, c3, r5 ; (addr << 18) | (da 0C06 : 1010_1010_0101_0110_0110_0101 363: spio r5, NODP 0C07 : 0010_0000_0101_0000_0000_0000 364: or r4, c1, r4 0C08 : 1010_1010_0100_0110_0010_0100 365: spio r4, NODP 0C09 : 0010_0000_0100_0000_0000_0000 366: jmp cc_uncond, ret_addr ; exit 0C0A : 0000_1000_0111_0000_0000_1111 367: 368: raw_send_cnf: 369: 370: #ifdef cpu_clocks_pk 371: mov 0x640, r0 0C0B : 1100_0110_1100_1000_0000_0000 372: spio r0, CTPCTRL 0C0C : 0010_0000_0000_0010_0000_0001 373: mov 0, r0 0C0D : 1100_0110_0000_0000_0000_0000 374: spio r0, CTPDINI 0C0E : 0010_0000_0000_0010_0000_0000 375: #endif 376: *** Include file "pack_conf_inc.asm" 1: ; Include file generated by PackConfASM (trap_cnf) 2: ; Pack the configuration and send via the readout tree 3: #ifdef cpu0 4: iext 0x3180 5: mov 0x3180, r14 ; address of TPL00 6: mov 128, r1 ; number of registers 7: mov 1, r3 ; address step 8: mvpcr, +2, r7 ; return address 9: jmp cc_uncond, cm_pack_5 ; block with 5 bit registe 10: iext 0x30a0 11: mov 0x30a0, r14 ; address of FGA0 12: mov 21, r1 ; number of registers 13: mvpcr, +2, r7 ; return address 14: jmp cc_uncond, cm_pack_6 ; block with 6 bit registe 15: iext 0x3080 16: mov 0x3080, r14 ; address of FGF0 17: mov 21, r1 ; number of registers 18: mvpcr, +2, r7 ; return address 19: jmp cc_uncond, cm_pack_10 ; block with 10 bit regist 20: mov 0x0a20, r14 ; address of CPU0CLK 21: mov 12, r1 ; number of registers 22: mov 2, r3 ; address step 23: mvpcr, +2, r7 ; return address 24: jmp cc_uncond, cm_pack_5 ; block with 5 bit registe 25: #endif 26: #ifdef cpu1 27: iext 0x3014 28: mov 0x3014, r14 ; address of EBIS 29: mov 3, r1 ; number of registers 30: mvpcr, +2, r7 ; return address 31: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 32: iext 0x3042 33: mov 0x3042, r14 ; address of TPVT 34: mov 10, r1 ; number of registers 35: mvpcr, +2, r7 ; return address 36: jmp cc_uncond, cm_pack_6 ; block with 6 bit registe 37: iext 0x3017 38: mov 0x3017, r14 ; address of EBIN 39: mov 6, r1 ; number of registers 40: mov 1, r3 ; address step 41: mvpcr, +2, r7 ; return address 42: jmp cc_uncond, cm_pack_5 ; block with 5 bit registe 43: iext 0x3100 44: mov 0x3100, r14 ; address of FLL00 45: mov 64, r1 ; number of registers 46: mvpcr, +2, r7 ; return address 47: jmp cc_uncond, cm_pack_6 ; block with 6 bit registe 48: iext 0x3000 49: mov 0x3000, r14 ; address of TPPT0 50: mov 16, r1 ; number of registers 51: mvpcr, +2, r7 ; return address 52: jmp cc_uncond, cm_pack_7 ; block with 7 bit registe 53: iext 0x3020 54: mov 0x3020, r14 ; address of FPTC 55: mov 3, r1 ; number of registers 56: mvpcr, +2, r7 ; return address 57: jmp cc_uncond, cm_pack_10 ; block with 10 bit regist 58: iext 0x3028 59: mov 0x3028, r14 ; address of FGTA 60: mov 3, r1 ; number of registers 61: mvpcr, +2, r7 ; return address 62: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 63: iext 0x3030 64: mov 0x3030, r14 ; address of FTAL 65: mov 3, r1 ; number of registers 66: mvpcr, +2, r7 ; return address 67: jmp cc_uncond, cm_pack_10 ; block with 10 bit regist 68: iext 0x3038 69: mov 0x3038, r14 ; address of FCW1 70: mov 5, r1 ; number of registers 71: mvpcr, +2, r7 ; return address 72: jmp cc_uncond, cm_pack_10 ; block with 10 bit regist 73: iext 0x3040 74: mov 0x3040, r14 ; address of TPFP 75: mov 2, r1 ; number of registers 76: mvpcr, +2, r7 ; return address 77: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 78: iext 0x3050 79: mov 0x3050, r14 ; address of ADCMSK 80: mvpcr, +2, r7 ; return address 81: jmp cc_uncond, cm_pack_s32 ; > 16 bits 82: iext 0x3051 83: mov 0x3051, r14 ; address of ADCINB 84: mov 2, r1 ; number of registers 85: mov 1, r3 ; address step 86: mvpcr, +2, r7 ; return address 87: jmp cc_uncond, cm_pack_5 ; block with 5 bit registe 88: iext 0x3053 89: mov 0x3053, r14 ; address of ADCPAR 90: mvpcr, +2, r7 ; return address 91: jmp cc_uncond, cm_pack_s32 ; > 16 bits 92: iext 0x3054 93: mov 0x3054, r14 ; address of ADCTST 94: mov 2, r1 ; number of registers 95: mov 1, r3 ; address step 96: mvpcr, +2, r7 ; return address 97: jmp cc_uncond, cm_pack_5 ; block with 5 bit registe 98: iext 0x3158 99: mov 0x3158, r14 ; address of PASADEL 100: mov 4, r1 ; number of registers 101: mvpcr, +2, r7 ; return address 102: jmp cc_uncond, cm_pack_10 ; block with 10 bit regist 103: iext 0x315d 104: mov 0x315d, r14 ; address of PASASTL 105: mov 3, r1 ; number of registers 106: mvpcr, +2, r7 ; return address 107: jmp cc_uncond, cm_pack_10 ; block with 10 bit regist 108: iext 0x3161 109: mov 0x3161, r14 ; address of SADCTRG 110: mov 3, r1 ; number of registers 111: mov 1, r3 ; address step 112: mvpcr, +2, r7 ; return address 113: jmp cc_uncond, cm_pack_5 ; block with 5 bit registe 114: iext 0x3165 115: mov 0x3165, r14 ; address of L0TSIM 116: mov 2, r1 ; number of registers 117: mvpcr, +2, r7 ; return address 118: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 119: iext 0x3170 120: mov 0x3170, r14 ; address of SADCMC 121: mov 2, r1 ; number of registers 122: mvpcr, +2, r7 ; return address 123: jmp cc_uncond, cm_pack_10 ; block with 10 bit regist 124: iext 0x3172 125: mov 0x3172, r14 ; address of SADCGTB 126: mvpcr, +2, r7 ; return address 127: jmp cc_uncond, cm_pack_s32 ; > 16 bits 128: iext 0x3178 129: mov 0x3178, r14 ; address of SEBDEN 130: mov 2, r1 ; number of registers 131: mov 1, r3 ; address step 132: mvpcr, +2, r7 ; return address 133: jmp cc_uncond, cm_pack_5 ; block with 5 bit registe 134: #endif 135: #ifdef cpu2 136: mov 0x0a00, r14 ; address of SML0 0C0F : 1100_0111_0100_0000_0000_1110 137: mov 3, r1 ; number of registers 0C10 : 1100_0110_0000_0000_0110_0001 138: mvpcr, +2, r7 ; return address 0C11 : 1100_0111_1000_0010_0110_0111 139: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 0C12 : 0000_0100_0000_0000_0000_1111 140: mov 0x0a03, r14 ; address of SMMODE 0C13 : 1100_0111_0100_0000_0110_1110 141: mvpcr, +2, r7 ; return address 0C14 : 1100_0111_1000_0010_1100_0111 142: jmp cc_uncond, cm_pack_s16 ; up to 16 bits 0C15 : 0000_0100_0000_0000_0000_1111 143: mov 0x0a08, r14 ; address of NITM0 0C16 : 1100_0111_0100_0001_0000_1110 144: mov 4, r1 ; number of registers 0C17 : 1100_0110_0000_0000_1000_0001 145: mvpcr, +2, r7 ; return address 0C18 : 1100_0111_1000_0011_0100_0111 146: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 0C19 : 0000_0100_0000_0000_0000_1111 147: mov 0x0a3f, r14 ; address of ARBTIM 0C1A : 1100_0111_0100_0111_1110_1110 148: mvpcr, +2, r7 ; return address 0C1B : 1100_0111_1000_0011_1010_0111 149: jmp cc_uncond, cm_pack_s16 ; up to 16 bits 0C1C : 0000_0100_0000_0000_0000_1111 150: mov 0x0b00, r14 ; address of IA0IRQ0 0C1D : 1100_0111_0110_0000_0000_1110 151: mov 16, r1 ; number of registers 0C1E : 1100_0110_0000_0010_0000_0001 152: mvpcr, +2, r7 ; return address 0C1F : 1100_0111_1000_0100_0010_0111 153: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 0C20 : 0000_0100_0000_0000_0000_1111 154: mov 0x0b20, r14 ; address of IA1IRQ0 0C21 : 1100_0111_0110_0100_0000_1110 155: mov 16, r1 ; number of registers 0C22 : 1100_0110_0000_0010_0000_0001 156: mvpcr, +2, r7 ; return address 0C23 : 1100_0111_1000_0100_1010_0111 157: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 0C24 : 0000_0100_0000_0000_0000_1111 158: mov 0x0b40, r14 ; address of IA2IRQ0 0C25 : 1100_0111_0110_1000_0000_1110 159: mov 16, r1 ; number of registers 0C26 : 1100_0110_0000_0010_0000_0001 160: mvpcr, +2, r7 ; return address 0C27 : 1100_0111_1000_0101_0010_0111 161: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 0C28 : 0000_0100_0000_0000_0000_1111 162: mov 0x0b60, r14 ; address of IA3IRQ0 0C29 : 1100_0111_0110_1100_0000_1110 163: mov 16, r1 ; number of registers 0C2A : 1100_0110_0000_0010_0000_0001 164: mvpcr, +2, r7 ; return address 0C2B : 1100_0111_1000_0101_1010_0111 165: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 0C2C : 0000_0100_0000_0000_0000_1111 166: mov 0x0b80, r14 ; address of CTGDINI 0C2D : 1100_0111_0111_0000_0000_1110 167: mvpcr, +2, r7 ; return address 0C2E : 1100_0111_1000_0110_0000_0111 168: jmp cc_uncond, cm_pack_s32 ; > 16 bits 0C2F : 0000_0100_0000_0000_0000_1111 169: mov 0x0b81, r14 ; address of CTGCTRL 0C30 : 1100_0111_0111_0000_0010_1110 170: mvpcr, +2, r7 ; return address 0C31 : 1100_0111_1000_0110_0110_0111 171: jmp cc_uncond, cm_pack_s16 ; up to 16 bits 0C32 : 0000_0100_0000_0000_0000_1111 172: iext 0xd000 0C33 : 0101_0000_0000_0000_0000_1101 173: mov 0xd000, r14 ; address of MEMRW 0C34 : 1100_0110_0000_0000_0000_1110 174: mov 4, r1 ; number of registers 0C35 : 1100_0110_0000_0000_1000_0001 175: mvpcr, +2, r7 ; return address 0C36 : 1100_0111_1000_0111_0000_0111 176: jmp cc_uncond, cm_pack_10 ; block with 10 bit regist 0C37 : 0000_0100_0000_0000_0000_1111 177: mov 0x0d40, r14 ; address of NMOD 0C38 : 1100_0111_1010_1000_0000_1110 178: mov 5, r1 ; number of registers 0C39 : 1100_0110_0000_0000_1010_0001 179: mvpcr, +2, r7 ; return address 0C3A : 1100_0111_1000_0111_1000_0111 180: jmp cc_uncond, cm_pack_31 ; block with 16..31 bit re 0C3B : 0000_0100_0000_0000_0000_1111 181: mov 0x0d47, r14 ; address of NBND 0C3C : 1100_0111_1010_1000_1110_1110 182: mvpcr, +2, r7 ; return address 0C3D : 1100_0111_1000_0111_1110_0111 183: jmp cc_uncond, cm_pack_s16 ; up to 16 bits 0C3E : 0000_0100_0000_0000_0000_1111 184: mov 0x0d48, r14 ; address of NP0 0C3F : 1100_0111_1010_1001_0000_1110 185: mov 4, r1 ; number of registers 0C40 : 1100_0110_0000_0000_1000_0001 186: mvpcr, +2, r7 ; return address 0C41 : 1100_0111_1000_1000_0110_0111 187: jmp cc_uncond, cm_pack_15 ; block with 6..15 bit reg 0C42 : 0000_0100_0000_0000_0000_1111 188: #endif 189: #ifdef cpu3 190: mov 0x0c00, r14 ; address of C08CPU0 191: mvpcr, +2, r7 ; return address 192: jmp cc_uncond, cm_pack_s32 ; > 16 bits 193: mov 0x0c01, r14 ; address of C09CPU0 194: mvpcr, +2, r7 ; return address 195: jmp cc_uncond, cm_pack_s32 ; > 16 bits 196: mov 0x0c02, r14 ; address of C10CPU0 197: mvpcr, +2, r7 ; return address 198: jmp cc_uncond, cm_pack_s32 ; > 16 bits 199: mov 0x0c03, r14 ; address of C11CPU0 200: mvpcr, +2, r7 ; return address 201: jmp cc_uncond, cm_pack_s32 ; > 16 bits 202: mov 0x0c04, r14 ; address of C12CPUA 203: mvpcr, +2, r7 ; return address 204: jmp cc_uncond, cm_pack_s32 ; > 16 bits 205: mov 0x0c05, r14 ; address of C13CPUA 206: mvpcr, +2, r7 ; return address 207: jmp cc_uncond, cm_pack_s32 ; > 16 bits 208: mov 0x0c06, r14 ; address of C14CPUA 209: mvpcr, +2, r7 ; return address 210: jmp cc_uncond, cm_pack_s32 ; > 16 bits 211: mov 0x0c07, r14 ; address of C15CPUA 212: mvpcr, +2, r7 ; return address 213: jmp cc_uncond, cm_pack_s32 ; > 16 bits 214: mov 0x0c08, r14 ; address of C08CPU1 215: mvpcr, +2, r7 ; return address 216: jmp cc_uncond, cm_pack_s32 ; > 16 bits 217: mov 0x0c09, r14 ; address of C09CPU1 218: mvpcr, +2, r7 ; return address 219: jmp cc_uncond, cm_pack_s32 ; > 16 bits 220: mov 0x0c0a, r14 ; address of C10CPU1 221: mvpcr, +2, r7 ; return address 222: jmp cc_uncond, cm_pack_s32 ; > 16 bits 223: mov 0x0c0b, r14 ; address of C11CPU1 224: mvpcr, +2, r7 ; return address 225: jmp cc_uncond, cm_pack_s32 ; > 16 bits 226: mov 0x0c10, r14 ; address of C08CPU2 227: mvpcr, +2, r7 ; return address 228: jmp cc_uncond, cm_pack_s32 ; > 16 bits 229: mov 0x0c11, r14 ; address of C09CPU2 230: mvpcr, +2, r7 ; return address 231: jmp cc_uncond, cm_pack_s32 ; > 16 bits 232: mov 0x0c12, r14 ; address of C10CPU2 233: mvpcr, +2, r7 ; return address 234: jmp cc_uncond, cm_pack_s32 ; > 16 bits 235: mov 0x0c13, r14 ; address of C11CPU2 236: mvpcr, +2, r7 ; return address 237: jmp cc_uncond, cm_pack_s32 ; > 16 bits 238: mov 0x0c18, r14 ; address of C08CPU3 239: mvpcr, +2, r7 ; return address 240: jmp cc_uncond, cm_pack_s32 ; > 16 bits 241: mov 0x0c19, r14 ; address of C09CPU3 242: mvpcr, +2, r7 ; return address 243: jmp cc_uncond, cm_pack_s32 ; > 16 bits 244: mov 0x0c1a, r14 ; address of C10CPU3 245: mvpcr, +2, r7 ; return address 246: jmp cc_uncond, cm_pack_s32 ; > 16 bits 247: mov 0x0c1b, r14 ; address of C11CPU3 248: mvpcr, +2, r7 ; return address 249: jmp cc_uncond, cm_pack_s32 ; > 16 bits 250: mov 0x0d45, r14 ; address of NES 251: mvpcr, +2, r7 ; return address 252: jmp cc_uncond, cm_pack_s32 ; > 16 bits 253: mov 0x0d46, r14 ; address of NTP 254: mvpcr, +2, r7 ; return address 255: jmp cc_uncond, cm_pack_s32 ; > 16 bits 256: mov 0x0d4c, r14 ; address of NCUT 257: mvpcr, +2, r7 ; return address 258: jmp cc_uncond, cm_pack_s32 ; > 16 bits 259: iext 0x315c 260: mov 0x315c, r14 ; address of PASACHM 261: mvpcr, +2, r7 ; return address 262: jmp cc_uncond, cm_pack_s32 ; > 16 bits 263: #endif 264: ; CPU0: 40 dwords, 182 registers 265: ; CPU1: 62 dwords, 138 registers 266: ; CPU2: 60 dwords, 89 registers 267: ; CPU3: 48 dwords, 24 registers 268: ; total dwords 210, registers 433 *** End of include file SRC/pack_conf_inc.asm 378: 379: #ifdef cpu_clocks_pk 380: lpio CTPDOUT, r6 ; the number of CPU 0C43 : 1110_0110_0100_0000_0100_0110 381: jmpr cc_busy, 0 0C44 : 0000_0101_1000_1000_1001_0111 382: iext cpu_clocks_pk 0C45 : 0101_0000_0000_0000_0000_1111 383: mov cpu_clocks_pk, r5 0C46 : 1100_0110_0001_1110_0000_0101 384: add r5, c5, r5 0C47 : 1000_0010_0101_0110_1010_0101 385: sgio r6, r5 0C48 : 0010_0100_0110_0000_1010_0000 386: #endif 387: 388: #ifdef cpu3 389: iext 0x00FE7FFF 390: mov 0x00FE7FFF, r0 391: swp r0, r0 392: spio r0, NODP ; end marker for con 393: #endif 394: jmp cc_uncond, raw_complete_ni_tmsn 0C49 : 0000_0100_0000_0000_0000_1111 *** End of include file SRC/pack_conf.asm 2262: 2263: org 0xD00 2264: ;#inc "config_man.asm" *** Include file "conf_mann.asm" 1: ; program to pack/unpack/crc32 the configuration in the TRAP 2: ; 3: ; by V.Angelov 4: ; 5: ; $Id: conf_mann.asm 2444 2008-11-12 08:27:09Z angelov $: 6: ; 7: ; The format for single conf. reg. 8: ; (addr << 18) | (data & 0xFFFF) << 2) | (flag32 << 1) | 1 9: ; Bit 0 is 1 10: ; Bit 1 (flag32) is 0 for up to 16 bit data and 1 for more 11: ; Bits 31..18 - address (note: up to 14 bits!) 12: ; Bits 17..2 - data, the lower up to 16 bits 13: ; in case of > 16 bits, a second dword is sent: 14: ; data | 1 15: 16: 17: ; The format of a block is 18: ; 19: ; (address << 16) | (words << 8) | (widthM1 << 3) | (astep < 20: ; Block start_address(31..16) words(15..8) widthM1(7..3) as 21: ; - start_address is 16-bit, with small exceptions all confi 22: ; below 0x3FFF 23: ; - words (8 bit) is the number of configuration words, not 24: ; of 32-bit data words that follow 25: ; words=0 means end of the data => our end marker is j 26: ;- widthM1 (5 bit) the bitwidth-1, possible values: 27: ; 4 for up to 6 x 5 bits 28: ; 5 for up to 5 x 6 bits 29: ; 6 for up to 4 x 7 bits 30: ; 9 for up to 3 x 10 bits 31: ; 14 for up to 2 x 15 bits 32: ; 30 for 1 x 31 bits 33: ;- astep 1|2 is the increment of the TRAP IO address, normal 34: ; any other width, or astep=0,3, or words=0 will stop the un 35: ; So there are many possible endmarkers. Just need to be dif 36: ; and from the MCM header!!! 37: 38: ; 31 30..16 15..8 7..3 2..1 0 39: ; 0 0x7FFF 0x00 0x1F 3 0 => 0x7FFF00FE is a 40: 41: ; This program is better executed by cpu0..2, not 3, because 42: 43: ; unpack 44: ; input: in c8 the start address in GIO 45: ; output: all configuration registers in the TRAP 46: ; unpacking time 44 us 47: 48: #def mask_1F = r9 ; 5 bit mask 49: #def mask_FF = r10 ; 8 bit mask 50: #def mask_FFFF = r11 ; 16 bit mask 51: #def mask_data = r12 ; data bit mask 52: 53: #def cnst_sa = c8 ; the start addr 54: #def cmp_errors_un = 0xF0F0 ; number of diff 55: #def cpu_clocks_un = 0xF0F1 ; number of cloc 56: #def cpu_clocks_crc = 0xF0F2 ; number of cloc 57: #def cpu_clocks_pk = 0xF0F3 ; number of cloc 58: 59: 60: ;#def cnf_compare = 1 ; enable compar 61: ;#def debug = 1 ; enable debugg 62: ;#def debugT = 1 ; enable timer 63: 64: conf_man_un: 65: #ifdef debugT 66: mov 0x640, r0 67: spio r0, CTPCTRL 68: mov 0, r0 69: spio r0, CTPDINI 70: #endif 71: 72: ; initialization 73: #ifdef debug 74: mov 0 , r15 ; the DMEM point 75: #endif 76: iext 0xFFFF 0D00 : 0101_0000_0000_0000_0000_1111 77: mov 0xFFFF, mask_FFFF 0D01 : 1100_0111_1111_1111_1110_1011 78: and mask_FFFF, cnst_sa, r14 ; the GIO access 0D02 : 1010_0110_1011_0111_0000_1110 79: mov r14, r13 ; copy of the st 0D03 : 1100_0010_0000_0001_1100_1101 80: lgio+ 0 ; request to rea 0D04 : 1111_0100_0000_0000_0000_0000 81: mov 0x1F, mask_1F ; prepare the ma 0D05 : 1100_0110_0000_0011_1110_1001 82: mov 0xFF, mask_FF 0D06 : 1100_0110_0001_1111_1110_1010 83: #ifdef cnf_compare 84: mov 0, r7 ; error counter 85: #endif 86: 87: ; start loop - next block/single 88: conf_man_un_next: 89: #ifdef debug 90: sra+ r14 ; debugging 91: #endif 92: jmpr cc_busy, 0 0D07 : 0000_0101_1010_0000_1111_0111 93: lpio GBUSR0, r0 0D08 : 1110_0110_0110_0000_0000_0000 94: lgio+ 0 ; read the next 0D09 : 1111_0100_0000_0000_0000_0000 95: #ifdef debug 96: sra+ r0 ; debugging 97: #endif 98: shl -1, r0, r0 ; check the 0th 0D0A : 1011_0011_1111_0000_0000_0000 99: jmp cc_carry, conf_man_un_sng ; jump to single 0D0B : 0000_0100_0000_0000_0001_0000 100: shl -7, r0, r1 ; shift right th 0D0C : 1011_0011_1001_0000_0000_0001 101: and mask_FF, r1, r1 ; number of word 0D0D : 1010_0110_1010_0000_0010_0001 102: #ifdef debug 103: sra+ r1 ; debugging 104: #endif 105: jmp cc_zero, conf_man_un_exit ; exit if 0 0D0E : 0000_0100_0000_0000_0001_0001 106: shl -2, r0, r2 ; shift the widt 0D0F : 1011_0011_1110_0000_0000_0010 107: and mask_1F, r2, r2 ; width-1 in r2 0D10 : 1010_0110_1001_0000_0100_0010 108: add r2, c1, r2 ; width in r2 0D11 : 1000_0010_0010_0110_0010_0010 109: #ifdef debug 110: sra+ r2 ; debugging 111: #endif 112: and r0, c3, r3 ; step in r3 0D12 : 1010_0110_0000_0110_0110_0011 113: #ifdef debug 114: sra+ r3 ; debugging 115: #endif 116: shl -15, r0, r0 ; address, not n 0D13 : 1011_0011_0001_0000_0000_0000 117: #ifdef debug 118: sra+ r0 ; debugging 119: #endif 120: 121: ; order according to the most frequent appearence!!! 122: cmp r2, 15 0D14 : 1100_1000_0010_0000_0000_1111 123: jmp cc_eq, conf_man_un_5_15 ; 15 bit case 0D15 : 0000_0100_0000_0000_0001_0001 124: cmp r2, 10 0D16 : 1100_1000_0010_0000_0000_1010 125: jmp cc_eq, conf_man_un_5_15 ; 10 bit case 0D17 : 0000_0100_0000_0000_0001_0001 126: cmp r2, 5 0D18 : 1100_1000_0010_0000_0000_0101 127: jmp cc_eq, conf_man_un_5_15 ; 5 bit case 0D19 : 0000_0100_0000_0000_0001_0001 128: cmp r2, 31 0D1A : 1100_1000_0010_0000_0001_1111 129: jmp cc_eq, conf_man_un_31 ; 31 bit case 0D1B : 0000_0100_0000_0000_0001_0001 130: cmp r2, 6 0D1C : 1100_1000_0010_0000_0000_0110 131: jmp cc_eq, conf_man_un_5_15 ; 6 bit case 0D1D : 0000_0100_0000_0000_0001_0001 132: cmp r2, 7 0D1E : 1100_1000_0010_0000_0000_0111 133: jmp cc_eq, conf_man_un_5_15 ; 7 bit case 0D1F : 0000_0100_0000_0000_0001_0001 134: ; if no one of the cases above => exit 135: jmp cc_uncond, conf_man_un_exit ; exit 0D20 : 0000_0100_0000_0000_0000_1111 136: 137: ; 5,6,7,10,15 bit cases 138: conf_man_un_5_15: 139: ; step in r3 140: ; width in r2 141: ; address in r0 142: ; number of words in r1 143: #ifdef cnf_compare 144: shl r2, c1, mask_data 145: sub mask_data, c1, mask_data ; the mask for t 146: #endif 147: neg r2, r2 ; later we need 0D21 : 1010_1110_0000_0000_0100_0010 148: mov 0, g1 ; bit counter 0D22 : 1100_0110_0000_0000_0001_0001 149: 150: conf_man_un_rd: 151: add r2, g1, g1 ; actually subtr 0D23 : 1000_0010_0010_0010_0011_0001 152: jmp cc_nneg, conf_man_un_nf ; no need to rea 0D24 : 0000_0100_0000_0000_0000_0010 153: ; jmpr cc_busy, 0 ; not necessary 154: lgio+ 0 ; request the ne 0D25 : 1111_0100_0000_0000_0000_0000 155: lpio GBUSR0, r4 ; read data 0D26 : 1110_0110_0110_0000_0000_0100 156: shl -1, r4, r4 ; shift right, t 0D27 : 1011_0011_1111_0000_1000_0100 157: mov 31, g1 ; init the bit c 0D28 : 1100_0110_0000_0011_1111_0001 158: add r2, g1, g1 ; and subtract t 0D29 : 1000_0010_0010_0010_0011_0001 159: conf_man_un_nf: 160: ; extract the field 161: #ifdef cnf_compare 162: ; jmpr cc_busy, 0 ; not necessary 163: lgio 1, r0 164: and r4, mask_data, r5 ; mask the upper 165: jmpr cc_busy, 0 166: lpio GBUSR1, r6 ; read data 167: and r6, mask_data, r6 ; mask the upper 168: cmp r5, r6 ; compare 169: ; jmpr cc_eq, +3 ; skip the error 170: jmpr cc_eq, +2 ; skip the error 171: add r7, c1, r7 ; count up the e 172: #else 173: ; jmpr cc_busy, 0 ; not necessary 174: #endif 175: sgio r4, r0 ; store to GIO t 0D2A : 0010_0100_0100_0000_0000_0000 176: #ifdef debug 177: sra+ r0 ; debugging 178: nop 179: sra+ r5 180: #endif 181: add r0, r3, r0 ; increment the 0D2B : 1000_0010_0000_0000_0110_0000 182: shl r2, r4, r4 ; shift right th 0D2C : 0111_0010_0010_0000_1000_0100 183: sub r1, c1, r1 ; decrement the 0D2D : 1000_1010_0001_0110_0010_0001 184: jmp cc_nzero, conf_man_un_rd ; extract next f 0D2E : 0000_0100_0000_0000_0000_0001 185: jmp cc_uncond, conf_man_un_next ; next block/sin 0D2F : 0000_0100_0000_0000_0000_1111 186: 187: ; 31 bit case 188: conf_man_un_31: 189: ; step in r3 190: ; address in r0 191: ; number of words in r1 192: shl -1, c7, mask_data 0D30 : 1011_0011_1111_0110_1110_1100 193: conf_man_un_31n: 194: ; jmpr cc_busy, 0 195: lgio+ 0 ; request the ne 0D31 : 1111_0100_0000_0000_0000_0000 196: lpio GBUSR0, r4 ; read data 0D32 : 1110_0110_0110_0000_0000_0100 197: shl -1, r4, r4 ; shift right, t 0D33 : 1011_0011_1111_0000_1000_0100 198: #ifdef cnf_compare 199: jmpr cc_busy, 0 200: lgio 1, r0 201: jmpr cc_busy, 0 202: lpio GBUSR1, r5 ; read data 203: and r5, mask_data, r5 ; mask the upper 204: cmp r5, r4 ; compare 205: ; jmpr cc_eq, +3 ; skip the error 206: jmpr cc_eq, +2 ; skip the error 207: add r7, c1, r7 ; count up the e 208: #else 209: jmpr cc_busy, 0 0D34 : 0000_0101_1010_0110_1001_0111 210: #endif 211: sgio r4, r0 ; store to GIO 0D35 : 0010_0100_0100_0000_0000_0000 212: #ifdef debug 213: sra+ r0 ; debugging 214: nop 215: sra+ r4 216: #endif 217: add r0, r3, r0 ; increment the 0D36 : 1000_0010_0000_0000_0110_0000 218: sub r1, c1, r1 ; decrement the 0D37 : 1000_1010_0001_0110_0010_0001 219: jmp cc_nzero, conf_man_un_31n ; next 32 bit wo 0D38 : 0000_0100_0000_0000_0000_0001 220: jmp cc_uncond, conf_man_un_next ; next block/sin 0D39 : 0000_0100_0000_0000_0000_1111 221: 222: ; single case 223: conf_man_un_sng: 224: ; here we have in r0 the data 225: shl -1, r0, r1 0D3A : 1011_0011_1111_0000_0000_0001 226: and r1, mask_FFFF, r1 ; data in r1, up 0D3B : 1010_0110_0001_0001_0110_0001 227: jmp cc_ncarry, conf_man_un_s16 ; 1 means more t 0D3C : 0000_0100_0000_0000_0000_0000 228: ; read the upper bits from the next dword 229: ;jmpr cc_busy, 0 230: lgio+ 0 ; request the ne 0D3D : 1111_0100_0000_0000_0000_0000 231: lpio GBUSR0, r4 ; read data 0D3E : 1110_0110_0110_0000_0000_0100 232: and r4, c6, r4 ; clear the bit 0D3F : 1010_0110_0100_0110_1100_0100 233: or r4, r1, r1 ; combine all to 0D40 : 1010_1010_0100_0000_0010_0001 234: conf_man_un_s16: 235: shl -11, r0, r0 ;[30..17] contai 0D41 : 1011_0011_0101_0000_0000_0000 236: shl -6, r0, r0 ; address in r0 0D42 : 1011_0011_1010_0000_0000_0000 237: #ifdef cnf_compare 238: jmpr cc_busy, 0 239: lgio 1, r0 240: jmpr cc_busy, 0 241: lpio GBUSR1, r5 ; read data 242: ; and r5, mask_FFFF, r5 ; data in r1 243: cmp r5, r1 ; compare 244: ; jmpr cc_eq, +3 ; skip the erro 245: jmpr cc_eq, +2 ; skip the error 246: add r7, c1, r7 ; count up the e 247: #else 248: ;jmpr cc_busy, 0 249: #endif 250: sgio r1, r0 0D43 : 0010_0100_0001_0000_0000_0000 251: #ifdef debug 252: sra+ r0 ; debugging 253: nop 254: sra+ r1 255: #endif 256: jmp cc_uncond, conf_man_un_next 0D44 : 0000_0100_0000_0000_0000_1111 257: 258: conf_man_un_exit: 259: #ifdef debugT 260: #ifdef cnf_compare 261: jmpr cc_busy, 0 262: iext cmp_errors_un 263: sgio r7, cmp_errors_un ; c11 of CPU0 in 264: #endif 265: lpio CTPDOUT, r6 ; the number of 266: jmpr cc_busy, 0 267: iext cpu_clocks_un 268: sgio r6, cpu_clocks_un 269: #endif 270: sub r14, c1, r14 0D45 : 1000_1010_1110_0110_0010_1110 271: jmp cc_uncond, crc32 ; calculate crc3 0D46 : 0000_0100_0000_0000_0000_1111 272: conf_man_un_lp: 273: #ifdef debugT 274: lpio CTPDOUT, r6 ; the number of 275: jmpr cc_busy, 0 276: iext cpu_clocks_crc 277: sgio r6, cpu_clocks_crc 278: #endif 279: 280: ; low power 281: shl 4, c12, r0 ; event counter << 2 0D47 : 1011_0010_0100_0111_1000_0000 282: or r0, c3, r0 ; (event counter << 0D48 : 1010_1010_0000_0110_0110_0000 283: iext LP_REP 0D49 : 0101_0000_0000_0000_0000_1111 284: mov LP_REP, r1 0D4A : 1100_0110_0001_1100_1000_0001 285: add r1, c5, r1 ; + CPU# 0D4B : 1000_0010_0001_0110_1010_0001 286: jmpr cc_busy, 0 0D4C : 0000_0101_1010_1001_1001_0111 287: sgio r0, r1 0D4D : 0010_0100_0000_0000_0010_0000 288: 289: mov cmd_lp, r0 0D4E : 1100_0110_0000_0010_0100_0000 290: jmpr cc_busy, 0 0D4F : 0000_0101_1010_1001_1111_0111 291: sgio r0, SMCMD ; go to low powe 0D50 : 0010_1000_0000_1010_0000_0100 292: jmpr cc_busy, 0 0D51 : 0000_0101_1010_1010_0011_0111 293: jmpr cc_uncond, 0 0D52 : 0000_0101_1010_1010_0100_1111 294: nop 0D53 : 0000_0000_0000_0000_0000_0000 295: 296: 297: ; execution time about 400 us 298: ; input: r14 points to the CRC32 word 299: ; r13 points to the packed conf. block (typic 300: crc32: mov r14, r2 ; r14 last value 0D54 : 1100_0010_0000_0001_1100_0010 301: mov r13, r14 ; the GIO access 0D55 : 1100_0010_0000_0001_1010_1110 302: lgio+ 0 ; request the fi 0D56 : 1111_0100_0000_0000_0000_0000 303: mov c7, r1 ; the CRC32 regi 0D57 : 1100_0010_0000_0110_1110_0001 304: 305: iext 0x04C11DB7 0D58 : 0101_0000_0100_1100_0001_0001 306: mov 0x04C11DB7, r3 ; the generator 0D59 : 1100_0111_1011_0110_1110_0011 307: jmpr cc_busy, 0 0D5A : 0000_0101_1010_1011_0101_0111 308: 309: crc32_next_word: 310: mov 32, r5 ; init the bit c 0D5B : 1100_0110_0000_0100_0000_0101 311: lpio GBUSR0, r0 ; hold the data, 0D5C : 1110_0110_0110_0000_0000_0000 312: lgio+ 0 ; request the ne 0D5D : 1111_0100_0000_0000_0000_0000 313: 314: crc32_next_bit: 315: shl -1, r0, r0 ; shift right r0 0D5E : 1011_0011_1111_0000_0000_0000 316: adc r1, r1, r1 ; shift left r1 0D5F : 1000_0110_0001_0000_0010_0001 317: jmpr cc_ncarry, +2 ; skip the xor i 0D60 : 0000_0101_1010_1100_0100_0000 318: xor r1, r3, r1 ; xor with the g 0D61 : 1010_0010_0001_0000_0110_0001 319: sub r5, c1, r5 ; dec the bit co 0D62 : 1000_1010_0101_0110_0010_0101 320: jmp cc_nzero, crc32_next_bit ; end of the bit 0D63 : 0000_0100_0000_0000_0000_0001 321: cmp r14, r2 ; compare with t 0D64 : 1000_1000_1110_0000_0100_0000 322: jmp cc_leu, crc32_next_word ; end of the loo 0D65 : 0000_0100_0000_0000_0001_1000 323: 324: xor r1, c7, r1 ; xor with FF..F 0D66 : 1010_0010_0001_0110_1110_0001 325: lpio GBUSR0, r0 0D67 : 1110_0110_0110_0000_0000_0000 326: cmp r1, r0 ; compare the ap 0D68 : 1000_1000_0001_0000_0000_0000 327: sgio+ r1 ; store the calc 0D69 : 0011_1100_0001_0000_0000_0000 328: jmp cc_uncond, conf_man_un_lp 0D6A : 0000_0100_0000_0000_0000_1111 329: nop 0D6B : 0000_0000_0000_0000_0000_0000 330: 331: 332: ; pack 333: ; input: in c8 the start address in GIO 334: ; output (typically, dep. on c8): in 0xf000..0xf0d2 335: ; packing time 89 us 336: 337: conf_man_pk: 338: #ifdef debugT 339: mov 0x640, r0 340: spio r0, CTPCTRL 341: mov 0, r0 342: spio r0, CTPDINI 343: #endif 344: 345: ; initialization 346: #ifdef debug 347: mov 0 , r15 ; the DMEM point 348: #endif 349: iext 0xFFFF 0D6C : 0101_0000_0000_0000_0000_1111 350: mov 0xFFFF, mask_FFFF 0D6D : 1100_0111_1111_1111_1110_1011 351: and mask_FFFF, cnst_sa, r14 ; the GIO access 0D6E : 1010_0110_1011_0111_0000_1110 352: mov 0x1F, mask_1F ; prepare the ma 0D6F : 1100_0110_0000_0011_1110_1001 353: mov 0xFF, mask_FF 0D70 : 1100_0110_0001_1111_1110_1010 354: 355: ; start loop - next block/single 356: conf_man_pk_next: 357: jmpr cc_busy, 0 0D71 : 0000_0101_1010_1110_0011_0111 358: lgio+ 0 ; read the next 0D72 : 1111_0100_0000_0000_0000_0000 359: jmpr cc_busy, 0 0D73 : 0000_0101_1010_1110_0111_0111 360: lpio GBUSR0, r0 0D74 : 1110_0110_0110_0000_0000_0000 361: shl -1, r0, r0 ; check the 0th 0D75 : 1011_0011_1111_0000_0000_0000 362: jmp cc_carry, conf_man_pk_sng ; jump to single 0D76 : 0000_0100_0000_0000_0001_0000 363: shl -7, r0, r1 ; shift right th 0D77 : 1011_0011_1001_0000_0000_0001 364: and mask_FF, r1, r1 ; number of word 0D78 : 1010_0110_1010_0000_0010_0001 365: jmp cc_zero, conf_man_pk_exit ; exit if 0 0D79 : 0000_0100_0000_0000_0001_0001 366: shl -2, r0, r2 ; shift the widt 0D7A : 1011_0011_1110_0000_0000_0010 367: and mask_1F, r2, r2 ; width-1 in r2 0D7B : 1010_0110_1001_0000_0100_0010 368: add r2, c1, r2 ; width in r2 0D7C : 1000_0010_0010_0110_0010_0010 369: and r0, c3, r3 ; step in r3 0D7D : 1010_0110_0000_0110_0110_0011 370: shl -15, r0, r0 ; address, not n 0D7E : 1011_0011_0001_0000_0000_0000 371: 372: ; order according to the most frequent appearence!!! 373: cmp r2, 15 0D7F : 1100_1000_0010_0000_0000_1111 374: jmp cc_eq, conf_man_pk_5_15 ; 15 bit case 0D80 : 0000_0100_0000_0000_0001_0001 375: cmp r2, 10 0D81 : 1100_1000_0010_0000_0000_1010 376: jmp cc_eq, conf_man_pk_5_15 ; 10 bit case 0D82 : 0000_0100_0000_0000_0001_0001 377: cmp r2, 5 0D83 : 1100_1000_0010_0000_0000_0101 378: jmp cc_eq, conf_man_pk_5_15 ; 5 bit case 0D84 : 0000_0100_0000_0000_0001_0001 379: cmp r2, 31 0D85 : 1100_1000_0010_0000_0001_1111 380: jmp cc_eq, conf_man_pk_31 ; 31 bit case 0D86 : 0000_0100_0000_0000_0001_0001 381: cmp r2, 6 0D87 : 1100_1000_0010_0000_0000_0110 382: jmp cc_eq, conf_man_pk_5_15 ; 6 bit case 0D88 : 0000_0100_0000_0000_0001_0001 383: cmp r2, 7 0D89 : 1100_1000_0010_0000_0000_0111 384: jmp cc_eq, conf_man_pk_5_15 ; 7 bit case 0D8A : 0000_0100_0000_0000_0001_0001 385: ; if no one of the cases above => exit 386: jmp cc_uncond, conf_man_pk_exit ; exit 0D8B : 0000_0100_0000_0000_0000_1111 387: 388: ; 5,6,7,10,15 bit cases 389: conf_man_pk_5_15: 390: ; step in r3 391: ; width in r2 392: ; address in r0 393: ; number of words in r1 394: shl r2, c1, mask_data 0D8C : 0111_0010_0010_0110_0010_1100 395: sub mask_data, c1, mask_data ; the mask for t 0D8D : 1000_1010_1100_0110_0010_1100 396: conf_man_pk_rp: 397: mov 0, r8 ; bit counter 0D8E : 1100_0110_0000_0000_0000_1000 398: mov 0, r5 ; packed data re 0D8F : 1100_0110_0000_0000_0000_0101 399: 400: conf_man_pk_rd: 401: jmpr cc_busy, 0 0D90 : 0000_0101_1011_0010_0001_0111 402: lgio 0, r0 ; request the ne 0D91 : 1110_1000_0000_0000_0000_0000 403: add r0, r3, r0 ; increment the 0D92 : 1000_0010_0000_0000_0110_0000 404: shl -1, r8, r7 0D93 : 1011_0011_1111_0001_0000_0111 405: jmpr cc_busy, 0 0D94 : 0000_0101_1011_0010_1001_0111 406: lpio GBUSR0, r4 ; read data 0D95 : 1110_0110_0110_0000_0000_0100 407: and r4, mask_data, r4 ; mask the upper 0D96 : 1010_0110_0100_0001_1000_0100 408: cmp r8, 15 0D97 : 1100_1000_1000_0000_0000_1111 409: 410: jmp cc_gtu, conf_man_pk_rdl 0D98 : 0000_0100_0000_0000_0000_1000 411: conf_man_pk_rds: 412: shl r8, r4, r4 ; r4 = r4 << bit 0D99 : 0111_0010_1000_0000_1000_0100 413: conf_man_pk_ns: 414: or r4, r5, r5 ; r5 = r5 | r4 0D9A : 1010_1010_0100_0000_1010_0101 415: sub r1, c1, r1 ; remaining numb 0D9B : 1000_1010_0001_0110_0010_0001 416: jmp cc_zero, conf_man_pk_wr ; no more regist 0D9C : 0000_0100_0000_0000_0001_0001 417: add r8, r2, r8 ; increment the 0D9D : 1000_0010_1000_0000_0100_1000 418: cmp r8, 27 0D9E : 1100_1000_1000_0000_0001_1011 419: jmp cc_ltu, conf_man_pk_rd ; more bits avai 0D9F : 0000_0100_0000_0000_0001_0000 420: ; no more bits, write the packed registers 421: shl 1, r5, r5 ; r5 = (r5 << 1) 0DA0 : 1011_0010_0001_0000_1010_0101 422: or r5, c1, r5 0DA1 : 1010_1010_0101_0110_0010_0101 423: sgio+ r5 ; store 0DA2 : 0011_1100_0101_0000_0000_0000 424: jmp cc_uncond, conf_man_pk_rp ; read next grou 0DA3 : 0000_0100_0000_0000_0000_1111 425: conf_man_pk_rdl: 426: shl r7, r4, r4 ; shift right in 0DA4 : 0111_0010_0111_0000_1000_0100 427: sub r8, r7, r7 0DA5 : 1000_1010_1000_0000_1110_0111 428: shl r7, r4, r4 ; r4 = r4 << bit 0DA6 : 0111_0010_0111_0000_1000_0100 429: jmp cc_uncond, conf_man_pk_ns 0DA7 : 0000_0100_0000_0000_0000_1111 430: 431: ; write and exit 432: conf_man_pk_wr: 433: shl 1, r5, r5 ; r5 = (r5 << 1) 0DA8 : 1011_0010_0001_0000_1010_0101 434: or r5, c1, r5 0DA9 : 1010_1010_0101_0110_0010_0101 435: sgio+ r5 0DAA : 0011_1100_0101_0000_0000_0000 436: jmp cc_uncond, conf_man_pk_next ; next block/sin 0DAB : 0000_0100_0000_0000_0000_1111 437: 438: ; 31 bit case 439: conf_man_pk_31: 440: ; step in r3 441: ; address in r0 442: ; number of words in r1 443: jmpr cc_busy, 0 0DAC : 0000_0101_1011_0101_1001_0111 444: lgio 0, r0 ; request the ne 0DAD : 1110_1000_0000_0000_0000_0000 445: add r0, r3, r0 ; increment the 0DAE : 1000_0010_0000_0000_0110_0000 446: jmpr cc_busy, 0 0DAF : 0000_0101_1011_0101_1111_0111 447: lpio GBUSR0, r4 ; read data 0DB0 : 1110_0110_0110_0000_0000_0100 448: shl 1, r4, r4 ; shift right, t 0DB1 : 1011_0010_0001_0000_1000_0100 449: or r4, c1, r4 0DB2 : 1010_1010_0100_0110_0010_0100 450: sgio+ r4 0DB3 : 0011_1100_0100_0000_0000_0000 451: sub r1, c1, r1 ; decrement the 0DB4 : 1000_1010_0001_0110_0010_0001 452: jmp cc_nzero, conf_man_pk_31 ; next 32 bit wo 0DB5 : 0000_0100_0000_0000_0000_0001 453: jmp cc_uncond, conf_man_pk_next ; next block/sin 0DB6 : 0000_0100_0000_0000_0000_1111 454: 455: ; single case 456: conf_man_pk_sng: 457: ; here we have in r0 the data shifted to the right 458: shl -11, r0, r1 ;[30..17] contai 0DB7 : 1011_0011_0101_0000_0000_0001 459: shl -6, r1, r1 ; address in r1 0DB8 : 1011_0011_1010_0000_0010_0001 460: jmpr cc_busy, 0 0DB9 : 0000_0101_1011_0111_0011_0111 461: lgio 0, r1 0DBA : 1110_1000_0000_0000_0010_0000 462: and r0, c1, r3 ; copy the flag3 0DBB : 1010_0110_0000_0110_0010_0011 463: sub r14, c1, r14 ; decrease r14, 0DBC : 1000_1010_1110_0110_0010_1110 464: ; we need to wri 465: jmpr cc_busy, 0 0DBD : 0000_0101_1011_0111_1011_0111 466: lpio GBUSR0, r4 ; read data 0DBE : 1110_0110_0110_0000_0000_0100 467: 468: shl 14, r1, r5 ; r5 = (addr << 0DBF : 1011_0010_1110_0000_0010_0101 469: shl 2, r5, r5 ; r5 = (addr << 0DC0 : 1011_0010_0010_0000_1010_0101 470: and r4, mask_FFFF, r2 ; r2 = Lo(data) 0DC1 : 1010_0110_0100_0001_0110_0010 471: or r5, r2, r5 ; (addr << 16) | 0DC2 : 1010_1010_0101_0000_0100_0101 472: shl 1, r5, r5 0DC3 : 1011_0010_0001_0000_1010_0101 473: or r5, r3, r5 ; (addr << 17) | 0DC4 : 1010_1010_0101_0000_0110_0101 474: shl 1, r5, r5 0DC5 : 1011_0010_0001_0000_1010_0101 475: or r5, c1, r5 ; (addr << 18) | 0DC6 : 1010_1010_0101_0110_0010_0101 476: sgio+ r5 0DC7 : 0011_1100_0101_0000_0000_0000 477: 478: and r3, c1, r3 ; check if > 16 0DC8 : 1010_0110_0011_0110_0010_0011 479: jmp cc_zero, conf_man_pk_next ; exit if not 0DC9 : 0000_0100_0000_0000_0001_0001 480: 481: ; > 16 bits single 482: or r4, c1, r5 0DCA : 1010_1010_0100_0110_0010_0101 483: jmpr cc_busy, 0 0DCB : 0000_0101_1011_1001_0111_0111 484: sgio+ r5 0DCC : 0011_1100_0101_0000_0000_0000 485: jmp cc_uncond, conf_man_pk_next 0DCD : 0000_0100_0000_0000_0000_1111 486: 487: conf_man_pk_exit: 488: #ifdef debugT 489: lpio CTPDOUT, r6 ; the number of 490: jmpr cc_busy, 0 491: iext cpu_clocks_pk 492: sgio r6, cpu_clocks_pk 493: #else 494: nop 0DCE : 0000_0000_0000_0000_0000_0000 495: #endif 496: ; sub r14, c1, r14 497: ; jmp cc_uncond, crc32 ; calculate crc 498: conf_man_pk_lp: 499: ; #ifdef debugT 500: ; lpio CTPDOUT, r6 ; the number of 501: ; jmpr cc_busy, 0 502: ; iext cpu_clocks_crc 503: ; sgio r6, cpu_clocks_crc 504: ; #endif 505: 506: ; low power 507: shl 4, c12, r0 ; event counter << 2 0DCF : 1011_0010_0100_0111_1000_0000 508: or r0, c3, r0 ; (event counter << 0DD0 : 1010_1010_0000_0110_0110_0000 509: iext LP_REP 0DD1 : 0101_0000_0000_0000_0000_1111 510: mov LP_REP, r1 0DD2 : 1100_0110_0001_1100_1000_0001 511: add r1, c5, r1 ; + CPU# 0DD3 : 1000_0010_0001_0110_1010_0001 512: jmpr cc_busy, 0 0DD4 : 0000_0101_1011_1010_1001_0111 513: sgio r0, r1 0DD5 : 0010_0100_0000_0000_0010_0000 514: 515: mov cmd_lp, r0 0DD6 : 1100_0110_0000_0010_0100_0000 516: jmpr cc_busy, 0 0DD7 : 0000_0101_1011_1010_1111_0111 517: sgio r0, SMCMD ; go to low powe 0DD8 : 0010_1000_0000_1010_0000_0100 518: jmpr cc_busy, 0 0DD9 : 0000_0101_1011_1011_0011_0111 519: jmpr cc_uncond, 0 0DDA : 0000_0101_1011_1011_0100_1111 520: nop 0DDB : 0000_0000_0000_0000_0000_0000 *** End of include file SRC/conf_mann.asm 2266: 2267: org 0xE00 *** Include file "adc2cpu.asm" 1: ; subprogram to read the ADCs directly and to write them to 2: ; 3: ; $Id: adc2cpu.asm 1949 2008-02-18 20:13:19Z angelov $: 4: 5: ; input 6: ; c10 contains one or two start addresses 0x100+i 7: 8: ; Start Address CPU ADCs 9: ; 0x100..0x107 0 0.. 7 10: ; 0x100..0x107 1 5..12 11: ; 0x100..0x107 2 9..16 12: ; 0x100..0x107 3 13..20 13: 14: ; c11 is the number of words-1 (bits 31..16) and the start a 15: ; the start addresses of IMEM0,1,2,3 are 0x8000, 0x9000, 0xA 16: ; after each increment, the address will be ANDed with 0xB00 17: ; after 0xBFFF to 0xA000! This is useful when using cpu1,2. 18: 19: ; Note that c11 is optionally used for debugging as counter 20: ; So when using adc2cpu disable these counters! 21: 22: #def debug_adc2cpu = 1; write to DMEM some parameters 23: 24: ; ONE channel 25: ; cpu start address max samples uses IMEM 26: ; 0 0x9000 3*4096*2 1,2,3 27: ; or 28: ; 1 0xA000 3*4096*2 2,3,0 29: ; or 30: ; 2 0xB000 3*4096*2 3,0,1 31: ; or 32: ; 3 0xA000 3*4096*2 0,1,2 33: 34: ; TWO channels in TWO CPUs 35: ; CPUs start addr max samples uses IMEM 36: ; 0,1 0xA000,0xB000 2 x 4096*2 2,3 37: ; ... 38: 39: adc2cpu: 40: mov c11, r0 0E00 : 1100_0010_0000_0111_0110_0000 41: iext 0xFFFF 0E01 : 0101_0000_0000_0000_0000_1111 42: mov 0xFFFF, r1 0E02 : 1100_0111_1111_1111_1110_0001 43: and r0, r1, r10 ; start address in GIO 0E03 : 1010_0110_0000_0000_0010_1010 44: jmp cc_zero, adc2cpu_off ; turn off if 0 0E04 : 0000_0100_0000_0000_0001_0001 45: 46: swp r0, r0 ; now bits 15..0 0E05 : 0111_1010_0000_0000_0000_0000 47: and r0, r1, r11 ; number of words 0E06 : 1010_0110_0000_0000_0010_1011 48: jmp cc_zero, adc2cpu_off ; turn off if 0 0E07 : 0000_0100_0000_0000_0001_0001 49: 50: mov 0x3FF, r2 ; mask for the ADC 0E08 : 1100_0110_0111_1111_1110_0010 51: shl 12, r2, r3 0E09 : 1011_0010_1100_0000_0100_0011 52: or r2, r3, r2 0E0A : 1010_1010_0010_0000_0110_0010 53: 54: iext 0xBFFF 0E0B : 0101_0000_0000_0000_0000_1011 55: mov 0xBFFF, r9 ; mask for the address in GI 0E0C : 1100_0111_1111_1111_1110_1001 56: 57: mov c10, r0 0E0D : 1100_0010_0000_0111_0100_0000 58: mov 0x107, r1 0E0E : 1100_0110_0010_0000_1110_0001 59: and r0, r1, r12 ; r12 points to the address 0E0F : 1010_0110_0000_0000_0010_1100 60: jmp cc_zero, adc2cpu_off ; turn off if 0 0E10 : 0000_0100_0000_0000_0001_0001 61: mov adc2cpu_1adc, r8 0E11 : 1100_0110_0000_0000_0000_1000 62: 63: shlt 1, r0 0E12 : 1011_0000_0001_0000_0000_0000 64: jmp cc_ncarry, adc2cpu_2adc_tst 0E13 : 0000_0100_0000_0000_0000_0000 65: swp r0, r0 0E14 : 0111_1010_0000_0000_0000_0000 66: mov 0xFFF, r3 0E15 : 1100_0111_1111_1111_1110_0011 67: and r3, r0, r3 ; the oversampling factor 0E16 : 1010_0110_0011_0000_0000_0011 68: mov r3, r4 ; the oversampling counter 0E17 : 1100_0010_0000_0000_0110_0100 69: mov 0, r1 ; the accumulator 0E18 : 1100_0110_0000_0000_0000_0001 70: mov 0x200, r14 0E19 : 1100_0110_0100_0000_0000_1110 71: mov adc2cpu_1dec, r8 ; 0E1A : 1100_0110_0000_0000_0000_1000 72: jmp cc_uncond, adc2cpu_sync_prep 0E1B : 0000_0100_0000_0000_0000_1111 73: 74: adc2cpu_2adc_tst: 75: swp r0, r0 ; now take bits 15..0 0E1C : 0111_1010_0000_0000_0000_0000 76: and r0, r1, r13 ; r13 points to the address 0E1D : 1010_0110_0000_0000_0010_1101 77: jmpr cc_zero, +2 0E1E : 0000_0101_1100_0100_0001_0001 78: mov adc2cpu_2adc, r8 0E1F : 1100_0110_0000_0000_0000_1000 79: 80: adc2cpu_sync_prep: 81: ; now sync... 82: cli 0E20 : 0010_1100_0000_0000_0000_0000 83: mov adc2cpu_sync, r0 0E21 : 1100_0110_0000_0000_0000_0000 84: mov 0x20, r5 0E22 : 1100_0110_0000_0100_0000_0101 85: mul32 r5, c5, r5 0E23 : 1001_0000_0101_0110_1010_1101 86: mov 0xb07, r6 0E24 : 1100_0111_0110_0000_1110_0110 87: add r6, r5, r6 ; the IRQ7 address 0E25 : 1000_0010_0110_0000_1010_0110 88: sgio r0, r6 0E26 : 0010_0100_0000_0000_1100_0000 89: 90: mov 0xb0e, r6 0E27 : 1100_0111_0110_0001_1100_0110 91: add r6, r5, r6 ; the IRQHW address 0E28 : 1000_0010_0110_0000_1010_0110 92: mov b10000101, r0 ; the mask 0E29 : 1100_0110_0001_0000_1010_0000 93: nop ; enough nops 0E2A : 0000_0000_0000_0000_0000_0000 94: nop ; to ensure that 0E2B : 0000_0000_0000_0000_0000_0000 95: nop ; no CPU will wait 0E2C : 0000_0000_0000_0000_0000_0000 96: nop ; after writing to GIO 0E2D : 0000_0000_0000_0000_0000_0000 97: nop ; otherwise the CPUs 0E2E : 0000_0000_0000_0000_0000_0000 98: nop ; will be not synchronized! 0E2F : 0000_0000_0000_0000_0000_0000 99: jmpr cc_busy, 0 ; this should not happen! 0E30 : 0000_0101_1100_0110_0001_0111 100: sgio r0, r6 0E31 : 0010_0100_0000_0000_1100_0000 101: sti ; enable interrupts 0E32 : 0011_0000_0000_0000_0000_0000 102: jmpr cc_uncond, 0 ; and wait forever 0E33 : 0000_0101_1100_0110_0110_1111 103: 104: adc2cpu_sync: 105: 106: ; for debugging 107: #ifdef debug_adc2cpu 108: mov 0, r15 0E34 : 1100_0110_0000_0000_0000_1111 109: nop 0E35 : 0000_0000_0000_0000_0000_0000 110: sra+ r9 0E36 : 0011_1000_1001_0000_0000_0000 111: nop 0E37 : 0000_0000_0000_0000_0000_0000 112: sra+ r10 0E38 : 0011_1000_1010_0000_0000_0000 113: nop 0E39 : 0000_0000_0000_0000_0000_0000 114: sra+ r11 0E3A : 0011_1000_1011_0000_0000_0000 115: nop 0E3B : 0000_0000_0000_0000_0000_0000 116: sra+ r12 0E3C : 0011_1000_1100_0000_0000_0000 117: nop 0E3D : 0000_0000_0000_0000_0000_0000 118: sra+ r13 0E3E : 0011_1000_1101_0000_0000_0000 119: #endif 120: 121: ; here the CPUs are synchronized with the EOC (end of co 122: jmp cc_uncond, r8 ; jump to the proper routine 0E3F : 0000_1000_1000_0000_0000_1111 123: 124: adc2cpu_off: 125: mov 0, r0 0E40 : 1100_0110_0000_0000_0000_0000 126: mov clk_onoff, r1 0E41 : 1100_0111_0100_0100_1010_0001 127: sub r1, c1, r1 ; turn off permanently 0E42 : 1000_1010_0001_0110_0010_0001 128: sgio r0, r1 0E43 : 0010_0100_0000_0000_0010_0000 129: jmpr cc_uncond, 0 0E44 : 0000_0101_1100_1000_1000_1111 130: nop 0E45 : 0000_0000_0000_0000_0000_0000 131: 132: adc2cpu_2adc: 133: ; Read 2 ADC channels 134: ; here we have 135: 136: ; r10 is the start address in GIO 137: ; 138: ; r9 is mask for the address = 0xBFFF, ANDed after ea 139: ; 140: ; r11 is the number of words, decremented after GIO wr 141: ; exit if carry is set! 142: ; 143: ; r2 mask for the data = 0x3FF3FF 144: ; 145: ; r12 is the address of the ADC 146: ; 147: ; r13 is the address of the 2nd ADC 148: 149: ; instruction CPU clock 150: lpio r12, r0 ; 0 0E46 : 1110_0010_0000_0001_1000_0000 151: lpio r13, r0 ; 1 0E47 : 1110_0010_0000_0001_1010_0000 152: lpio r13, r1 ; 2 0E48 : 1110_0010_0000_0001_1010_0001 153: shl 12, r1, r1 ; 3 0E49 : 1011_0010_1100_0000_0010_0001 154: or r0, r1, r0 ; 4 0E4A : 1010_1010_0000_0000_0010_0000 155: and r0, r2, r0 ; 5 0E4B : 1010_0110_0000_0000_0100_0000 156: sgio r0, r10 ; 6 0E4C : 0010_0100_0000_0001_0100_0000 157: add r10, c1, r10 ; 7 write_address++ 0E4D : 1000_0010_1010_0110_0010_1010 158: and r10, r9, r10 ; 8 write_address & 0xBFFF 0E4E : 1010_0110_1010_0001_0010_1010 159: sub r11, c1, r11 ; 9 word_counter-- 0E4F : 1000_1010_1011_0110_0010_1011 160: jmp cc_ncarry, r8 ; 10 & 11 0E50 : 0000_1000_1000_0000_0000_0000 161: 162: jmp cc_uncond, adc2cpu_clear 0E51 : 0000_0100_0000_0000_0000_1111 163: 164: adc2cpu_1adc: 165: ; Read 1 ADC channel 166: ; here we have 167: 168: ; r10 is the start address in GIO 169: ; 170: ; r9 is mask for the address = 0xBFFF, ANDed after ea 171: ; 172: ; r11 is the number of words, decremented after GIO wr 173: ; exit if carry is set! 174: ; 175: ; r2 mask for the data = 0x3FF3FF 176: ; 177: ; r12 is the address of the 1st ADC 178: ; 179: lpio r12, r0 ; 0 0E52 : 1110_0010_0000_0001_1000_0000 180: lpio r12, r0 ; 1 0E53 : 1110_0010_0000_0001_1000_0000 181: nop ; 2 0E54 : 0000_0000_0000_0000_0000_0000 182: nop ; 3 0E55 : 0000_0000_0000_0000_0000_0000 183: nop ; 4 0E56 : 0000_0000_0000_0000_0000_0000 184: nop ; 5 0E57 : 0000_0000_0000_0000_0000_0000 185: nop ; 6 0E58 : 0000_0000_0000_0000_0000_0000 186: nop ; 7 0E59 : 0000_0000_0000_0000_0000_0000 187: nop ; 8 0E5A : 0000_0000_0000_0000_0000_0000 188: nop ; 9 0E5B : 0000_0000_0000_0000_0000_0000 189: nop ; 10 0E5C : 0000_0000_0000_0000_0000_0000 190: nop ; 11 0E5D : 0000_0000_0000_0000_0000_0000 191: lpio r12, r1 ; 0 0E5E : 1110_0010_0000_0001_1000_0001 192: lpio r12, r1 ; 1 0E5F : 1110_0010_0000_0001_1000_0001 193: shl 12, r1, r1 ; 2 0E60 : 1011_0010_1100_0000_0010_0001 194: or r1, r0, r0 ; 3 0E61 : 1010_1010_0001_0000_0000_0000 195: and r0, r2, r0 ; 4 0E62 : 1010_0110_0000_0000_0100_0000 196: sgio r0, r10 ; 5 0E63 : 0010_0100_0000_0001_0100_0000 197: add r10, c1, r10 ; 6 write_address++ 0E64 : 1000_0010_1010_0110_0010_1010 198: and r10, r9, r10 ; 7 write_address & 0xBFFF 0E65 : 1010_0110_1010_0001_0010_1010 199: sub r11, c1, r11 ; 8 word_counter-- 0E66 : 1000_1010_1011_0110_0010_1011 200: nop ; 9 0E67 : 0000_0000_0000_0000_0000_0000 201: jmp cc_ncarry, r8 ; 10 & 11 0E68 : 0000_1000_1000_0000_0000_0000 202: 203: jmp cc_uncond, adc2cpu_clear 0E69 : 0000_0100_0000_0000_0000_1111 204: 205: 206: adc2cpu_1dec: 207: ; Read 1 ADC channel 208: ; here we have 209: 210: ; r10 is the start address in GIO 211: ; 212: ; r9 is mask for the address = 0xBFFF, ANDed after ea 213: ; 214: ; r11 is the number of words, decremented after GIO wr 215: ; exit if carry is set! 216: ; 217: ; r2 mask for the data = 0x3FF3FF 218: ; r3 number of oversamples 219: ; 220: ; r12 is the address of the 1st ADC 221: ; 222: lpio r12, r0 ; 0 0E6A : 1110_0010_0000_0001_1000_0000 223: lpio r12, r0 ; 1 0E6B : 1110_0010_0000_0001_1000_0000 224: and r0, r2, r0 ; 2 mask 0E6C : 1010_0110_0000_0000_0100_0000 225: xor r0, r14, r0 ; 3 invert the MSB 0E6D : 1010_0010_0000_0001_1100_0000 226: add r0, r1, r1 ; 4 accumulate 0E6E : 1000_0010_0000_0000_0010_0001 227: sub r4, c1, r4 ; 5 loop counter-- 0E6F : 1000_1010_0100_0110_0010_0100 228: jmp cc_zero, adc2cpu_1dec_store ; 6 0E70 : 0000_0100_0000_0000_0001_0001 229: nop ; 7 0E71 : 0000_0000_0000_0000_0000_0000 230: nop ; 8 0E72 : 0000_0000_0000_0000_0000_0000 231: nop ; 9 0E73 : 0000_0000_0000_0000_0000_0000 232: jmp cc_uncond, r8 ; 10 & 11 0E74 : 0000_1000_1000_0000_0000_1111 233: 234: adc2cpu_1dec_store: 235: sgio r1, r10 ; 8 store 0E75 : 0010_0100_0001_0001_0100_0000 236: add r10, c1, r10 ; 9 write_address++ 0E76 : 1000_0010_1010_0110_0010_1010 237: and r10, r9, r10 ; 10 write_address & 0xBFFF 0E77 : 1010_0110_1010_0001_0010_1010 238: sub r11, c1, r11 ; 11 word_counter-- 0E78 : 1000_1010_1011_0110_0010_1011 239: jmp cc_carry, adc2cpu_clear ; 0 0E79 : 0000_0100_0000_0000_0001_0000 240: 241: ; first sample in the loop 242: lpio r12, r0 ; 1 0E7A : 1110_0010_0000_0001_1000_0000 243: lpio r12, r0 ; 2 0E7B : 1110_0010_0000_0001_1000_0000 244: and r0, r2, r0 ; 3 mask & accumulate 0E7C : 1010_0110_0000_0000_0100_0000 245: xor r0, r14, r1 ; 4 invert the MSB 0E7D : 1010_0010_0000_0001_1100_0001 246: mov r3, r4 ; 5 the oversampling counter 0E7E : 1100_0010_0000_0000_0110_0100 247: sub r4, c1, r4 ; 6 loop counter-- 0E7F : 1000_1010_0100_0110_0010_0100 248: jmp cc_zero, adc2cpu_1dec_store ; 7 0E80 : 0000_0100_0000_0000_0001_0001 249: nop ; 8 0E81 : 0000_0000_0000_0000_0000_0000 250: nop ; 9 0E82 : 0000_0000_0000_0000_0000_0000 251: jmp cc_uncond, r8 ; 10 & 11 0E83 : 0000_1000_1000_0000_0000_1111 252: 253: adc2cpu_clear: 254: ; for debugging 255: #ifdef debug_adc2cpu 256: sra+ r10 0E84 : 0011_1000_1010_0000_0000_0000 257: nop 0E85 : 0000_0000_0000_0000_0000_0000 258: sra+ r11 0E86 : 0011_1000_1011_0000_0000_0000 259: #endif 260: cli; 0E87 : 0010_1100_0000_0000_0000_0000 261: mov b00000101, r1 ; restore the mask 0E88 : 1100_0110_0000_0000_1010_0001 262: jmpr cc_busy, 0 0E89 : 0000_0101_1101_0001_0011_0111 263: sgio r1, r6 0E8A : 0010_0100_0001_0000_1100_0000 264: mov 0x412, r0 ; code for clear 0E8B : 1100_0110_1000_0010_0100_0000 265: jmpr cc_busy, 0 0E8C : 0000_0101_1101_0001_1001_0111 266: sgio r0, SMCMD ; send clear 0E8D : 0010_1000_0000_1010_0000_0100 267: jmp cc_uncond, clr_endloop 0E8E : 0000_0100_0000_0000_0000_1111 268: nop 0E8F : 0000_0000_0000_0000_0000_0000 *** End of include file SRC/adc2cpu.asm 2269: 2270: 2271: org 0xFFE 2272: jmp cc_uncond, lpw2 0FFE : 0000_0100_0000_0000_0000_1111 2273: jmp cc_uncond, lpw2 0FFF : 0000_0100_0000_0000_0000_1111 Source file read, 0 error(s), 0 warning(s).