// 1-pretrigger, 2-clear, 3-reserved, 4-low power, 5-acq, 6-test, 7-pasa pulse
// go to acq
include SRC/scsn_ids.tcs
include SRC/defines.tcs
include SRC/parameters.tcs
write ADCPAR, adc_power_backgr | (0 << 3) | (adc_enibf_backgr << 4) | (adc_power_pretr << 5) | (1 << 8) | (adc_enibf_pretr << 9) | (adc_smp_phase << 10) | (adc_irq_phase << 14);
// wait 200
// pretrigger 5
// wait 10
// // trigger
// pretrigger 1
// // read status
// wait 200
// read chip_hm, 0x0A04
// read chip_bm, 0x0A04
// read chip2  , 0x0A04
// write           C11CPU3, 0; // const11, delay ni not necessary if no data
// wait 100
// // clear
// // 1-pretrigger, 2-clear, 3-reserved, 4-low power, 5-acq, 6-test, 7-pasa pulse
// pretrigger 2
// wait 10
// pretrigger 1
// read chip_hm, 0x0A04
// read chip_bm, 0x0A04
// read chip2  , 0x0A04