Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.3, Apr 2004 Please send any comments to: angelov@kip.uni-heidelberg.de 17:00:37 / 21 Sep 2006 Source code file: src/fitred.asm Memory initialisation file: Log file: wrk/cpu3.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU3 = 2 CC_SIGNED = 0X14 3 CC_NSIGNED = 0X04 4 CC_ZERO = 0X11 5 CC_NZERO = 0X01 6 CC_OVERFL = 0X13 7 CC_NOVERFL = 0X03 8 CC_NEG = 0X12 9 CC_NNEG = 0X02 10 CC_CARRY = 0X10 11 CC_NCARRY = 0X00 12 CC_BUSY = 0X17 13 CC_NBUSY = 0X07 14 CC_DIVB = 0X15 15 CC_NDIVB = 0X05 16 CC_ERRDIV = 0X16 17 CC_NERRDIV = 0X06 18 CC_UNCOND = 0X0F 19 CC_EQ = 0X11 20 CC_NEQ = 0X01 21 CC_NEG = 0X12 22 CC_POS0 = 0X02 23 CC_LTS = 0X14 24 CC_GES = 0X04 25 CC_LTU = 0X10 26 CC_GEU = 0X00 27 CC_LES = 0X19 28 CC_GTS = 0X09 29 CC_LEU = 0X18 30 CC_GTU = 0X08 31 RR_BYTE = 3 32 RR_WORD = 1 33 RR_DWORD = 0 34 LRA1 = LRA 3, 35 LRA2 = LRA 1, 36 LRA4 = LRA 0, 37 LRA4+ = LRA+ 0, 38 XOR = EOR 39 NOT = COM 40 SHLT = SHL 41 ANDT = AND 42 R0 = PRF[0] 43 R1 = PRF[1] 44 R2 = PRF[2] 45 R3 = PRF[3] 46 R4 = PRF[4] 47 R5 = PRF[5] 48 R6 = PRF[6] 49 R7 = PRF[7] 50 R8 = PRF[8] 51 R9 = PRF[9] 52 R10 = PRF[10] 53 R11 = PRF[11] 54 R12 = PRF[12] 55 R13 = PRF[13] 56 R14 = PRF[14] 57 R15 = PRF[15] 58 G0 = GRF[0] 59 G1 = GRF[1] 60 G2 = GRF[2] 61 G3 = GRF[3] 62 G4 = GRF[4] 63 G5 = GRF[5] 64 G6 = GRF[6] 65 G7 = GRF[7] 66 G8 = GRF[8] 67 G9 = GRF[9] 68 G10 = GRF[10] 69 G11 = GRF[11] 70 G12 = GRF[12] 71 G13 = GRF[13] 72 G14 = GRF[14] 73 G15 = GRF[15] 74 F0 = FIT[0] 75 F1 = FIT[1] 76 F2 = FIT[2] 77 F3 = FIT[3] 78 F4 = FIT[4] 79 F5 = FIT[5] 80 F6 = FIT[6] 81 F7 = FIT[7] 82 F8 = FIT[8] 83 F9 = FIT[9] 84 F10 = FIT[10] 85 F11 = FIT[11] 86 F12 = FIT[12] 87 F13 = FIT[13] 88 F14 = FIT[14] 89 F15 = FIT[15] 90 C0 = CON[0] 91 C1 = CON[1] 92 C2 = CON[2] 93 C3 = CON[3] 94 C4 = CON[4] 95 C5 = CON[5] 96 C6 = CON[6] 97 C7 = CON[7] 98 C8 = CON[8] 99 C9 = CON[9] 100 C10 = CON[10] 101 C11 = CON[11] 102 C12 = CON[12] 103 C13 = CON[13] 104 C14 = CON[14] 105 C15 = CON[15] 1: ;################################################# 2: ;# 3: ;# Rudimentary Readout Program for TRAP3 chip 4: ;# 5: ;# Marcus Gutfleisch 6: ;# Universitaet Heidelberg, Kirchhoff-Institut fue 7: ;# 8: ;# -- last modified: 17:01 / 31-Jan-2006 / V.Angel 9: ;# 10: ;################################################# 11: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 31: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 32: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 33: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 34: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 35: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 36: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 37: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 38: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 39: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 40: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 41: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 42: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 43: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 44: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 45: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 46: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 47: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 48: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 49: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 50: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 51: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 52: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 53: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 54: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 55: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 56: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 57: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 58: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 59: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 60: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 61: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 62: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 63: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 64: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 65: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 66: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 67: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 68: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 69: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 70: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 71: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 72: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 73: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 74: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 75: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 76: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 77: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 78: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 79: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 80: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 81: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 82: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 83: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 84: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 85: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 86: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 87: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 88: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 89: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 90: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 91: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 92: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 93: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 94: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 95: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 96: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 97: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 98: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 99: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 100: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 101: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 102: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 103: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 104: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 105: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 106: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 107: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 108: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 109: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 110: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 111: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 112: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 113: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 114: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 115: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 116: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 117: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 118: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 119: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 120: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 121: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 122: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 123: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 124: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 125: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 126: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 127: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 128: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 129: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 130: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 131: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 132: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 133: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 134: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 135: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 136: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 137: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 138: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 139: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 140: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 141: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 142: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 143: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 144: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 145: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 146: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 147: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 148: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 149: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 150: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 151: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 152: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 153: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 154: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 155: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 156: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 157: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 158: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 159: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 160: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 161: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 162: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 163: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 164: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 165: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 166: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 167: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 168: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 169: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 170: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 171: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 172: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 173: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 174: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 175: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 176: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 177: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 178: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 179: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 180: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 181: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 182: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 183: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 184: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 185: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 186: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 187: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 188: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 189: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 190: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 191: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 192: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 193: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 194: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 195: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 196: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 197: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 198: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 199: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 200: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 201: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 202: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 203: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 204: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 205: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 206: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 207: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 208: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 209: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 210: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- 211: #def GBUSR0=0x0300; -- readonly 212: #def GBUSR1=0x0301; -- readonly 213: *** End of include file /cad/tools/bin/conf_va.inc 13: 14: ; define this parameter in order to sent testpatte 15: ;#def testmode = 1 16: 17: ; define this parameter to run the raw program fir 18: ; This helps only to limit the max current, but ta 19: ;#def raw_cpu_pair = 1 20: ;################################################# 21: ;# 22: ;# defines 23: ;# 24: ;################################################# 25: ; for I2C and JTAG 26: #def srv_command = 0xF0E0 27: #def srv_indata = 0xF0E1 28: #def srv_outdata = 0xF0F0 29: 30: #def endsig_tr = g14 ; end 31: #def endsig_rr = g15 ; end 32: #def nsamples = c13 ; numb 33: #def ChipPOS = c14 ; Chip 34: #def CHIP_ID_EXT = c14 ; Chip 35: #def EventHeader = c9 ; Read 36: #def EHchip = 0xfff ; Even 37: #def EventCounter = c12 ; even 38: #def EvtCtrGIOAdr = 0xC04 ; Addr 39: #def NI_tmsn_delay = c11 ; prog 40: #def ReadoutFlag = c15 ; bit1 41: ; bit0 42: ; bit2 43: 44: #def rstack = r8 ; prog 45: #def rio = r14 ; loca 46: 47: #ifdef cpu0 48: #def clk_onoff = CPU0SS ; own 49: #def clk_onoff_next = CPU2SS ; for 50: #def LSBdata = 0x03 ; LSBs 51: #def AddrSCdata = 0xF000 ; Addr 52: #def lpcount0 = 0xF03C ; coun 53: #def lpcount1 = 0xF07C ; coun 54: #endif 55: 56: #ifdef cpu1 57: #def clk_onoff = CPU1SS ; own 58: #def clk_onoff_next = CPU3SS ; for 59: #def LSBdata = 0x02 ; LSBs 60: #def AddrSCdata = 0xF040 ; Addr 61: #def lpcount0 = 0xF03D ; coun 62: #def lpcount1 = 0xF07D ; coun 63: #endif 64: 65: #ifdef cpu2 66: #def clk_onoff = CPU2SS ; own 67: #def LSBdata = 0x03 ; LSBs 68: #def AddrSCdata = 0xF080 ; Addr 69: #def lpcount0 = 0xF03E ; coun 70: #def lpcount1 = 0xF07E ; coun 71: #endif 72: 73: #ifdef cpu3 74: #def clk_onoff = CPU3SS ; own 75: #def LSBdata = 0x02 ; LSBs 76: #def AddrSCdata = 0xF0C0 ; Addr 77: #def lpcount0 = 0xF03F ; coun 78: #def lpcount1 = 0xF07F ; coun 79: #endif 80: 81: 82: ;################################################# 83: ;# 84: ;# 0x000: Infinite Loop at Instruction Memory Rese 85: ;# 86: ;################################################# 87: 88: ORG 0x0; 89: lpw: 90: nop 0000 : 0000_0000_0000_0000_0000_0000 91: nop 0001 : 0000_0000_0000_0000_0000_0000 92: nop 0002 : 0000_0000_0000_0000_0000_0000 93: ; ; low power 94: ; mov 0, r0 95: ; sgio r0, clk_onoff 96: 97: iext lpcount0 0003 : 0101_0000_0000_0000_0000_1111 98: lgio 0, lpcount0 0004 : 1110_1100_1111_0000_0011_1111 99: jmpr cc_busy, 0 0005 : 0000_0100_0000_0000_1011_0111 100: lpio GBUSR0, r1 0006 : 1110_0110_0110_0000_0000_0001 101: add r1, c1, r1 0007 : 1000_0010_0001_0110_0010_0001 102: iext lpcount0 0008 : 0101_0000_0000_0000_0000_1111 103: sgio r1, lpcount0 0009 : 0010_1000_0001_0000_0011_1111 104: jmpr cc_uncond, 0 000A : 0000_0100_0000_0001_0100_1111 105: nop 000B : 0000_0000_0000_0000_0000_0000 106: 107: lpw2: 108: nop 000C : 0000_0000_0000_0000_0000_0000 109: nop 000D : 0000_0000_0000_0000_0000_0000 110: iext lpcount1 000E : 0101_0000_0000_0000_0000_1111 111: lgio 0, lpcount1 000F : 1110_1100_1111_0000_0111_1111 112: jmpr cc_busy, 0 0010 : 0000_0100_0000_0010_0001_0111 113: lpio GBUSR0, r1 0011 : 1110_0110_0110_0000_0000_0001 114: add r1, c1, r1 0012 : 1000_0010_0001_0110_0010_0001 115: iext lpcount1 0013 : 0101_0000_0000_0000_0000_1111 116: sgio r1, lpcount1 0014 : 0010_1000_0001_0000_0111_1111 117: jmpr cc_uncond, 0 0015 : 0000_0100_0000_0010_1010_1111 118: nop 0016 : 0000_0000_0000_0000_0000_0000 119: 120: 121: ;################################################# 122: ;# 123: ;# 0x100: Interrupt Clear Jump Address 124: ;# 125: ;################################################# 126: 127: ORG 0x100; 128: 129: clr: 130: mov 0, r12 0100 : 1100_0110_0000_0000_0000_1100 131: mov 4, r13 0101 : 1100_0110_0000_0000_1000_1101 132: 133: #ifdef cpu0 134: iext b1111_0101_0000_0000_0010_0000; 135: mov b1111_0101_0000_0000_0010_0000, r1 136: jmpr cc_busy, 0 137: sgio r1, SMOFFON ; switch off all NI LVDS 138: nop 139: nop 140: nop 141: nop 142: #endif 143: 144: #ifdef cpu1 145: ; copy the end signature words NES into GRF 146: lgio 0, NES 147: iext 0xFFFF 148: mov 0xFFFF, r1 149: jmpr cc_busy, 0 150: lpio 0x300, r2 151: and r1, r2, endsig_tr 152: swp r2, r2 153: and r1, r2, endsig_rr 154: #endif 155: 156: #ifdef cpu2 157: nop 158: nop 159: nop 160: nop 161: nop 162: nop 163: nop 164: nop 165: #endif 166: 167: #ifdef cpu3 168: ; exit from clear state 169: nop 0102 : 0000_0000_0000_0000_0000_0000 170: nop 0103 : 0000_0000_0000_0000_0000_0000 171: nop 0104 : 0000_0000_0000_0000_0000_0000 172: nop 0105 : 0000_0000_0000_0000_0000_0000 173: lgio 0, NES 0106 : 1110_1100_0000_1101_0100_0101 174: jmpr cc_busy, 0; here just to be sure cpu3 wai 0107 : 0000_0100_0010_0000_1111_0111 175: mov cmd_ext_clr, r0 0108 : 1100_0110_0110_0010_0100_0000 176: sgio r0, SMCMD ; clear ready (VA) 0109 : 0010_1000_0000_1010_0000_0100 177: #endif 178: 179: jmpr cc_uncond, 0 010A : 0000_0100_0010_0001_0100_1111 180: nop 010B : 0000_0000_0000_0000_0000_0000 181: 182: 183: ;################################################# 184: ;# 185: ;# 0x200: Interrupt Tracklet Processing Jump Addre 186: ;# 187: ;################################################# 188: 189: ORG 0x200; 190: 191: acq: 192: #ifdef cpu0 193: mov b0000_0010_0000, r1 194: jmpr cc_busy, 0 195: sgio r1, SMOFF ; switch off clk_f 196: mov 1, g0 ; should be moved 197: #else 198: nop ; could be omitted 0200 : 0000_0000_0000_0000_0000_0000 199: nop 0201 : 0000_0000_0000_0000_0000_0000 200: nop 0202 : 0000_0000_0000_0000_0000_0000 201: nop 0203 : 0000_0000_0000_0000_0000_0000 202: #endif 203: 204: ;################################# 205: ;# 206: ;# check for tracklets: CHANN 207: ;# 208: ;################################# 209: 210: shl 10, f8, r8 ; ( CHANNE 0204 : 1011_0010_1010_0101_0000_1000 211: ; to guara 212: 213: ; jmp cc_uncond, acq_no_tr ; skip t 214: jmp cc_zero, acq_no_tr ; if CHANN 0205 : 0000_0100_0000_0000_0001_0001 215: 216: ;################################# 217: ;# 218: ;# fit parameter calculation 219: ;# 220: ;# SLOPE = ( N * XY - X * Y ) 221: ;# OFFSET = ( XX * Y - X * XY 222: ;# 223: ;################################# 224: 225: add f1, f9, r15 ; N = N0 0206 : 1000_0011_0001_0101_0010_1111 226: add f3, f11, r1 ; X = X0 0207 : 1000_0011_0011_0101_0110_0001 227: mul32 r1, r1, r3 ; X * 0208 : 1001_0000_0001_0000_0010_1011 228: add f4, f12, r2 ; XX = XX0 0209 : 1000_0011_0100_0101_1000_0010 229: mul32 r15, r2, r4 ; N * 020A : 1001_0000_1111_0000_0100_1100 230: add f2, f10, r7 ; Q = Q0 020B : 1000_0011_0010_0101_0100_0111 231: sub r4, r3, r3 ; N * 020C : 1000_1010_0100_0000_0110_0011 232: 233: ; r12 = 0 234: ; r13 = 4 235: 236: div r12, r3 ; 2**34 / 020D : 1001_1000_1100_0000_0110_0000 237: 238: shl 8, f9, r5 ; 256 020E : 1011_0010_1000_0101_0010_0101 239: add f13, r5, r5 ; Y1 020F : 1000_0011_1101_0000_1010_0101 240: add f5, r5, r5 ; Y = Y0 0210 : 1000_0011_0101_0000_1010_0101 241: 242: shl 8, f11, r6 ; 256 0211 : 1011_0010_1000_0101_0110_0110 243: add f14, r6, r6 ; XY1 0212 : 1000_0011_1110_0000_1100_0110 244: add f6, r6, r6 ; XY = XY0 0213 : 1000_0011_0110_0000_1100_0110 245: 246: mus32 r1, r5, r3 ; X * 0214 : 1001_0100_0001_0000_1010_1011 247: mus32 r1, r6, r4 ; X * 0215 : 1001_0100_0001_0000_1100_1100 248: mus32 r2, r5, r1 ; XX 0216 : 1001_0100_0010_0000_1010_1001 249: mus32 r15, r6, r2 ; N * 0217 : 1001_0100_1111_0000_1100_1010 250: 251: sub r1, r4, r1 ; OF = XX 0218 : 1000_1010_0001_0000_1000_0001 252: sub r2, r3, r2 ; SL = N * 0219 : 1000_1010_0010_0000_0110_0010 253: 254: shl 2, r15, r15 ; byt 021A : 1011_0010_0010_0001_1110_1111 255: 256: ; QA = low 257: shl -16, r7, r4 ; QB = hig 021B : 1011_0011_0000_0000_1110_0100 258: 259: lra rr_dword, r0 ; 2** 021C : 1101_0010_0000_0000_0000_0000 260: lra rr_dword, r0 ; 2** 021D : 1101_0010_0000_0000_0000_0000 261: 262: mul r0, r4, r0 ; QB * 2** 021E : 1001_0000_0000_0000_1000_0000 263: mov 0x1F, r6 ; do somet 021F : 1100_0110_0000_0011_1110_0110 264: 265: and r13, r6, r6 ; QB * 2** 0220 : 1010_0110_1101_0000_1100_0110 266: ; QB / N > 267: shl 7, r6, r6 ; E.PROBAB 0221 : 1011_0010_0111_0000_1100_0110 268: or r6, CHIP_ID_EXT, r6 ; E.PROBAB 0222 : 1010_1010_0110_0111_1100_0110 269: 270: die r7 ; get 2**3 0223 : 1001_1110_0000_0000_0000_0111 271: 272: mus r7, r1, r1 ; lower 32 0224 : 1001_0100_0111_0000_0010_0001 273: mus r7, r2, r2 ; lower 32 0225 : 1001_0100_0111_0000_0100_0010 274: 275: add r8, r13, r1 ; OFFSET [ 0226 : 1000_0010_1000_0001_1010_0001 276: shl 11, r13, r2 ; SLOPE [ 0227 : 1011_0010_1011_0001_1010_0010 277: 278: ;################################# 279: ;# 280: ;# tracklet synthesis and tra 281: ;# 282: ;# SLOPE [9] *1 283: ;# & OFFSET [11] *6 284: ;# & E.PROBABILITY [5] /3 285: ;# & CHIP ID [7] 286: ;# 287: ;################################# 288: 289: shl -4, r1, r1 ; OFFSET [ 0228 : 1011_0011_1100_0000_0010_0001 290: or r1, r2, r5 ; SLOPE & 0229 : 1010_1010_0001_0000_0100_0101 291: shl 12, r5, r5 ; SLOPE & 022A : 1011_0010_1100_0000_1010_0101 292: or r5, r6, r5 ; SLOPE & 022B : 1010_1010_0101_0000_1100_0101 293: 294: mov 23, r1 ; delay tr 022C : 1100_0110_0000_0010_1110_0001 295: 296: acq_tr_del: 297: sub r1, c1, r1 022D : 1000_1010_0001_0110_0010_0001 298: jmp cc_nzero, acq_tr_del 022E : 0000_0100_0000_0000_0000_0001 299: 300: spio r5, NODP 022F : 0010_0000_0101_0000_0000_0000 301: 302: jmpr cc_uncond, 0 0230 : 0000_0100_0100_0110_0000_1111 303: nop 0231 : 0000_0000_0000_0000_0000_0000 304: 305: ;################################# 306: ;# 307: ;# send end signature if ther 308: ;# 309: ;# do any power management he 310: ;# 311: ;################################# 312: 313: acq_no_tr: 314: mov 24, r1 ; delay tr 0232 : 1100_0110_0000_0011_0000_0001 315: mov r1, r5 0233 : 1100_0010_0000_0000_0010_0101 316: acq_nt_del: 317: mul r5, r1, r5; more power - more pesi 0234 : 1001_0000_0101_0000_0010_0101 318: sub r1, c1, r1 0235 : 1000_1010_0001_0110_0010_0001 319: jmp cc_nzero, acq_nt_del 0236 : 0000_0100_0000_0000_0000_0001 320: mov endsig_tr, r5 0237 : 1100_0010_0000_0011_1100_0101 321: 322: spio r5, NODP 0238 : 0010_0000_0101_0000_0000_0000 323: 324: jmpr cc_uncond, 0 0239 : 0000_0100_0100_0111_0010_1111 325: nop 023A : 0000_0000_0000_0000_0000_0000 326: 327: 328: ;################################################# 329: ;# 330: ;# 0x400: Interrupt Raw Data Transmission Jump Add 331: ;# 332: ;################################################# 333: 334: ORG 0x400 335: 336: raw: 337: 338: #ifdef cpu0 339: mov cmd_CPU_done r0 ; CPU0 indicat 340: jmpr cc_busy, 0 341: sgio r0 SMCMD; 342: jmp cc_uncond, raw_continue ; CPU0 fills F 343: #endif 344: 345: #ifdef cpu1 346: nop 347: nop 348: nop 349: jmp cc_uncond, raw_continue ; CPU1 fills F 350: #endif 351: 352: #ifdef cpu2 353: nop 354: nop 355: nop 356: nop 357: #endif 358: 359: #ifdef cpu3 360: nop 0400 : 0000_0000_0000_0000_0000_0000 361: nop 0401 : 0000_0000_0000_0000_0000_0000 362: nop 0402 : 0000_0000_0000_0000_0000_0000 363: nop 0403 : 0000_0000_0000_0000_0000_0000 364: #endif 365: 366: #ifdef raw_cpu_pair 367: mov 0, r0 ; switch off o 368: jmpr cc_busy, 0 369: sgio r0, clk_onoff ; CPU2 and CPU 370: jmpr cc_busy, 0 ; They will be 371: 372: nop 373: nop 374: nop 375: nop 376: 377: nop 378: nop 379: nop 380: nop 381: #endif 382: 383: raw_continue: 384: 385: ;############################################## 386: ;# Store Start addresses for SCSN transfer via D 387: ;############################################## 388: 389: iext AddrSCdata 0404 : 0101_0000_0000_0000_0000_1111 390: mov AddrSCdata, rio 0405 : 1100_0110_0001_1000_0000_1110 391: 392: ;############################################## 393: ;# NI transfer event header (CPU0 only) 394: ;############################################## 395: 396: #ifdef cpu0 397: ; Note: this is normally not used!!! 398: mov EHchip, r0 ; chip EHchip star 399: cmp r0, ChipPOS ; and sends event 400: jmp cc_nzero, raw_no_event_header 401: 402: shl 2, EventHeader, r0 ; combine event he 403: or r0, c1, r0 ; SOE+"01"+SOE+"01 404: shl 15, r0, r1 ; where SOE is the 405: shl 1, r1, r1 406: or r0, r1, r0 407: 408: spio r0 NODP ; NI transfer even 409: jmpr cc_busy, 0 ; SCSN transfer ch 410: sgio+ r0 411: 412: #else 413: 414: nop 0406 : 0000_0000_0000_0000_0000_0000 415: nop 0407 : 0000_0000_0000_0000_0000_0000 416: nop 0408 : 0000_0000_0000_0000_0000_0000 417: nop 0409 : 0000_0000_0000_0000_0000_0000 418: nop 040A : 0000_0000_0000_0000_0000_0000 419: nop 040B : 0000_0000_0000_0000_0000_0000 420: nop 040C : 0000_0000_0000_0000_0000_0000 421: nop 040D : 0000_0000_0000_0000_0000_0000 422: nop 040E : 0000_0000_0000_0000_0000_0000 423: nop 040F : 0000_0000_0000_0000_0000_0000 424: nop 0410 : 0000_0000_0000_0000_0000_0000 425: 426: #endif 427: 428: raw_no_event_header: 429: 430: 431: mov ReadoutFlag, r2 ; load NI&SCSN rea 0411 : 1100_0010_0000_0111_1110_0010 432: ; cmp r2, 0 433: ; jmp cc_zero, raw_del_end ; check for transm 434: 435: #ifdef cpu0 436: 437: shlt -3, r2 ; move bit 2 to C 438: jmp cc_ncarry, raw_no_2nd_header ; bit 2=1 me 439: shl -8, r2, r0 ; the header itself is 440: shl 8, r0, r0 ; mask the lower 8 bit 441: or r0, c1, r0 ; and set bit 0 442: spio r0 NODP ; NI transfer chip hea 443: sgio+ r0 444: #else 445: 446: nop 0412 : 0000_0000_0000_0000_0000_0000 447: nop 0413 : 0000_0000_0000_0000_0000_0000 448: nop 0414 : 0000_0000_0000_0000_0000_0000 449: nop 0415 : 0000_0000_0000_0000_0000_0000 450: nop 0416 : 0000_0000_0000_0000_0000_0000 451: nop 0417 : 0000_0000_0000_0000_0000_0000 452: nop 0418 : 0000_0000_0000_0000_0000_0000 453: #endif 454: 455: raw_no_2nd_header: 456: swp rio, rio ; swap DBANK addre 0419 : 0111_1010_0000_0001_1100_1110 457: andt r2, c3 041A : 1010_0100_0010_0110_0110_0000 458: jmp cc_zero, raw_del_end ; check for transm 041B : 0000_0100_0000_0000_0001_0001 459: 460: #ifdef cpu0 461: shl 15, ChipPOS, r0 ; combine chip header 462: shl 5, r0, r0 ; ChipPOS(8)+EventCoun 463: or r0, EventCounter, r0 464: shl 2, r0, r0 465: or r0, c3, r0 466: shl 2, r0, r0 467: 468: spio r0 NODP ; NI transfer chip hea 469: swp rio, rio 470: jmpr cc_busy, 0 ; SCSN transfer chip h 471: sgio+ r0 ; no busy flag check d 472: swp rio, rio ; till next access 473: 474: #else 475: 476: nop 041C : 0000_0000_0000_0000_0000_0000 477: nop 041D : 0000_0000_0000_0000_0000_0000 478: nop 041E : 0000_0000_0000_0000_0000_0000 479: nop 041F : 0000_0000_0000_0000_0000_0000 480: nop 0420 : 0000_0000_0000_0000_0000_0000 481: nop 0421 : 0000_0000_0000_0000_0000_0000 482: nop 0422 : 0000_0000_0000_0000_0000_0000 483: nop 0423 : 0000_0000_0000_0000_0000_0000 484: nop 0424 : 0000_0000_0000_0000_0000_0000 485: nop 0425 : 0000_0000_0000_0000_0000_0000 486: nop 0426 : 0000_0000_0000_0000_0000_0000 487: nop 0427 : 0000_0000_0000_0000_0000_0000 488: 489: #endif 490: 491: mov LSBdata, r7 ; pass the two LSB 0428 : 1100_0110_0000_0000_0100_0111 492: 493: iext 0xFFFF0000 ; high word mask f 0429 : 0101_0001_1111_1111_1111_0000 494: mov 0xFFFF0000, r15 ; Note: this works 042A : 1100_0110_0000_0000_0000_1111 495: 496: mov g0, r0 042B : 1100_0010_0000_0010_0000_0000 497: cmp r0, 0 042C : 1100_1000_0000_0000_0000_0000 498: jmp cc_eq, raw_del_end 042D : 0000_0100_0000_0000_0001_0001 499: 500: mov nsamples, r1 ; initially load n 042E : 1100_0010_0000_0111_1010_0001 501: cmp r1, 0 042F : 1100_1000_0001_0000_0000_0000 502: jmp cc_nzero, raw_run_tmsn ; check for tr 0430 : 0000_0100_0000_0000_0000_0001 503: 504: raw_del_end: 505: mov 0x002, r2 ; wait a while to 0431 : 1100_0110_0000_0000_0100_0010 506: raw_no_tmsn_del: ; NI are ready for 507: sub r2, c1, r2 ; transition. 0432 : 1000_1010_0010_0110_0010_0010 508: jmp cc_nzero, raw_no_tmsn_del 0433 : 0000_0100_0000_0000_0000_0001 509: 510: nop 0434 : 0000_0000_0000_0000_0000_0000 511: jmp cc_uncond, raw_complete_ni_tmsn 0435 : 0000_0100_0000_0000_0000_1111 512: nop 0436 : 0000_0000_0000_0000_0000_0000 513: 514: raw_run_tmsn: 515: 516: 517: ;############################################## 518: ;# NI&SCSN transfer 1st channel 519: ;############################################## 520: 521: mov EBR0, r0 ; address in LIO o 0437 : 1100_0111_0000_0000_0000_0000 522: or r0, rio, rio ; to low word of r 0438 : 1010_1010_0000_0001_1100_1110 523: ; mov nsamples,r1 ; number of sample 524: mvpcr +2, rstack 0439 : 1100_0110_1000_0111_0110_1000 525: jmp cc_uncond, raw_ChTML; 043A : 0000_0100_0000_0000_0000_1111 526: 527: 528: ;############################################## 529: ;# NI&SCSN transfer 2nd channel 530: ;############################################## 531: 532: and r15, rio, rio 043B : 1010_0110_1111_0001_1100_1110 533: mov EBR1, r0 ; address in LIO o 043C : 1100_0111_0000_1000_0000_0000 534: or r0, rio, rio ; to low word of r 043D : 1010_1010_0000_0001_1100_1110 535: mov nsamples,r1 ; number of sample 043E : 1100_0010_0000_0111_1010_0001 536: mvpcr +2, rstack 043F : 1100_0110_1000_1000_0010_1000 537: jmp cc_uncond, raw_ChTML; 0440 : 0000_0100_0000_0000_0000_1111 538: 539: 540: ;############################################## 541: ;# NI&SCSN transfer 3rd channel 542: ;############################################## 543: 544: and r15, rio, rio 0441 : 1010_0110_1111_0001_1100_1110 545: mov EBR2, r0 ; address in LIO o 0442 : 1100_0111_0001_0000_0000_0000 546: or r0, rio, rio ; to low word of r 0443 : 1010_1010_0000_0001_1100_1110 547: mov nsamples,r1 ; number of sample 0444 : 1100_0010_0000_0111_1010_0001 548: mvpcr +2, rstack 0445 : 1100_0110_1000_1000_1110_1000 549: jmp cc_uncond, raw_ChTML; 0446 : 0000_0100_0000_0000_0000_1111 550: 551: 552: ;############################################## 553: ;# NI&SCSN transfer 4th channel 554: ;############################################## 555: 556: and r15, rio, rio 0447 : 1010_0110_1111_0001_1100_1110 557: mov EBR3, r0 ; address in LIO o 0448 : 1100_0111_0001_1000_0000_0000 558: or r0, rio, rio ; to low word of r 0449 : 1010_1010_0000_0001_1100_1110 559: mov nsamples,r1 ; number of sample 044A : 1100_0010_0000_0111_1010_0001 560: mvpcr +2, rstack 044B : 1100_0110_1000_1001_1010_1000 561: jmp cc_uncond, raw_ChTML; 044C : 0000_0100_0000_0000_0000_1111 562: 563: 564: ;############################################## 565: ;# NI&SCSN transfer 5th channel 566: ;############################################## 567: 568: and r15, rio, rio 044D : 1010_0110_1111_0001_1100_1110 569: mov EBR4, r0 ; address in LIO o 044E : 1100_0111_0010_0000_0000_0000 570: or r0, rio, rio ; to low word of r 044F : 1010_1010_0000_0001_1100_1110 571: mov nsamples,r1 ; number of sample 0450 : 1100_0010_0000_0111_1010_0001 572: mvpcr +2, rstack 0451 : 1100_0110_1000_1010_0110_1000 573: jmp cc_uncond, raw_ChTML; 0452 : 0000_0100_0000_0000_0000_1111 574: 575: 576: ;############################################## 577: ;# NI&SCSN transfer 6th channel (CPU3 only) 578: ;############################################## 579: 580: #ifdef cpu3 581: and r15, rio, rio 0453 : 1010_0110_1111_0001_1100_1110 582: mov EBR5, r0 ; address in LIO o 0454 : 1100_0111_0010_1000_0000_0000 583: or r0, rio, rio ; to low word of r 0455 : 1010_1010_0000_0001_1100_1110 584: mov nsamples,r1 ; number of sample 0456 : 1100_0010_0000_0111_1010_0001 585: mvpcr +2, rstack 0457 : 1100_0110_1000_1011_0010_1000 586: jmp cc_uncond, raw_ChTML; 0458 : 0000_0100_0000_0000_0000_1111 587: #else 588: nop 589: nop 590: nop 591: nop 592: nop 593: nop 594: #endif; 595: 596: 597: ;############################################## 598: ;# Slow down NI transmission if NI_tmsn_delay != 599: ;############################################## 600: 601: raw_complete_ni_tmsn: 602: nop 0459 : 0000_0000_0000_0000_0000_0000 603: 604: #ifdef cpu3 605: 606: mov NI_tmsn_delay, r1 ; mov does 045A : 1100_0010_0000_0111_0110_0001 607: andt r1, r1 045B : 1010_0100_0001_0000_0010_0000 608: jmp cc_zero, raw_end_ni_tmsn 045C : 0000_0100_0000_0000_0001_0001 609: cli 045D : 0010_1100_0000_0000_0000_0000 610: lgio 0, IRQHW3 045E : 1110_1100_0000_1011_0110_1110 611: jmpr cc_busy, 0 045F : 0000_0100_1000_1011_1111_0111 612: lpio 0x300, r8 0460 : 1110_0110_0110_0000_0000_1000 613: ; mov 0x015, r8 ; the pre 614: mov 0x415, r0 ; the new 0461 : 1100_0110_1000_0010_1010_0000 615: sgio r0, IRQHW3 ; modify t 0462 : 0010_1000_0000_1011_0110_1110 616: jmpr cc_busy, 0 0463 : 0000_0100_1000_1100_0111_0111 617: sgio r0, IRQHL3 0464 : 0010_1000_0000_1011_0110_1111 618: jmpr cc_busy, 0 0465 : 0000_0100_1000_1100_1011_0111 619: jmp cc_uncond, raw_coff 0466 : 0000_0100_0000_0000_0000_1111 620: 621: #else 622: 623: nop 624: nop 625: nop 626: nop 627: nop 628: nop 629: nop 630: nop 631: nop 632: nop 633: nop 634: nop 635: nop 636: nop 637: 638: #endif 639: 640: 641: 642: ;############################################## 643: ;# CPU0, CPU1: start CPU2 and CPU3 for delayed t 644: ;############################################## 645: 646: raw_end_ni_tmsn: 647: mov 1, r1 0467 : 1100_0110_0000_0000_0010_0001 648: #ifdef raw_cpu_pair 649: #ifdef cpu0 650: jmpr cc_busy, 0 651: sgio r1 clk_onoff_next 652: #endif 653: 654: #ifdef cpu1 655: jmpr cc_busy, 0 656: sgio r1 clk_onoff_next 657: #endif 658: 659: #ifdef cpu2 660: nop 661: nop 662: #endif 663: 664: #ifdef cpu3 665: nop 666: nop 667: #endif 668: #endif 669: 670: 671: ;############################################## 672: ;# CPU3: Increment Event Counter 673: ;############################################## 674: 675: #ifdef cpu3 676: 677: mov EventCounter, r0 0468 : 1100_0010_0000_0111_1000_0000 678: add r0, c1, r0 0469 : 1000_0010_0000_0110_0010_0000 679: iext 0x1FFFFF 046A : 0101_0000_0000_0001_1111_1111 680: mov 0x1FFFFF, r1 046B : 1100_0111_1111_1111_1110_0001 681: and r1, r0, r0 046C : 1010_0110_0001_0000_0000_0000 682: jmp cc_nzero, raw_EvtCtrOK 046D : 0000_0100_0000_0000_0000_0001 683: mov 10, r0 046E : 1100_0110_0000_0001_0100_0000 684: raw_EvtCtrOK: 685: jmpr cc_busy, 0 046F : 0000_0100_1000_1101_1111_0111 686: sgio r0 EvtCtrGIOAdr 0470 : 0010_1000_0000_1100_0000_0100 687: 688: #else 689: 690: nop 691: nop 692: nop 693: nop 694: nop 695: nop 696: nop 697: nop 698: nop 699: 700: #endif 701: 702: ;############################################## 703: ;# NI&SCSN transfer end marker 704: ;############################################## 705: 706: mov endsig_rr r0 0471 : 1100_0010_0000_0011_1110_0000 707: spio r0 NODP 0472 : 0010_0000_0000_0000_0000_0000 708: swp rio, rio 0473 : 0111_1010_0000_0001_1100_1110 709: jmpr cc_busy, 0 0474 : 0000_0100_1000_1110_1001_0111 710: sgio+ r0 0475 : 0011_1100_0000_0000_0000_0000 711: swp rio, rio 0476 : 0111_1010_0000_0001_1100_1110 712: 713: 714: ;############################################## 715: ;# automatically go to clear state if ReadoutFla 716: ;############################################## 717: 718: ; mov ReadoutFlag, r2 ; load NI& 719: ; cmp r2, 0 720: ; jmp cc_nzero, coff ; check for transm 721: ; 722: ; #ifdef cpu3 723: ; mov CMD_CLEAR, r0 ; CPU0 indicates u 724: ; jmpr cc_busy, 0 725: ; sgio r0 SMCMD; 726: ; #else 727: ; nop 728: ; nop 729: ; nop 730: ; #endif 731: 732: 733: 734: ;############################################## 735: ;# switch off own clock after transfer 736: ;############################################## 737: 738: raw_coff: 739: mov 0, r0 0477 : 1100_0110_0000_0000_0000_0000 740: 741: jmpr cc_busy, 0 0478 : 0000_0100_1000_1111_0001_0111 742: sgio r0 clk_onoff 0479 : 0010_1000_0000_1010_0010_0111 743: jmpr cc_busy, 0 047A : 0000_0100_1000_1111_0101_0111 744: 745: nop 047B : 0000_0000_0000_0000_0000_0000 746: nop 047C : 0000_0000_0000_0000_0000_0000 747: nop 047D : 0000_0000_0000_0000_0000_0000 748: nop 047E : 0000_0000_0000_0000_0000_0000 749: nop 047F : 0000_0000_0000_0000_0000_0000 750: nop 0480 : 0000_0000_0000_0000_0000_0000 751: nop 0481 : 0000_0000_0000_0000_0000_0000 752: #ifdef cpu3 753: jmpr cc_uncond, 0 0482 : 0000_0100_1001_0000_0100_1111 754: #else 755: jmp cc_uncond, raw_coff 756: #endif 757: nop 0483 : 0000_0000_0000_0000_0000_0000 758: 759: 760: ;################################################# 761: ;# 762: ;# NI transmission of one channel 763: ;# 764: ;################################################# 765: ;# 766: ;# Interface: 767: ;# 768: ;# Input: r14 start address of event buf 769: ;# r1 number of time bins to rea 770: ;# r7 OR mask for the 32 bit wor 771: ;# r2 Readout Flags 772: ;# 773: ;# Output: sends data to the NI outpu 774: ;# Modifies: r3, r4, r5, r14, r1 (0) 775: ;# 776: ;################################################# 777: 778: ;################# 779: ;# BEGIN data tran 780: raw_ChTML: ;################# 781: 782: #ifdef testmode 783: shl 8, rio, r5 784: or r5, c14, r5 785: shl 8, r5, r5 786: or r5, c5, r5 787: add r5, c1, r5 788: add rio, c1, rio 789: 790: #else 791: lpio+ r3 ; initial read has 0484 : 1110_1110_0000_0000_0000_0011 792: lpio+ r3 ; memory delay (sy 0485 : 1110_1110_0000_0000_0000_0011 793: lpio+ r4 0486 : 1110_1110_0000_0000_0000_0100 794: lpio rio, r5 0487 : 1110_0010_0000_0001_1100_0101 795: 796: shl 10, r5, r5 ; combine three 10 0488 : 1011_0010_1010_0000_1010_0101 797: or r5, r4, r5 ; to one (32=10+10 0489 : 1010_1010_0101_0000_1000_0101 798: jmp cc_zero, raw_ADCzero ; correct data if 048A : 0000_0100_0000_0000_0001_0001 799: 800: raw_ADCcor: 801: shl 10, r5, r5 048B : 1011_0010_1010_0000_1010_0101 802: or r5, r3, r5 048C : 1010_1010_0101_0000_0110_0101 803: shl 2, r5, r5 048D : 1011_0010_0010_0000_1010_0101 804: or r5, r7, r5 ; set the two LSBs 048E : 1010_1010_0101_0000_1110_0101 805: #endif 806: 807: spio r5, NODP ; write to NI 048F : 0010_0000_0101_0000_0000_0000 808: 809: ;raw_scsn_readout: 810: swp rio, rio ; switch to SCSN s 0490 : 0111_1010_0000_0001_1100_1110 811: jmpr cc_busy, 0 0491 : 0000_0100_1001_0010_0011_0111 812: sgio+ r5 ; write to DBANK f 0492 : 0011_1100_0101_0000_0000_0000 813: swp rio, rio ; switch back to e 0493 : 0111_1010_0000_0001_1100_1110 814: 815: sub r1, c3, r1 ; decrease number 0494 : 1000_1010_0001_0110_0110_0001 816: jmp cc_gtu, raw_ChTML ; loop 0495 : 0000_0100_0000_0000_0000_1000 817: 818: xor r7, c1, r7 ; turn the LSB 0496 : 1010_0010_0111_0110_0010_0111 819: jmp cc_uncond, rstack ; return from subr 0497 : 0000_1000_1000_0000_0000_1111 820: 821: #ifndef testmode 822: raw_ADCzero: 823: mov 0x400, r4 ; set the LSB of t 0498 : 1100_0110_1000_0000_0000_0100 824: or r5, r4, r5 ; to prevent sendi 0499 : 1010_1010_0101_0000_1000_0101 825: jmp cc_uncond, raw_ADCcor 049A : 0000_0100_0000_0000_0000_1111 826: #endif 827: ;################# 828: ;# END data transf 829: ;################# 830: 831: nop 049B : 0000_0000_0000_0000_0000_0000 832: 833: 834: ;################################################# 835: ;# 836: ;# 0x500: Interrupt NI FIFO empty, irq10 837: ;# 838: ;################################################# 839: 840: ORG 0x500 841: 842: nififoe: 843: 844: sgio r8, IRQHL3 0500 : 0010_1000_1000_1011_0110_1111 845: jmpr cc_busy, 0 0501 : 0000_0100_1010_0000_0011_0111 846: sgio r8, IRQHW3 0502 : 0010_1000_1000_1011_0110_1110 847: jmpr cc_busy, 0 0503 : 0000_0100_1010_0000_0111_0111 848: 849: ; program the delay 850: mov NI_tmsn_delay, r1 0504 : 1100_0010_0000_0111_0110_0001 851: spio r1, 0x200 0505 : 0010_0000_0001_0010_0000_0000 852: mov b1010_0101_1111, r1 ; counter, down, ir 0506 : 1100_0111_0100_1011_1110_0001 853: spio r1, 0x201 0507 : 0010_0000_0001_0010_0000_0001 854: ; enable IRQ local timer 855: mov b0101_0101, r1 0508 : 1100_0110_0000_1010_1010_0001 856: sgio r1, IRQHL3 0509 : 0010_1000_0001_1011_0110_1111 857: jmpr cc_busy, 0 050A : 0000_0100_1010_0001_0101_0111 858: sgio r1, IRQHW3 050B : 0010_1000_0001_1011_0110_1110 859: jmpr cc_busy, 0 050C : 0000_0100_1010_0001_1001_0111 860: jmp cc_uncond, raw_coff 050D : 0000_0100_0000_0000_0000_1111 861: 862: 863: ;################################################# 864: ;# 865: ;# 0x600: Interrupt Local Counter/Timer 866: ;# 867: ;################################################# 868: 869: ORG 0x600 870: 871: localtm: 872: 873: ; restore the interrupt mask 874: ; mov 0x015, r1 875: sgio r8, IRQHL3 0600 : 0010_1000_1000_1011_0110_1111 876: jmpr cc_busy, 0 0601 : 0000_0100_1100_0000_0011_0111 877: sgio r8, IRQHW3 0602 : 0010_1000_1000_1011_0110_1110 878: jmpr cc_busy, 0 0603 : 0000_0100_1100_0000_0111_0111 879: 880: ; send end signature 881: jmp cc_uncond, raw_end_ni_tmsn 0604 : 0000_0100_0000_0000_0000_1111 882: nop 0605 : 0000_0000_0000_0000_0000_0000 883: 884: ORG 0x700 885: ; Style recommendations 886: ; 887: ; 1) use include for the different parts of the CP 888: ; 889: ; 2) use prefix in the labels, e.g. 890: ; 891: ; -- start of the acq subroutine 892: ; acq: ... 893: ; ... 894: ; acq_store: 895: ; ... 896: ; acq_delay: 897: ; ... 898: ; -- end of the acq subroutine 899: 900: ; ADDITIONAL PROGRAMS 901: ; 902: ; GENERAL RULES 903: ; 904: ; 1) The programs do not use any programmable cons 905: ; 2) CPU3 is never used 906: ; 3) The programs use for data exchange a small re 907: ; or DMEM or IMEM3, accessible through GIO. The 908: ; must be defined in the main program as follow 909: ; 910: ; srv_command - command from the SCSN master, 911: ; srv_indata - input data, stored by the SCSN 912: ; srv_outdata - output data, stored by the TRA 913: ; 914: ; 4) The programs may modify all registers (privat 915: ; 916: ; 5) The programs end with command low power to th 917: ; This can be changed later - may be is reasona 918: ; IRT (interrupt return) or just jump to some a 919: ; 920: ; 6) By default the configuration of the main prog 921: ; but sets the start address to a small assembl 922: ; 923: ; 7) When the SCSN master wants to start some serv 924: ; TRAP to the low power state, then modify the 925: ; - store the correct start address of the serv 926: ; stores its request at srv_command and activat 927: ; the state of the TRAP and sends it to low pow 928: ; After finishing the service operation (which 929: ; the SCSN master restores the IVT to the origi 930: 931: 932: ; J2C 933: #ifdef cpu0 934: #inc "j2c.asm" 935: #endif 936: 937: #ifdef cpu1 938: #inc "I2C.asm" 939: #endif 940: 941: #ifdef cpu2 942: ;#inc "jtag.asm" 943: tst: nop 944: #endif 945: org 0xFFE 946: jmp cc_uncond, lpw2 0FFE : 0000_0100_0000_0000_0000_1111 947: jmp cc_uncond, lpw2 0FFF : 0000_0100_0000_0000_0000_1111 Source file read, 0 error(s), 0 warning(s).