Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.6, Dec 2007 SVN Revision 0, SVN Date 2007-12-27 Please send any comments to: angelov@kip.uni-heidelberg.de 23:11:45 / 17 Mar 2008 Source code file: src/fitred.asm Memory initialisation file: Log file: wrk/cpu0.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU0 = 2 CC_SIGNED = 0X14 3 CC_NSIGNED = 0X04 4 CC_ZERO = 0X11 5 CC_NZERO = 0X01 6 CC_OVERFL = 0X13 7 CC_NOVERFL = 0X03 8 CC_NEG = 0X12 9 CC_NNEG = 0X02 10 CC_CARRY = 0X10 11 CC_NCARRY = 0X00 12 CC_BUSY = 0X17 13 CC_NBUSY = 0X07 14 CC_DIVB = 0X15 15 CC_NDIVB = 0X05 16 CC_ERRDIV = 0X16 17 CC_NERRDIV = 0X06 18 CC_UNCOND = 0X0F 19 CC_EQ = 0X11 20 CC_NEQ = 0X01 21 CC_NEG = 0X12 22 CC_POS0 = 0X02 23 CC_LTS = 0X14 24 CC_GES = 0X04 25 CC_LTU = 0X10 26 CC_GEU = 0X00 27 CC_LES = 0X19 28 CC_GTS = 0X09 29 CC_LEU = 0X18 30 CC_GTU = 0X08 31 RR_BYTE = 3 32 RR_WORD = 1 33 RR_DWORD = 0 34 LRA1 = LRA 3, 35 LRA2 = LRA 1, 36 LRA4 = LRA 0, 37 LRA4+ = LRA+ 0, 38 XOR = EOR 39 NOT = COM 40 SHLT = SHL 41 ANDT = AND 42 R0 = PRF[0] 43 R1 = PRF[1] 44 R2 = PRF[2] 45 R3 = PRF[3] 46 R4 = PRF[4] 47 R5 = PRF[5] 48 R6 = PRF[6] 49 R7 = PRF[7] 50 R8 = PRF[8] 51 R9 = PRF[9] 52 R10 = PRF[10] 53 R11 = PRF[11] 54 R12 = PRF[12] 55 R13 = PRF[13] 56 R14 = PRF[14] 57 R15 = PRF[15] 58 G0 = GRF[0] 59 G1 = GRF[1] 60 G2 = GRF[2] 61 G3 = GRF[3] 62 G4 = GRF[4] 63 G5 = GRF[5] 64 G6 = GRF[6] 65 G7 = GRF[7] 66 G8 = GRF[8] 67 G9 = GRF[9] 68 G10 = GRF[10] 69 G11 = GRF[11] 70 G12 = GRF[12] 71 G13 = GRF[13] 72 G14 = GRF[14] 73 G15 = GRF[15] 74 F0 = FIT[0] 75 F1 = FIT[1] 76 F2 = FIT[2] 77 F3 = FIT[3] 78 F4 = FIT[4] 79 F5 = FIT[5] 80 F6 = FIT[6] 81 F7 = FIT[7] 82 F8 = FIT[8] 83 F9 = FIT[9] 84 F10 = FIT[10] 85 F11 = FIT[11] 86 F12 = FIT[12] 87 F13 = FIT[13] 88 F14 = FIT[14] 89 F15 = FIT[15] 90 C0 = CON[0] 91 C1 = CON[1] 92 C2 = CON[2] 93 C3 = CON[3] 94 C4 = CON[4] 95 C5 = CON[5] 96 C6 = CON[6] 97 C7 = CON[7] 98 C8 = CON[8] 99 C9 = CON[9] 100 C10 = CON[10] 101 C11 = CON[11] 102 C12 = CON[12] 103 C13 = CON[13] 104 C14 = CON[14] 105 C15 = CON[15] 106 ASM_SVN_REV = 0 1: ;################################################# 2: ;# 3: ;# Rudimentary Readout Program for TRAP3 chip 4: ;# 5: ;# Marcus Gutfleisch, Venelin Angelov 6: ;# Universitaet Heidelberg, Kirchhoff-Institut fue 7: ;# 8: ;# $Id: fitred.asm 1949 2008-02-18 20:13:19Z angel 9: ;# 10: ;################################################# 11: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: 31: #def CTGDINI=0x0B80; dddd dddd dddd dddd dddd dddd 32: #def CTGCTRL=0x0B81; ---- ---- ---- ---- ---S idce 33: #def CTGDOUT=0x0B82; DDDD DDDD DDDD DDDD DDDD DDDD 34: #def CTPDINI=0x0200; dddd dddd dddd dddd dddd dddd 35: #def CTPCTRL=0x0201; ---- ---- ---- ---- ---S idce 36: #def CTPDOUT=0x0202; DDDD DDDD DDDD DDDD DDDD DDDD 37: 38: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 39: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 40: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 41: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 42: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 43: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 44: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 45: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 46: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 47: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 48: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 49: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 50: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 51: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 52: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 53: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 54: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 55: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 56: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 57: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 58: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 59: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 60: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 61: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 62: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 63: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 64: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 65: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 66: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 67: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 68: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 69: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 70: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 71: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 72: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 73: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 74: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 75: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 76: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 77: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 78: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 79: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 80: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 81: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 82: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 83: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 84: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 85: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 86: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 87: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 88: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 89: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 90: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 91: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 92: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 93: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 94: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 95: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 96: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 97: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 98: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 99: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 100: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 101: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 102: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 103: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 104: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 105: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 106: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 107: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 108: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 109: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 110: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 111: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 112: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 113: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 114: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 115: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 116: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 117: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 118: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 119: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 120: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 121: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 122: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 123: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 124: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 125: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 126: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 127: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 128: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 129: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 130: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 131: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 132: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 133: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 134: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 135: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 136: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 137: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 138: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 139: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 140: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 141: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 142: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 143: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 144: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 145: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 146: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 147: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 148: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 149: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 150: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 151: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 152: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 153: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 154: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 155: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 156: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 157: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 158: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 159: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 160: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 161: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 162: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 163: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 164: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 165: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 166: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 167: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 168: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 169: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 170: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 171: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 172: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 173: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 174: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 175: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 176: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 177: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 178: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 179: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 180: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 181: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 182: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 183: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 184: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 185: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 186: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 187: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 188: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 189: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 190: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 191: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 192: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 193: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 194: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 195: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 196: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 197: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 198: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 199: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 200: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 201: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 202: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 203: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 204: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 205: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 206: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 207: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 208: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 209: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 210: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 211: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 212: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 213: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 214: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 215: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 216: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 217: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 218: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- 219: #def GBUSR0=0x0300; -- readonly 220: #def GBUSR1=0x0301; -- readonly *** End of include file /cad/tools/bin//conf_va.inc 13: #def set_NFSM_acq = 1 14: 15: ;#def testmode_t = 1 ; for tracklets - not up t 16: 17: ; major version bits 18: ; - 1 bit as ZS flag 19: ; - 1 bit as tracklet disable flag 20: ; - 1 bit for ADC data/test pattern 21: ; if ZS then 22: ; - 1 bit: suppress sending of empty header/mask 23: ; - 2 bits: 01/10/11: send every 128/256/1024 ev 24: ; else 25: ; if Testpattern Mode then 26: ; - 3 bits to define the pattern 27: ; else 28: ; - send full data, 1 bit: accumulate sum(ADC) a 29: ; ... 30: ; 31: ; -------------------- 32: ; Ressources in TRAP: 33: ; -------------------- 34: ; DMEM (without BM/HCM chips) 35: ; -------------------- 36: ; Word-Addr Byte-Addr Used for 37: ; 38: ; 0..0x01F 0..0x07C 2**31/N LUT 39: ; 0x020 0x080 pad row number 40: ; 0x021 0x084 y-coord offset 41: ; 0x022 0x088 deflection corr 42: ; 0x023 0x08C scale_y 43: ; 0x024 0x090 scale_d 44: ; 0x025 0x094 ndrift for fitprog 45: ; 0x030..0x053 0x0C0..0x14C deflection range t 46: ; 47: ; 0x058..0x096 0x160..0x258 ADC statistics, se 48: ; 0x058+3*ch 0x160+12*ch ch=0..20, Sum(ADC) 49: ; 0x059+3*ch 0x164+12*ch ch=0..20, Sum(ADC* 50: ; 0x05A+3*ch 0x168+12*ch ch=0..20, Sum(ADC* 51: 52: ; 0x100..0x2FF 0x400..0xBFF e/pi probability L 53: ; 0x300..0x33F 0xC00..0xCFF ADC data of CPU0 f 54: ; 0x340..0x37F 0xD00..0xDFF ADC data of CPU1 f 55: ; 0x380..0x3BF 0xE00..0xEFF ADC data of CPU2 f 56: ; 0x3C0..0x3FF 0xF00..0xFFF ADC data of CPU3 f 57: 58: 59: ; -------------------- 60: ; DBANK 61: ; -------------------- 62: ; Address Used for 63: ; 64: ; 0xF000..0xF0DF packed configuration, used for 65: ; 0xF0E0..0xF0FF packed configuration and singl 66: ; 0xF0E0..0xF0FF MCM3,7,11,15: mailbox, used fo 67: ; 0xF0F0..0xF0FF HCM only: headers for SCSN rea 68: 69: ; -------------------- 70: ; Constants 71: ; -------------------- 72: ; CPU0 73: ; 8 : the start address in GIO of the pa 74: ; 9 : counter for L0A without tracklet, 75: ; 10 : - 76: ; 11 : - 77: ; -------------------- 78: ; CPU1 79: ; 8 : HCM only, used to detect the first 80: ; 9 : counter for L0A without tracklet, 81: ; 10 : - 82: ; 11 : - 83: ; -------------------- 84: ; CPU2 85: ; 8 : - 86: ; 9 : counter for L0A without tracklet, 87: ; 10 : - 88: ; 11 : - 89: ; -------------------- 90: ; CPU3 91: ; 8 : programmable network interface rea 92: ; 9 : counter for L0A without tracklet, 93: ; 10 : - 94: ; 11 : 95: ; -------------------- 96: ; CPU-all 97: ; 12 : event counter, incremented by CPU3 98: ; 13 : number of samples, used for raw da 99: ; 14 : Chip Position for MCM Header (bits 100: ; 15 : half-chamber header 0 101: 102: ; Testpatterns 103: ; 104: ;################################################# 105: ;# 106: ;# defines 107: ;# 108: ;################################################# 109: #def FIT_SVN_REV = $Rev 1949 $; 110: ; ASM_SVN_REV is internally defined in the as 111: ; for I2C and JTAG 112: #def srv_command = 0xF0E0 113: #def srv_indata = 0xF0E1 114: #def srv_outdata = 0xF0F0 115: #def LP_REP = 0xF0E4 116: ; #def DBANKscsn = 1 ; sto 117: ; othe 118: 119: #def nachkommast = 5 120: #def minus_nachk = -5 121: #def rounding_add = 17; 2**(nachkommast-1)+1 122: #def pad_ext = 13; 8 + nachkommast. 123: 124: ; the constants here are used to move the corres 125: #def TPATTflag = -7; test pattern flag (raw d 126: #def ZSflag = -6; zero suppression flag in 127: #def TDISflag = -5; disable tracklets flag i 128: #def ZS_no_empty = -1; suppress sending of empt 129: ; if so finally, some instructions can be optimi 130: #def OPTs = 0; options, 0..15 in bits 3 131: 132: ; For the tracklet calculation 133: ; Name 134: #def pad_row_n = g8; pad row number 135: #def yoffs = g9; y-coord offset 136: #def defl_cor = g10; deflection corr 137: #def scale_y = g11; 0.162354 = 0x29900000 / 2 138: #def scale_d = g12; 0.185547 = 0x2F800000 / 2 139: #def ndrift = g13; drift time in ADC samples 140: 141: #def endsig_rr_tr = g15 ; end 142: #def nsamples = c13 ; numb 143: #def ChipPOS = c14 ; Chip 144: #def EventCounter = c12 ; even 145: #def EvtCtrGIOAdr = 0xC04 ; Addr 146: #def h_0 = c15 ; half 147: #def func_code = g14 ; func 148: #def L0AnTRcnt = c9 ; coun 149: 150: #def rstack = r8 ; prog 151: #def rio = r14 ; loca 152: #def mask_7F = g1 ; mask 153: #def mask_FF = g2 ; mask 154: #def mask_1FFF = g3 ; mask 155: #def ClrCntCxx = c11 ; cons 156: #ifdef cpu0 157: ; #def FIT_READ = 1 ; rea 158: ; Note: Merging is not supported in this case! 159: 160: #def clk_onoff = CPU0SS ; own 161: #def LSBdata = 0x03 ; LSBs 162: #def AddrSCdata = 0xF000 ; Addr 163: #def AddrDMdata = 0x0C00 ; Addr 164: #def AddrDMstat = 0x0160 ; Addr 165: #def lpcount0 = 0xF03C ; coun 166: #def lpcount1 = 0xF07C ; coun 167: #def adc_ch_msk = g4 168: #def L0AnTRcntIO = 0x0C01 169: ;#def ClrCntGio = 0x0C03 170: #ifdef FIT_READ 171: #inc "fit_values0.asm" 172: #endif 173: #endif 174: 175: #ifdef cpu1 176: ; #def FIT_READ = 1 ; rea 177: ; Note: Merging is not supported in this case! 178: 179: #def clk_onoff = CPU1SS ; own 180: #def LSBdata = 0x02 ; LSBs 181: #def AddrSCdata = 0xF040 ; Addr 182: #def AddrDMdata = 0x0D00 ; Addr 183: #def AddrDMstat = 0x019C ; Addr 184: #def lpcount0 = 0xF03D ; coun 185: #def lpcount1 = 0xF07D ; coun 186: #def adc_ch_msk = g5 187: #def L0AnTRcntIO = 0x0C09 188: ;#def ClrCntGio = 0x0C0B 189: #ifdef FIT_READ 190: #inc "fit_values1.asm" 191: #endif 192: #endif 193: 194: #ifdef cpu2 195: #def clk_onoff = CPU2SS ; own 196: #def LSBdata = 0x03 ; LSBs 197: #def AddrSCdata = 0xF080 ; Addr 198: #def AddrDMdata = 0x0E00 ; Addr 199: #def AddrDMstat = 0x01D8 ; Addr 200: #def lpcount0 = 0xF03E ; coun 201: #def lpcount1 = 0xF07E ; coun 202: #def adc_ch_msk = g6 203: #def L0AnTRcntIO = 0x0C11 204: ;#def ClrCntGio = 0x0C13 205: #ifdef FIT_READ 206: #inc "fit_values2.asm" 207: #endif 208: #endif 209: 210: #ifdef cpu3 211: #def clk_onoff = CPU3SS ; own 212: #def LSBdata = 0x02 ; LSBs 213: #def AddrSCdata = 0xF0C0 ; Addr 214: #def AddrDMdata = 0x0F00 ; Addr 215: #def AddrDMstat = 0x0214 ; Addr 216: #def lpcount0 = 0xF03F ; coun 217: #def lpcount1 = 0xF07F ; coun 218: #def adc_ch_msk = g7 219: #def L0AnTRcntIO = 0x0C19 220: ;#def ClrCntGio = 0x0C1B 221: #ifdef FIT_READ 222: #inc "fit_values3.asm" 223: #endif 224: #def NI_tmsn_delay = c8 ; prog 225: #endif 226: 227: 228: ;################################################# 229: ;# 230: ;# 0x000: Infinite Loop at Instruction Memory Rese 231: ;# 232: ;################################################# 233: 234: ORG 0x0; 235: lpw: 236: nop 0000 : 0000_0000_0000_0000_0000_0000 237: nop 0001 : 0000_0000_0000_0000_0000_0000 238: nop 0002 : 0000_0000_0000_0000_0000_0000 239: 240: iext lpcount0 0003 : 0101_0000_0000_0000_0000_1111 241: lgio 0, lpcount0 0004 : 1110_1100_1111_0000_0011_1100 242: jmpr cc_busy, 0 0005 : 0000_0100_0000_0000_1011_0111 243: lpio GBUSR0, r1 0006 : 1110_0110_0110_0000_0000_0001 244: add r1, c1, r1 0007 : 1000_0010_0001_0110_0010_0001 245: iext lpcount0 0008 : 0101_0000_0000_0000_0000_1111 246: sgio r1, lpcount0 0009 : 0010_1000_0001_0000_0011_1100 247: jmpr cc_uncond, 0 000A : 0000_0100_0000_0001_0100_1111 248: nop 000B : 0000_0000_0000_0000_0000_0000 249: 250: lpw2: 251: nop 000C : 0000_0000_0000_0000_0000_0000 252: nop 000D : 0000_0000_0000_0000_0000_0000 253: iext lpcount1 000E : 0101_0000_0000_0000_0000_1111 254: lgio 0, lpcount1 000F : 1110_1100_1111_0000_0111_1100 255: jmpr cc_busy, 0 0010 : 0000_0100_0000_0010_0001_0111 256: lpio GBUSR0, r1 0011 : 1110_0110_0110_0000_0000_0001 257: add r1, c1, r1 0012 : 1000_0010_0001_0110_0010_0001 258: iext lpcount1 0013 : 0101_0000_0000_0000_0000_1111 259: sgio r1, lpcount1 0014 : 0010_1000_0001_0000_0111_1100 260: jmpr cc_uncond, 0 0015 : 0000_0100_0000_0010_1010_1111 261: nop 0016 : 0000_0000_0000_0000_0000_0000 262: 263: 264: ;################################################# 265: ;# 266: ;# 0x100: Interrupt Clear Jump Address 267: ;# 268: ;################################################# 269: 270: ; In IRQ CLR some data are copied from DMEM to GRF 271: ; 1) read pad_row_n (pad row number) from 0xC020 a 272: ; 2) read yoffset (y-coordinate offset) from 0xC02 273: ; 3) read defl_cor (deflection correction constant 274: ; 4) read scale_y : 0.162354 = 0x29900000 / 2^32 f 275: ; 5) read scale_d : 0.185547 = 0x2F800000 / 2^32 f 276: 277: 278: ORG 0x100; 279: 280: clr: 281: mov 0, r12 0100 : 1100_0110_0000_0000_0000_1100 282: #ifdef cpu0 283: #ifdef ClrCntGio 284: mov ClrCntCxx, r1 285: add r1, c1, r1 286: sgio r1, ClrCntGio 287: #endif 288: iext b1111_0000_0000_0000_0010_0000; 0101 : 0101_0000_0000_1111_0000_0000 289: mov b1111_0000_0000_0000_0010_0000, r1 0102 : 1100_0110_0000_0100_0000_0001 290: jmpr cc_busy, 0 0103 : 0000_0100_0010_0000_0111_0111 291: sgio r1, SMOFFON ; switch o 0104 : 0010_1000_0001_1010_0000_0101 292: 293: mov 0x28, r0 ; clear N 0105 : 1100_0110_0000_0101_0000_0000 294: jmpr cc_busy, 0 0106 : 0000_0100_0010_0000_1101_0111 295: sgio r0, NMOD 0107 : 0010_1000_0000_1101_0100_0000 296: 297: mov 0x08, r0 0108 : 1100_0110_0000_0001_0000_0000 298: jmpr cc_busy, 0 0109 : 0000_0100_0010_0001_0011_0111 299: sgio r0, NMOD 010A : 0010_1000_0000_1101_0100_0000 300: 301: #else ; cpu1,2,3 302: #ifdef ClrCntGio 303: mov ClrCntCxx, r1 304: add r1, c1, r1 305: sgio r1, ClrCntGio 306: #endif 307: ; check the type of the chip 308: swp ChipPOS, r1 ; the flag 309: andt r1, c3 ; if 0, HC 310: jmp cc_zero, clr_bm_hcm 311: 312: ; clr for normal chips, cpu1,2,3 313: 314: #ifdef cpu1 315: mov 0x080, r15; prepare for reading from D 316: mov 18, r0 ; or may b 317: lra rr_dword, r1 318: lra+ rr_dword, r1 319: mov r1, pad_row_n 320: 321: lra rr_dword, r1 322: lra+ rr_dword, r1 323: shl pad_ext, r0, r0 ; 18*256*2 324: add r1, r0, yoffs 325: #endif 326: 327: #ifdef cpu2 328: mov 0x088, r15 ; prepare 329: nop 330: nop 331: lra rr_dword, r1 332: lra+ rr_dword, r1 333: mov r1, defl_cor 334: 335: lra rr_dword, r1 336: lra+ rr_dword, r1 337: mov r1, scale_y 338: #endif 339: 340: #ifdef cpu3 341: mov 0x090, r15 ; prepare 342: nop 343: nop 344: lra rr_dword, r1 345: lra+ rr_dword, r1 346: mov r1, scale_d 347: lra rr_dword, r1 348: lra+ rr_dword, r1 349: mov r1, ndrift 350: #endif 351: #endif 352: clr_endloop: 353: nop 010B : 0000_0000_0000_0000_0000_0000 354: nop 010C : 0000_0000_0000_0000_0000_0000 355: nop 010D : 0000_0000_0000_0000_0000_0000 356: nop 010E : 0000_0000_0000_0000_0000_0000 357: nop 010F : 0000_0000_0000_0000_0000_0000 358: nop 0110 : 0000_0000_0000_0000_0000_0000 359: nop 0111 : 0000_0000_0000_0000_0000_0000 360: nop 0112 : 0000_0000_0000_0000_0000_0000 361: nop 0113 : 0000_0000_0000_0000_0000_0000 362: nop 0114 : 0000_0000_0000_0000_0000_0000 363: nop 0115 : 0000_0000_0000_0000_0000_0000 364: nop 0116 : 0000_0000_0000_0000_0000_0000 365: nop 0117 : 0000_0000_0000_0000_0000_0000 366: nop 0118 : 0000_0000_0000_0000_0000_0000 367: nop 0119 : 0000_0000_0000_0000_0000_0000 368: nop 011A : 0000_0000_0000_0000_0000_0000 369: nop 011B : 0000_0000_0000_0000_0000_0000 370: nop 011C : 0000_0000_0000_0000_0000_0000 371: jmpr cc_uncond, 0 011D : 0000_0100_0010_0011_1010_1111 372: nop 011E : 0000_0000_0000_0000_0000_0000 373: 374: clr_bm_hcm: 375: #ifdef cpu1 376: mov c8, g0 ; flag to 377: cmp r12, g0 ; r12=0, g 378: jmp cc_neq, clr_endloop ; if r12 /= g 379: ; store 1 to c8 via GIO 380: mov 1, r0 381: sgio r0, 0xC08 382: ; init the privat counter/timer as counter/up/ 383: mov 0x640, r0 384: spio r0, CTPCTRL 385: spio r12, CTPDINI 386: #endif 387: 388: #ifdef cpu2 389: nop 390: nop 391: cmp r12, g0 ; r12 is 0 392: jmp cc_neq clr_endloop 393: ; init the privat counter/timer as counter/dow 394: mov 0xA40, r0 395: spio r0, CTPCTRL 396: mov 11, r0 397: spio r0, CTPDINI 398: #endif 399: 400: #ifdef cpu3 401: nop 402: nop 403: nop 404: cmp r12, g0 405: jmp cc_neq, clr_endloop 406: ; init the privat counter/timer as counter/up/pr 407: mov 0x700, r0 408: spio r0, CTPCTRL 409: spio r12, CTPDINI 410: #endif 411: 412: jmp cc_uncond, clr_endloop 011F : 0000_0100_0000_0000_0000_1111 413: nop 0120 : 0000_0000_0000_0000_0000_0000 414: 415: 416: ;################################################# 417: ;# 418: ;# 0x200: Interrupt Tracklet Processing Jump Addre 419: ;# 420: ;################################################# 421: 422: ORG 0x200; 423: 424: #ifndef testmode_t 425: acq: 426: ; by only one CPU! 427: #ifdef cpu0 428: lgio 0, NES 0200 : 1110_1100_0000_1101_0100_0101 429: shl nachkommast, c1, r13 0201 : 1011_0010_0101_0110_0010_1101 430: neg r13, r13 ; load 0202 : 1010_1110_0000_0001_1010_1101 431: jmpr cc_busy, 0 0203 : 0000_0100_0100_0000_0111_0111 432: lpio GBUSR0, r2 0204 : 1110_0110_0110_0000_0000_0010 433: mov r2, endsig_rr_tr 0205 : 1100_0010_0000_0000_0101_1111 434: #endif 435: 436: #ifdef cpu1 437: shl nachkommast, c1, r13 438: neg r13, r13 ; load 439: mov 0x7F, mask_7F 440: ; copy the end signature words NES into GR 441: mov 0xFF, mask_FF 442: iext 0x1FFF 443: mov 0x1FFF, mask_1FFF 444: #endif 445: 446: #ifdef cpu2 447: shl nachkommast, c1, r13 448: neg r13, r13 ; load 449: shl -11, h_0, func_code 450: shl -11, func_code, func_code 451: nop 452: nop 453: #endif 454: 455: #ifdef cpu3 456: shl nachkommast, c1, r13 457: neg r13, r13 ; load 458: nop 459: nop 460: nop 461: nop 462: #endif 463: 464: 465: shlt TDISflag, func_code 0206 : 1011_0001_1011_0011_1100_0000 466: jmp cc_carry, acq_no_tr 0207 : 0000_0100_0000_0000_0001_0000 467: #ifdef FIT_READ 468: mov f00_value, adc_ch_msk 469: #else 470: mov f0, adc_ch_msk ; g[4+CPU# 0208 : 1100_0010_0000_0100_0001_0100 471: #endif 472: 473: 474: ;################################# 475: ;# 476: ;# check for tracklets: CHANN 477: ;# 478: ;################################# 479: 480: #ifdef FIT_READ 481: mov f00_value, r8 482: cmp r8, 31 483: #else 484: cmp f0, 31 0209 : 1100_1001_0000_0000_0001_1111 485: #endif 486: 487: #ifdef testmode_r 488: jmp cc_uncond, acq_no_tr 489: #else 490: jmp cc_eq, acq_no_tr ; if CHANN 020A : 0000_0100_0000_0000_0001_0001 491: #endif 492: 493: #ifdef cpu1 494: #ifdef FIT_READ 495: sub r8, g4, r0 ; r0 = f0( 496: #else 497: sub f0, g4, r0 ; r0 = f0( 498: #endif 499: #endif 500: 501: #ifdef cpu2 502: #ifdef FIT_READ 503: sub r8, g5, r0 ; r0 = f0( 504: #else 505: sub f0, g5, r0 ; r0 = f0( 506: #endif 507: #endif 508: 509: #ifdef cpu3 510: #ifdef FIT_READ 511: sub r8, g6, r0 ; r0 = f0( 512: #else 513: sub f0, g6, r0 ; r0 = f0( 514: #endif 515: #endif 516: 517: #ifdef cpu0 518: nop 020B : 0000_0000_0000_0000_0000_0000 519: nop 020C : 0000_0000_0000_0000_0000_0000 520: nop 020D : 0000_0000_0000_0000_0000_0000 521: nop 020E : 0000_0000_0000_0000_0000_0000 522: nop 020F : 0000_0000_0000_0000_0000_0000 523: #else 524: cmp r0, c1 ; compare 525: jmp cc_eq, acq_no_tr1 526: cmp r0, c7 ; compare 527: jmp cc_eq, acq_no_tr2 528: #endif 529: 530: ;################################# 531: ;# 532: ;# fit parameter calculation 533: ;# 534: ;# SLOPE = ( N * XY - X * Y ) 535: ;# OFFSET = ( XX * Y - X * XY 536: ;# 537: ;################################# 538: 539: #ifdef FIT_READ 540: mov f01_value, r15 ; f9_value 541: mov f03_value, r1 ; f3+f11, 542: #else 543: add f1, f9, r15 ; N = N0 0210 : 1000_0011_0001_0101_0010_1111 544: add f3, f11, r1 ; X = X0 0211 : 1000_0011_0011_0101_0110_0001 545: #endif 546: mul32 r1, r1, r3 ; X * 0212 : 1001_0000_0001_0000_0010_1011 547: 548: #ifdef FIT_READ 549: iext f04_value 550: mov f04_value, r2 ; f4 is 14 551: #else 552: add f4, f12, r2 ; XX = XX0 0213 : 1000_0011_0100_0101_1000_0010 553: #endif 554: mul32 r15, r2, r4 ; N * 0214 : 1001_0000_1111_0000_0100_1100 555: 556: #ifdef FIT_READ 557: iext f02_value 558: mov f02_value, r7 559: #else 560: add f2, f10, r7 ; Q = Q0 0215 : 1000_0011_0010_0101_0100_0111 561: #endif 562: sub r4, r3, r3 ; N * 0216 : 1000_1010_0100_0000_0110_0011 563: 564: ; r12 = 0 565: ; r13 = -4 566: 567: div r12, r3 ; 2**(32+n 0217 : 1001_1000_1100_0000_0110_0000 568: 569: #ifdef FIT_READ 570: iext f05_value 571: mov f05_value, r5 572: #else 573: shl 8, f9, r5 ; 256 0218 : 1011_0010_1000_0101_0010_0101 574: add f13, r5, r5 ; Y1 0219 : 1000_0011_1101_0000_1010_0101 575: add f5, r5, r5 ; Y = Y0 021A : 1000_0011_0101_0000_1010_0101 576: #endif 577: 578: #ifdef FIT_READ 579: iext f06_value 580: mov f06_value, r6 581: #else 582: shl 8, f11, r6 ; 256 021B : 1011_0010_1000_0101_0110_0110 583: add f14, r6, r6 ; XY1 021C : 1000_0011_1110_0000_1100_0110 584: add f6, r6, r6 ; XY = XY0 021D : 1000_0011_0110_0000_1100_0110 585: #endif 586: 587: mus32 r1, r5, r3 ; X * 021E : 1001_0100_0001_0000_1010_1011 588: mus32 r1, r6, r4 ; X * 021F : 1001_0100_0001_0000_1100_1100 589: mus32 r2, r5, r1 ; XX 0220 : 1001_0100_0010_0000_1010_1001 590: mus32 r15, r6, r2 ; N * 0221 : 1001_0100_1111_0000_1100_1010 591: 592: sub r1, r4, r1 ; OF = XX 0222 : 1000_1010_0001_0000_1000_0001 593: sub r2, r3, r2 ; SL = N * 0223 : 1000_1010_0010_0000_0110_0010 594: 595: shl 2, r15, r15 ; byt 0224 : 1011_0010_0010_0001_1110_1111 596: 597: ; QA = low 598: shl -16, r7, r4 ; QB = hig 0225 : 1011_0011_0000_0000_1110_0100 599: 600: lra rr_dword, r0 ; 2** 0226 : 1101_0010_0000_0000_0000_0000 601: lra rr_dword, r0 ; 2** 0227 : 1101_0010_0000_0000_0000_0000 602: 603: mul r0, r4, r0 ; QB * 2** 0228 : 1001_0000_0000_0000_1000_0000 604: nop ; do somet 0229 : 0000_0000_0000_0000_0000_0000 605: 606: and r13, mask_FF, r6 ; QB * 2** 022A : 1010_0110_1101_0010_0100_0110 607: ; QB / N > 608: shl 4, r6, r6 ; E.PROBAB 022B : 1011_0010_0100_0000_1100_0110 609: or r6, pad_row_n, r6 ; E.PROBAB 022C : 1010_1010_0110_0011_0000_0110 610: 611: die r7 ; get 2**( 022D : 1001_1110_0000_0000_0000_0111 612: 613: mus r7, r1, r1 ; lower 32 022E : 1001_0100_0111_0000_0010_0001 614: mus r7, r2, r2 ; lower 32 022F : 1001_0100_0111_0000_0100_0010 615: 616: add r13, yoffs, r1 ; save the 0230 : 1000_0010_1101_0011_0010_0001 617: mus32 r13, ndrift, r2 ; save the 0231 : 1001_0100_1101_0011_1010_1010 618: ; here we have: 619: ; offset in r1 (1 PAD = 256*2**nachkommas 620: ; slope in r2 (1 PAD = 256*2**nachkommas 621: 622: ; the deflection table is at address 0x0C0 623: 624: mov 0x0C0, r15 ; the star 0232 : 1100_0110_0001_1000_0000_1111 625: #ifdef FIT_READ 626: mov f00_value, r13 627: shl 3, r13, r13 628: #else 629: shl 3, f0, r13 ; 2**3 (=8 0233 : 1011_0010_0011_0100_0000_1101 630: #endif 631: add r13, r15, r15 ; the addr 0234 : 1000_0010_1101_0001_1110_1111 632: 633: #ifdef FIT_READ 634: mov f00_value, r8 635: shl pad_ext, r8, r8 636: #else 637: shl pad_ext, f0, r8 ; 256*2**n 0235 : 1011_0010_1101_0100_0000_1000 638: #endif 639: sub r1, r8, r1 ; OFFSET [ 0236 : 1000_1010_0001_0001_0000_0001 640: add r2, defl_cor, r2 ; add the 0237 : 1000_0010_0010_0011_0100_0010 641: 642: ; check if the deflection is in the proper 643: lra rr_dword, r13 0238 : 1101_0010_0000_0000_0000_1101 644: lra+ rr_dword, r13 ; the min 0239 : 1111_0010_0000_0000_0000_1101 645: cmp r13, r2 023A : 1000_1000_1101_0000_0100_0000 646: jmp cc_gts, acq_out_min ; jump if 023B : 0000_0100_0000_0000_0000_1001 647: lra rr_dword, r13 023C : 1101_0010_0000_0000_0000_1101 648: lra+ rr_dword, r13 ; the min 023D : 1111_0010_0000_0000_0000_1101 649: cmp r2, r13 023E : 1000_1000_0010_0001_1010_0000 650: jmp cc_gts, acq_out_max ; jump if 023F : 0000_0100_0000_0000_0000_1001 651: mov rounding_add, r8 ; prepare 0240 : 1100_0110_0000_0010_0010_1000 652: mus r1, scale_y, r1 ; scale pr 0241 : 1001_0100_0001_0011_0110_0001 653: mus r2, scale_d, r2 ; the resu 0242 : 1001_0100_0010_0011_1000_0010 654: add r13, r8, r1 ; rounding 0243 : 1000_0010_1101_0001_0000_0001 655: add r13, r8, r2 0244 : 1000_0010_1101_0001_0000_0010 656: 657: sha minus_nachk, r1, r1 ; remove t 0245 : 1011_0111_1011_0000_0010_0001 658: sha minus_nachk, r2, r2 0246 : 1011_0111_1011_0000_0100_0010 659: 660: and r1, mask_1FFF, r1 0247 : 1010_0110_0001_0010_0110_0001 661: and r2, mask_7F, r2 0248 : 1010_0110_0010_0010_0010_0010 662: 663: shl 7, r6, r6 ; prepare 0249 : 1011_0010_0111_0000_1100_0110 664: or r6, r2, r6 ; put the 024A : 1010_1010_0110_0000_0100_0110 665: shl 13, r6, r6 ; prepare 024B : 1011_0010_1101_0000_1100_0110 666: or r6, r1, r6 ; the trac 024C : 1010_1010_0110_0000_0010_0110 667: 668: ;################################# 669: ;# 670: ;# tracklet synthesis and tra 671: ;# Bits Name Size Ty 672: ;# 12.. 0 OFFSET 13 si 673: ;# 19..13 DEFLECTION 7 si 674: ;# 23..20 PAD ROW 4 un 675: ;# 31..24 QTOTAL 8 un 676: ;# 677: ;################################# 678: 679: acq_write_tr: 680: mov 13, r1 ; delay tr 024D : 1100_0110_0000_0001_1010_0001 681: 682: acq_tr_del: 683: sub r1, c1, r1 024E : 1000_1010_0001_0110_0010_0001 684: jmp cc_nzero, acq_tr_del 024F : 0000_0100_0000_0000_0000_0001 685: 686: #ifdef cpu0 687: mov b0000_0010_0000, r1 0250 : 1100_0110_0000_0100_0000_0001 688: jmpr cc_busy, 0 0251 : 0000_0100_0100_1010_0011_0111 689: sgio r1, SMOFF ; switch o 0252 : 0010_1000_0001_1010_0000_0111 690: #else 691: nop 692: nop 693: nop 694: #endif 695: 696: #ifdef set_NFSM_acq 697: #ifdef cpu0 698: lgio 0, NFSM 0253 : 1110_1100_0000_1101_1100_0010 699: jmpr cc_busy, 0 0254 : 0000_0100_0100_1010_1001_0111 700: lpio GBUSR0, r5 0255 : 1110_0110_0110_0000_0000_0101 701: lgio 1, SMCMD 0256 : 1110_1101_0000_1010_0000_0100 702: shl 12, r5, r5 0257 : 1011_0010_1100_0000_1010_0101 703: jmpr cc_busy, 0 0258 : 0000_0100_0100_1011_0001_0111 704: lpio GBUSR1, r4 0259 : 1110_0110_0110_0000_0010_0100 705: or r5, r4, r5 025A : 1010_1010_0101_0000_1000_0101 706: sgio r5, 0xC02 025B : 0010_1000_0101_1100_0000_0010 707: #else 708: nop 709: nop 710: nop 711: nop 712: nop 713: nop 714: nop 715: nop 716: nop 717: #endif 718: #endif 719: ;acq_send_tr_mult: 720: spio r6, NODP 025C : 0010_0000_0110_0000_0000_0000 721: nop 025D : 0000_0000_0000_0000_0000_0000 722: spio r6, NODP 025E : 0010_0000_0110_0000_0000_0000 723: jmp cc_uncond, clr_endloop 025F : 0000_0100_0000_0000_0000_1111 724: nop 0260 : 0000_0000_0000_0000_0000_0000 725: 726: ;################################# 727: ;# 728: ;# send end signature if ther 729: ;# 730: ;# do any power management he 731: ;# 732: ;################################# 733: 734: acq_no_tr0: 735: nop 0261 : 0000_0000_0000_0000_0000_0000 736: nop 0262 : 0000_0000_0000_0000_0000_0000 737: nop 0263 : 0000_0000_0000_0000_0000_0000 738: nop 0264 : 0000_0000_0000_0000_0000_0000 739: acq_no_tr: 740: nop 0265 : 0000_0000_0000_0000_0000_0000 741: nop 0266 : 0000_0000_0000_0000_0000_0000 742: nop 0267 : 0000_0000_0000_0000_0000_0000 743: acq_no_tr1: 744: nop 0268 : 0000_0000_0000_0000_0000_0000 745: nop 0269 : 0000_0000_0000_0000_0000_0000 746: nop 026A : 0000_0000_0000_0000_0000_0000 747: acq_no_tr2: 748: mov 16, r1 ; delay tr 026B : 1100_0110_0000_0010_0000_0001 749: acq_nt_del: 750: sub r1, c1, r1 026C : 1000_1010_0001_0110_0010_0001 751: jmp cc_nzero, acq_nt_del 026D : 0000_0100_0000_0000_0000_0001 752: acq_L1AnTRcnt: 753: mov L0AnTRcnt, r1 026E : 1100_0010_0000_0111_0010_0001 754: add r1, c1, r1 026F : 1000_0010_0001_0110_0010_0001 755: sgio r1, L0AnTRcntIO 0270 : 0010_1000_0001_1100_0000_0001 756: 757: mov endsig_rr_tr, r6 0271 : 1100_0010_0000_0011_1110_0110 758: jmp cc_uncond, acq_write_tr 0272 : 0000_0100_0000_0000_0000_1111 759: nop 0273 : 0000_0000_0000_0000_0000_0000 760: 761: acq_out_min: 762: nop 0274 : 0000_0000_0000_0000_0000_0000 763: nop 0275 : 0000_0000_0000_0000_0000_0000 764: nop 0276 : 0000_0000_0000_0000_0000_0000 765: nop 0277 : 0000_0000_0000_0000_0000_0000 766: acq_out_max: 767: nop; 0278 : 0000_0000_0000_0000_0000_0000 768: nop; 0279 : 0000_0000_0000_0000_0000_0000 769: nop; 027A : 0000_0000_0000_0000_0000_0000 770: nop; 027B : 0000_0000_0000_0000_0000_0000 771: jmp cc_uncond, acq_L1AnTRcnt 027C : 0000_0100_0000_0000_0000_1111 772: nop 027D : 0000_0000_0000_0000_0000_0000 773: 774: #else ; testmode_t=1 775: 776: ;################################# 777: ;# 778: ;# Test mode, send tracklets 779: ;# 780: ;# depending on C14, C15 781: ;# 782: ;# The tracklet is composed s 783: ;# 784: ;# [31..16] = c15[31..16] (RO 785: ;# [19..16] = bit mask, which 786: ;# [15.. 8] = c14[ 4.. 0] (MC 787: ;# [ 7.. 0] = C & CPU ID (c5) 788: ;# 789: ;################################# 790: acq: 791: #ifdef cpu0 792: mov b0000_0010_0000, r1 793: jmpr cc_busy, 0 794: sgio r1, SMOFF ; switch o 795: #else 796: nop ; could be 797: nop 798: nop 799: #endif 800: 801: iext 0xFFFF 802: mov 0xFFFF, r0 803: swp r0, r0 804: and r0, c15, r0 805: mov 0x1F, r1 806: and r1, ChipPOS, r1 807: shl 8, r1, r1 808: or r1, r0, r0 809: mov 0xC0, r1 810: or r1, r0, r0 811: or r0, c5, r0 812: 813: shl -8, ChipPOS, r2 814: shl -8, r2, r2 815: neg c5, r3 816: shl r3, r2, r2 817: and r2, c1, r2 818: jmp cc_zero, acq_no_tr 819: shl 1, ChipPOS 820: jmp cc_nzero, acq_no_tr ; in case 821: 822: 823: nop 824: mov 36, r1 ; delay tr 825: acq_tr_del: 826: sub r1, c1, r1 827: jmp cc_nzero, acq_tr_del 828: nop 829: 830: spio r0, NODP 831: nop 832: 833: spio r0, NODP 834: jmpr cc_uncond, 0 835: nop 836: 837: acq_no_tr: 838: mov 36, r1 ; delay tr 839: acq_nt_del: 840: sub r1, c1, r1 841: jmp cc_nzero, acq_nt_del 842: 843: mov endsig_rr_tr, r5 844: #ifdef cpu0 845: xor r5,c1,r5 ; emulate 846: #else 847: nop 848: #endif 849: spio r5, NODP 850: nop 851: 852: spio r5, NODP 853: 854: jmpr cc_uncond, 0 855: nop 856: #endif 857: 858: ;################################################# 859: ;# 860: ;# 0x400: Interrupt Raw Data Transmission Jump Add 861: ;# 862: ;################################################# 863: 864: ORG 0x400 865: 866: raw: 867: 868: #ifdef cpu0 869: mov cmd_CPU_done r0 ; CPU0 ind 0400 : 1100_0110_1110_0010_0100_0000 870: sgio r0 SMCMD; 0401 : 0010_1000_0000_1010_0000_0100 871: #else 872: nop 873: nop 874: #endif 875: 876: ;############################################## 877: ;# Store Start addresses for SCSN transfer via D 878: ;############################################## 879: 880: #ifdef DBANKscsn 881: iext AddrSCdata 882: mov AddrSCdata, rio 883: #else 884: mov AddrDMstat, r15 0402 : 1100_0110_0010_1100_0000_1111 885: swp r15, r15 0403 : 0111_1010_0000_0001_1110_1111 886: mov AddrDMdata, r2 0404 : 1100_0111_1000_0000_0000_0010 887: or r15, r2, r15 0405 : 1010_1010_1111_0000_0100_1111 888: #endif 889: 890: swp ChipPOS, r2 ; load NI& 0406 : 0111_1010_0000_0111_1100_0010 891: 892: shlt -3, r2 ; move bit 0407 : 1011_0001_1101_0000_0100_0000 893: jmp cc_carry, raw_hc0 ; bit 2=1 0408 : 0000_0100_0000_0000_0001_0000 894: 895: #ifdef DBANKscsn 896: swp rio, rio ; swap DBA 897: #endif 898: andt r2, c3 0409 : 1010_0100_0010_0110_0110_0000 899: jmp cc_zero, raw_complete_ni_tmsn ; check fo 040A : 0000_0100_0000_0000_0001_0001 900: 901: #ifdef cpu0 902: shl 7, c1, r0 040B : 1011_0010_0111_0110_0010_0000 903: or r0, ChipPOS, r0 ; combine 040C : 1010_1010_0000_0111_1100_0000 904: shl 12, r0, r0 040D : 1011_0010_1100_0000_0000_0000 905: shl 12, r0, r0 ; 1 & Chip 040E : 1011_0010_1100_0000_0000_0000 906: mov 0xC, r1 040F : 1100_0110_0000_0001_1000_0001 907: or r0, r1, r0 ; 1 & Chip 0410 : 1010_1010_0000_0000_0010_0000 908: or r0, g5, r11 ; 1 & Chip 0411 : 1010_1010_0000_0010_1010_1011 909: ; do not send the MCM Header now 910: #ifdef DBANKscsn 911: swp rio, rio 912: sgio+ r11 ; no busy 913: swp rio, rio ; till nex 914: #else 915: sra+ r11 0412 : 0011_1000_1011_0000_0000_0000 916: #endif 917: #endif 918: 919: #ifdef cpu1 920: ; this CPU helps to CPU0 to prepare the event 921: iext 0xFFFFF ; 20 bits 922: mov 0xFFFFF, r0 ; mask for 923: and r0, EventCounter, r0 ; event co 924: shl 4, r0, g5 ; the lowe 925: jmp cc_uncond raw_check_zs 926: nop 927: nop 928: nop 929: #ifdef DBANKscsn 930: nop 931: nop 932: #endif 933: #endif 934: 935: #ifdef cpu2 936: jmp cc_uncond raw_check_zs 937: nop 938: nop 939: nop 940: nop 941: nop 942: nop 943: nop 944: #ifdef DBANKscsn 945: nop 946: nop 947: #endif 948: #endif 949: 950: #ifdef cpu3 951: jmp cc_uncond raw_check_zs 952: nop 953: nop 954: nop 955: nop 956: nop 957: nop 958: nop 959: #ifdef DBANKscsn 960: nop 961: nop 962: #endif 963: #endif 964: 965: raw_check_zs: 966: 967: #ifdef DBANKscsn 968: iext 0xFFFF0000 ; high wor 969: mov 0xFFFF0000, r15 ; Note: th 970: #endif 971: 972: mov nsamples, r1 ; initiall 0413 : 1100_0010_0000_0111_1010_0001 973: cmp r1, 0 0414 : 1100_1000_0001_0000_0000_0000 974: jmp cc_zero, raw_complete_ni_tmsn ; check fo 0415 : 0000_0100_0000_0000_0001_0001 975: 976: ; first check if the zero suppression is on 977: shlt ZSflag, func_code 0416 : 1011_0001_1010_0011_1100_0000 978: jmp cc_ncarry raw_no_zsup 0417 : 0000_0100_0000_0000_0000_0000 979: 980: ; ZERO SUPPRESSION case 981: ; check if some events should be send without 982: shl OPTs, func_code, r8 0418 : 1011_0010_0000_0011_1100_1000 983: shl -1, r8, r8 ; only bit 0419 : 1011_0011_1111_0001_0000_1000 984: and r8, c3, r8 041A : 1010_0110_1000_0110_0110_1000 985: jmp cc_zero, raw_ebi_read ; 00 means 041B : 0000_0100_0000_0000_0001_0001 986: mov 0x07F, r9 ; in case 041C : 1100_0110_0000_1111_1110_1001 987: cmp r8, 2 041D : 1100_1000_1000_0000_0000_0010 988: jmpr cc_neq, +2 041E : 0000_0100_1000_0100_0000_0001 989: mov 0x0FF, r9 ; in case 041F : 1100_0110_0001_1111_1110_1001 990: cmp r8, 3 0420 : 1100_1000_1000_0000_0000_0011 991: jmpr cc_neq, +2 0421 : 0000_0100_1000_0100_0110_0001 992: mov 0x3FF, r9 ; in case 0422 : 1100_0110_0111_1111_1110_1001 993: and r9, EventCounter, r9 ; take the 0423 : 1010_0110_1001_0111_1000_1001 994: cmp r9, 1 ; and comp 0424 : 1100_1000_1001_0000_0000_0001 995: jmp cc_neq, raw_ebi_read ; normal Z 0425 : 0000_0100_0000_0000_0000_0001 996: #ifdef cpu3 997: mov b11_1111, r6 ; set whic 998: #else 999: mov b01_1111, r6 ; set whic 0426 : 1100_0110_0000_0011_1110_0110 1000: #endif 1001: jmp cc_uncond, raw_ebiscan_done ; skip the 0427 : 0000_0100_0000_0000_0000_1111 1002: 1003: ; now read the indicators and mark the ADC cha 1004: raw_ebi_read: 1005: SEM b1111_0000 ; sync mas 0428 : 0001_0000_0000_0000_1111_0000 1006: mov c1, r8 ; mask, wi 0429 : 1100_0010_0000_0110_0010_1000 1007: mov EBI0, r9 ; address 042A : 1100_0111_0011_0000_0000_1001 1008: 1009: not c0, r10 042B : 1011_1110_0000_0110_0000_1010 1010: mov 32, r0 042C : 1100_0110_0000_0100_0000_0000 1011: sub r0, nsamples, r0 042D : 1000_1010_0000_0111_1010_0000 1012: neg r0, r0 042E : 1010_1110_0000_0000_0000_0000 1013: shl r0, r10, r10 042F : 0111_0010_0000_0001_0100_1010 1014: mov c0, r6 0430 : 1100_0010_0000_0110_0000_0110 1015: raw_ebiscan: 1016: lpio r9, r0 ; read twi 0431 : 1110_0010_0000_0001_0010_0000 1017: lpio r9, r0 0432 : 1110_0010_0000_0001_0010_0000 1018: not r0, r0 ; invert t 0433 : 1011_1110_0000_0000_0000_0000 1019: and r0, r10, r0 ; mask the 0434 : 1010_0110_0000_0001_0100_0000 1020: jmpr cc_zero, +2 0435 : 0000_0100_1000_0110_1111_0001 1021: or r6, r8, r6 ; set the 0436 : 1010_1010_0110_0001_0000_0110 1022: add r9, c2, r9 ; incremen 0437 : 1000_0010_1001_0110_0100_1001 1023: shl 1, r8, r8 ; shift th 0438 : 1011_0010_0001_0001_0000_1000 1024: #ifdef cpu3 1025: cmp r8, b100_0000 ; check fo 1026: #else 1027: cmp r8, b010_0000 ; check fo 0439 : 1100_1000_1000_0000_0010_0000 1028: #endif 1029: jmp cc_neq, raw_ebiscan 043A : 0000_0100_0000_0000_0000_0001 1030: 1031: ; the adc mask in r6 is not absolute, now shif 1032: raw_ebiscan_done: 1033: #ifdef cpu0 1034: nop ; cpu0 has 043B : 0000_0000_0000_0000_0000_0000 1035: #endif 1036: #ifdef cpu1 1037: shl 5, r6, r6 ; cpu1 has 1038: #endif 1039: #ifdef cpu2 1040: shl 10, r6, r6 ; cpu2 has 1041: #endif 1042: #ifdef cpu3 1043: shl 15, r6, r6 ; cpu3 has 1044: #endif 1045: 1046: ; calculate the ADC mask for the zero suppress 1047: cmp f8, 0 ; ch+1 is 043C : 1100_1001_1000_0000_0000_0000 1048: jmp cc_zero raw_notrack 043D : 0000_0100_0000_0000_0001_0001 1049: mov 0xF, r0 ; 1111b, t 043E : 1100_0110_0000_0001_1110_0000 1050: cmp f9, 0 ; number o 043F : 1100_1001_1001_0000_0000_0000 1051: jmp cc_nzero raw_4pads 0440 : 0000_0100_0000_0000_0000_0001 1052: shl -1, r0, r0 ; 0111b bu 0441 : 1011_0011_1111_0000_0000_0000 1053: raw_4pads: 1054: mov f0, r1 0442 : 1100_0010_0000_0100_0000_0001 1055: cmp r1, 16 ; the max 0443 : 1100_1000_0001_0000_0001_0000 1056: jmpr cc_ltu, +3 0444 : 0000_0100_1000_1000_1111_0000 1057: shl 4, r0, r0 0445 : 1011_0010_0100_0000_0000_0000 1058: sub r1, c4, r1 0446 : 1000_1010_0001_0110_1000_0001 1059: ; continue, r1 is < 16 here 1060: shl r1, r0, r0 ; X111b << 0447 : 0111_0010_0001_0000_0000_0000 1061: or r0, r6, r6 0448 : 1010_1010_0000_0000_1100_0110 1062: raw_notrack: 1063: mov r6, adc_ch_msk 0449 : 1100_0010_0000_0000_1101_0100 1064: SYN; 044A : 0000_1100_0000_0000_0000_0000 1065: ; here all CPUs start simultaneously 1066: 1067: or r6, g4, r6 ; CPU0 044B : 1010_1010_0110_0010_1000_0110 1068: or r6, g5, r6 ; CPU1 044C : 1010_1010_0110_0010_1010_0110 1069: or r6, g6, r6 ; CPU2 044D : 1010_1010_0110_0010_1100_0110 1070: or r6, g7, r6 ; CPU3 044E : 1010_1010_0110_0010_1110_0110 1071: 1072: ; shift back to the right to get the mask rela 1073: #ifdef cpu0 1074: nop 044F : 0000_0000_0000_0000_0000_0000 1075: #endif 1076: #ifdef cpu1 1077: shl -5, r6, r6 1078: #endif 1079: #ifdef cpu2 1080: shl -10, r6, r6 1081: #endif 1082: #ifdef cpu3 1083: shl -15, r6, r6 1084: #endif 1085: SEM b1111_0000 ; sync mas 0450 : 0001_0000_0000_0000_1111_0000 1086: 1087: ; count the number of 1 in r6 1088: mov 0, r7 ; clear th 0451 : 1100_0110_0000_0000_0000_0111 1089: shlt -1, r6 ; copy bit 0452 : 1011_0001_1111_0000_1100_0000 1090: adc r7, c0, r7 ; add the 0453 : 1000_0110_0111_0110_0000_0111 1091: shlt -2, r6 ; copy bit 0454 : 1011_0001_1110_0000_1100_0000 1092: adc r7, c0, r7 ; add the 0455 : 1000_0110_0111_0110_0000_0111 1093: shlt -3, r6 ; copy bit 0456 : 1011_0001_1101_0000_1100_0000 1094: adc r7, c0, r7 ; add the 0457 : 1000_0110_0111_0110_0000_0111 1095: shlt -4, r6 ; copy bit 0458 : 1011_0001_1100_0000_1100_0000 1096: adc r7, c0, r7 ; add the 0459 : 1000_0110_0111_0110_0000_0111 1097: shlt -5, r6 ; copy bit 045A : 1011_0001_1011_0000_1100_0000 1098: adc r7, c0, r7 ; add the 045B : 1000_0110_0111_0110_0000_0111 1099: #ifdef cpu3 1100: shlt -6, r6 ; copy bit 1101: adc r7, c0, r7 ; add the 1102: #else 1103: nop 045C : 0000_0000_0000_0000_0000_0000 1104: nop 045D : 0000_0000_0000_0000_0000_0000 1105: #endif 1106: mov r7, adc_ch_msk ; move to 045E : 1100_0010_0000_0000_1111_0100 1107: SYN 045F : 0000_1100_0000_0000_0000_0000 1108: #ifdef cpu0 1109: add r7, g5, r7 ; accumula 0460 : 1000_0010_0111_0010_1010_0111 1110: add r7, g6, r7 ; accumula 0461 : 1000_0010_0111_0010_1100_0111 1111: add r7, g7, r7 ; accumula 0462 : 1000_0010_0111_0010_1110_0111 1112: #else 1113: nop 1114: nop 1115: nop 1116: #endif 1117: nop 0463 : 0000_0000_0000_0000_0000_0000 1118: mov r6, adc_ch_msk ; copy bac 0464 : 1100_0010_0000_0000_1101_0100 1119: mov raw_ChTML_adc, r9 ; use the 0465 : 1100_0110_0000_0000_0000_1001 1120: #ifdef cpu0 1121: nop 0466 : 0000_0000_0000_0000_0000_0000 1122: #else 1123: jmp cc_uncond, raw_transf_ch ; cpu0 mus 1124: #endif; 1125: 1126: 1127: ; CPU0 only 1128: shlt ZS_no_empty, func_code 0467 : 1011_0001_1111_0011_1100_0000 1129: jmpr cc_ncarry +3 0468 : 0000_0100_1000_1101_0110_0000 1130: cmp r7, 0 0469 : 1100_1000_0111_0000_0000_0000 1131: jmp cc_eq raw_transf_ch ; skip sen 046A : 0000_0100_0000_0000_0001_0001 1132: ; start st 1133: 1134: spio r11 NODP ; NI trans 046B : 0010_0000_1011_0000_0000_0000 1135: ; combine the full mask 1136: not r7, r7 ; the numb 046C : 1011_1110_0000_0000_1110_0111 1137: shl 13, r7, r7 046D : 1011_0010_1101_0000_1110_0111 1138: shl 13, r7, r7 046E : 1011_0010_1101_0000_1110_0111 1139: shl -1, r7, r7 046F : 1011_0011_1111_0000_1110_0111 1140: shl 2, r6, r6 0470 : 1011_0010_0010_0000_1100_0110 1141: or r6, c3, r6 ; 11 0471 : 1010_1010_0110_0110_0110_0110 1142: shl 2, r6, r6 ; 01 & not 0472 : 1011_0010_0010_0000_1100_0110 1143: or r7, r6, r6 0473 : 1010_1010_0111_0000_1100_0110 1144: spio r6, NODP ; send the 0474 : 0010_0000_0110_0000_0000_0000 1145: 1146: jmp cc_uncond raw_transf_ch 0475 : 0000_0100_0000_0000_0000_1111 1147: 1148: raw_no_zsup: 1149: 1150: #ifdef cpu0 1151: spio r11 NODP ; NI trans 0476 : 0010_0000_1011_0000_0000_0000 1152: #else 1153: nop 1154: #endif 1155: 1156: #ifdef cpu3 1157: mov b11_1111, adc_ch_msk ; show whi 1158: #else 1159: mov b01_1111, adc_ch_msk ; show whi 0477 : 1100_0110_0000_0011_1111_0100 1160: #endif 1161: 1162: shlt TPATTflag, func_code 0478 : 1011_0001_1001_0011_1100_0000 1163: jmp cc_carry, raw_pattern_sel 0479 : 0000_0100_0000_0000_0001_0000 1164: 1165: mov raw_ChTML_adc, r9 ; use the 047A : 1100_0110_0000_0000_0000_1001 1166: shlt ZS_no_empty, func_code ; here use 047B : 1011_0001_1111_0011_1100_0000 1167: jmp cc_ncarry, raw_transf_ch 047C : 0000_0100_0000_0000_0000_0000 1168: mov raw_ChTML_adcS, r9 ; use the 047D : 1100_0110_0000_0000_0000_1001 1169: jmp cc_uncond, raw_transf_ch ; 047E : 0000_0100_0000_0000_0000_1111 1170: 1171: raw_pattern_sel: 1172: ; patterns 1173: shl OPTs, func_code, r9 047F : 1011_0010_0000_0011_1100_1001 1174: mov 0x3, r6 ; 2 bit ma 0480 : 1100_0110_0000_0000_0110_0110 1175: and r6, r9, r6 ; the patt 0481 : 1010_0110_0110_0001_0010_0110 1176: mov raw_ChTML_p0, r9 ; pattern 0482 : 1100_0110_0000_0000_0000_1001 1177: cmp r6, 2 0483 : 1100_1000_0110_0000_0000_0010 1178: jmpr cc_neq, +3 0484 : 0000_0100_1001_0000_1110_0001 1179: mov raw_ChTML_p2, r9 ; pattern 0485 : 1100_0110_0000_0000_0000_1001 1180: jmp cc_uncond, raw_prepare_23 0486 : 0000_0100_0000_0000_0000_1111 1181: cmp r6, 3 0487 : 1100_1000_0110_0000_0000_0011 1182: jmp cc_neq, raw_check_psrg 0488 : 0000_0100_0000_0000_0000_0001 1183: mov raw_ChTML_p3, r9 ; pattern 0489 : 1100_0110_0000_0000_0000_1001 1184: 1185: raw_prepare_23: 1186: shl -1, h_0, r13 ; sector/p 048A : 1011_0011_1111_0111_1110_1101 1187: mov 0x7FF, r3 048B : 1100_0110_1111_1111_1110_0011 1188: and r3, r13, r13 048C : 1010_0110_0011_0001_1010_1101 1189: mov b100_1001, r3 048D : 1100_0110_0000_1001_0010_0011 1190: add r3, r13, r13 ; add 1 to 048E : 1000_0010_0011_0001_1010_1101 1191: mov ChipPos, r3 048F : 1100_0010_0000_0111_1100_0011 1192: and r3, mask_7F, r3 0490 : 1010_0110_0011_0010_0010_0011 1193: shl 7, r13, r13 0491 : 1011_0010_0111_0001_1010_1101 1194: or r13, r3, r13 ; sector(5 0492 : 1010_1010_1101_0000_0110_1101 1195: shl 2, r13, r13 0493 : 1011_0010_0010_0001_1010_1101 1196: or r13, c5, r13 ; sector(5 0494 : 1010_1010_1101_0110_1010_1101 1197: 1198: jmp cc_neq, raw_transf_ch 0495 : 0000_0100_0000_0000_0000_0001 1199: 1200: raw_check_psrg: 1201: cmp r6, 1 0496 : 1100_1000_0110_0000_0000_0001 1202: jmp cc_neq, raw_transf_ch 0497 : 0000_0100_0000_0000_0000_0001 1203: mov raw_ChTML_p1, r9 ; pattern 0498 : 1100_0110_0000_0000_0000_1001 1204: ; init the local counter 1205: mov b101001, r6 ; inc afte 0499 : 1100_0110_0000_0101_0010_0110 1206: spio r6, CTPCTRL 049A : 0010_0000_0110_0010_0000_0001 1207: shl 7, c1, r6 ; 1000 000 049B : 1011_0010_0111_0110_0010_0110 1208: add r6, ChipPOS, r6 ; 1rrr mmm 049C : 1000_0010_0110_0111_1100_0110 1209: shl 2, r6, r6 ; 1r rrmm 049D : 1011_0010_0010_0000_1100_0110 1210: or r6, c5, r6 ; 1r rrmm 049E : 1010_1010_0110_0110_1010_0110 1211: spio r6, CTPDINI 049F : 0010_0000_0110_0010_0000_0000 1212: 1213: raw_transf_ch: 1214: 1215: ;############################################## 1216: ;# NI&SCSN transfer 1st channel 1217: ;############################################## 1218: 1219: mov LSBdata, r7 ; pass the 04A0 : 1100_0110_0000_0000_0110_0111 1220: mov 0, r3 ; used in 04A1 : 1100_0110_0000_0000_0000_0011 1221: mov NODP, r6 ; the NI o 04A2 : 1100_0110_0000_0000_0000_0110 1222: shl -1, adc_ch_msk, adc_ch_msk ; check th 04A3 : 1011_0011_1111_0010_1001_0100 1223: jmpr cc_carry, +2 04A4 : 0000_0100_1001_0100_1101_0000 1224: mov GBUSR0, r6 ; dummy ou 04A5 : 1100_0110_0110_0000_0000_0110 1225: 1226: #ifdef DBANKscsn 1227: mov EBR0, r0 ; address 1228: or r0, rio, rio ; to low w 1229: #else 1230: mov EBR0, rio 04A6 : 1100_0111_0000_0000_0000_1110 1231: #endif 1232: cmp r9, raw_ChTML_adcS ; check if 04A7 : 1100_1000_1001_0000_0000_0000 1233: jmpr cc_neq, +3 04A8 : 0000_0100_1001_0101_0110_0001 1234: mov 0, r11 04A9 : 1100_0110_0000_0000_0000_1011 1235: mov 0, r13 04AA : 1100_0110_0000_0000_0000_1101 1236: mov nsamples,r1 ; number o 04AB : 1100_0010_0000_0111_1010_0001 1237: mvpcr +2, rstack 04AC : 1100_0110_1001_0101_1100_1000 1238: jmp cc_uncond, r9; 04AD : 0000_1000_1001_0000_0000_1111 1239: 1240: ;############################################## 1241: ;# NI&SCSN transfer 2nd channel 1242: ;############################################## 1243: 1244: mov NODP, r6 ; the NI o 04AE : 1100_0110_0000_0000_0000_0110 1245: shl -1, adc_ch_msk, adc_ch_msk ; check th 04AF : 1011_0011_1111_0010_1001_0100 1246: jmpr cc_carry, +2 04B0 : 0000_0100_1001_0110_0101_0000 1247: mov GBUSR0, r6 ; dummy ou 04B1 : 1100_0110_0110_0000_0000_0110 1248: 1249: 1250: #ifdef DBANKscsn 1251: and r15, rio, rio 1252: mov EBR1, r0 ; address 1253: or r0, rio, rio ; to low w 1254: #else 1255: mov EBR1, rio 04B2 : 1100_0111_0000_1000_0000_1110 1256: #endif 1257: cmp r9, raw_ChTML_adcS ; check if 04B3 : 1100_1000_1001_0000_0000_0000 1258: jmpr cc_neq, +3 04B4 : 0000_0100_1001_0110_1110_0001 1259: mov 0, r11 04B5 : 1100_0110_0000_0000_0000_1011 1260: mov 0, r13 04B6 : 1100_0110_0000_0000_0000_1101 1261: mov nsamples,r1 ; number o 04B7 : 1100_0010_0000_0111_1010_0001 1262: mvpcr +2, rstack 04B8 : 1100_0110_1001_0111_0100_1000 1263: jmp cc_uncond, r9; 04B9 : 0000_1000_1001_0000_0000_1111 1264: 1265: 1266: ;############################################## 1267: ;# NI&SCSN transfer 3rd channel 1268: ;############################################## 1269: 1270: mov NODP, r6 ; the NI o 04BA : 1100_0110_0000_0000_0000_0110 1271: shl -1, adc_ch_msk, adc_ch_msk ; check th 04BB : 1011_0011_1111_0010_1001_0100 1272: jmpr cc_carry, +2 04BC : 0000_0100_1001_0111_1101_0000 1273: mov GBUSR0, r6 ; dummy ou 04BD : 1100_0110_0110_0000_0000_0110 1274: 1275: #ifdef DBANKscsn 1276: and r15, rio, rio 1277: mov EBR2, r0 ; address 1278: or r0, rio, rio ; to low w 1279: #else 1280: mov EBR2, rio 04BE : 1100_0111_0001_0000_0000_1110 1281: #endif 1282: cmp r9, raw_ChTML_adcS ; check if 04BF : 1100_1000_1001_0000_0000_0000 1283: jmpr cc_neq, +3 04C0 : 0000_0100_1001_1000_0110_0001 1284: mov 0, r11 04C1 : 1100_0110_0000_0000_0000_1011 1285: mov 0, r13 04C2 : 1100_0110_0000_0000_0000_1101 1286: mov nsamples,r1 ; number o 04C3 : 1100_0010_0000_0111_1010_0001 1287: mvpcr +2, rstack 04C4 : 1100_0110_1001_1000_1100_1000 1288: jmp cc_uncond, r9; 04C5 : 0000_1000_1001_0000_0000_1111 1289: 1290: 1291: ;############################################## 1292: ;# NI&SCSN transfer 4th channel 1293: ;############################################## 1294: 1295: mov NODP, r6 ; the NI o 04C6 : 1100_0110_0000_0000_0000_0110 1296: shl -1, adc_ch_msk, adc_ch_msk ; check th 04C7 : 1011_0011_1111_0010_1001_0100 1297: jmpr cc_carry, +2 04C8 : 0000_0100_1001_1001_0101_0000 1298: mov GBUSR0, r6 ; dummy ou 04C9 : 1100_0110_0110_0000_0000_0110 1299: 1300: #ifdef DBANKscsn 1301: and r15, rio, rio 1302: mov EBR3, r0 ; address 1303: or r0, rio, rio ; to low w 1304: #else 1305: mov EBR3, rio 04CA : 1100_0111_0001_1000_0000_1110 1306: #endif 1307: cmp r9, raw_ChTML_adcS ; check if 04CB : 1100_1000_1001_0000_0000_0000 1308: jmpr cc_neq, +3 04CC : 0000_0100_1001_1001_1110_0001 1309: mov 0, r11 04CD : 1100_0110_0000_0000_0000_1011 1310: mov 0, r13 04CE : 1100_0110_0000_0000_0000_1101 1311: mov nsamples,r1 ; number o 04CF : 1100_0010_0000_0111_1010_0001 1312: mvpcr +2, rstack 04D0 : 1100_0110_1001_1010_0100_1000 1313: jmp cc_uncond, r9; 04D1 : 0000_1000_1001_0000_0000_1111 1314: 1315: 1316: ;############################################## 1317: ;# NI&SCSN transfer 5th channel 1318: ;############################################## 1319: 1320: mov NODP, r6 ; the NI o 04D2 : 1100_0110_0000_0000_0000_0110 1321: shl -1, adc_ch_msk, adc_ch_msk ; check th 04D3 : 1011_0011_1111_0010_1001_0100 1322: jmpr cc_carry, +2 04D4 : 0000_0100_1001_1010_1101_0000 1323: mov GBUSR0, r6 ; dummy ou 04D5 : 1100_0110_0110_0000_0000_0110 1324: 1325: #ifdef DBANKscsn 1326: and r15, rio, rio 1327: mov EBR4, r0 ; address 1328: or r0, rio, rio ; to low w 1329: #else 1330: mov EBR4, rio 04D6 : 1100_0111_0010_0000_0000_1110 1331: #endif 1332: cmp r9, raw_ChTML_adcS ; check if 04D7 : 1100_1000_1001_0000_0000_0000 1333: jmpr cc_neq, +3 04D8 : 0000_0100_1001_1011_0110_0001 1334: mov 0, r11 04D9 : 1100_0110_0000_0000_0000_1011 1335: mov 0, r13 04DA : 1100_0110_0000_0000_0000_1101 1336: mov nsamples,r1 ; number o 04DB : 1100_0010_0000_0111_1010_0001 1337: mvpcr +2, rstack 04DC : 1100_0110_1001_1011_1100_1000 1338: jmp cc_uncond, r9; 04DD : 0000_1000_1001_0000_0000_1111 1339: 1340: 1341: ;############################################## 1342: ;# NI&SCSN transfer 6th channel (CPU3 only) 1343: ;############################################## 1344: 1345: #ifdef cpu3 1346: mov NODP, r6 ; the NI o 1347: shl -1, adc_ch_msk, adc_ch_msk ; check th 1348: jmpr cc_carry, +2 1349: mov GBUSR0, r6 ; dummy ou 1350: 1351: #ifdef DBANKscsn 1352: and r15, rio, rio 1353: mov EBR5, r0 ; address 1354: or r0, rio, rio ; to low w 1355: #else 1356: mov EBR5, rio 1357: #endif 1358: cmp r9, raw_ChTML_adcS ; check if 1359: jmpr cc_neq, +3 1360: mov 0, r11 1361: mov 0, r13 1362: mov nsamples,r1 ; number o 1363: mvpcr +2, rstack 1364: jmp cc_uncond, r9; 1365: #else 1366: nop 04DE : 0000_0000_0000_0000_0000_0000 1367: nop 04DF : 0000_0000_0000_0000_0000_0000 1368: nop 04E0 : 0000_0000_0000_0000_0000_0000 1369: nop 04E1 : 0000_0000_0000_0000_0000_0000 1370: nop 04E2 : 0000_0000_0000_0000_0000_0000 1371: nop 04E3 : 0000_0000_0000_0000_0000_0000 1372: nop 04E4 : 0000_0000_0000_0000_0000_0000 1373: nop 04E5 : 0000_0000_0000_0000_0000_0000 1374: nop 04E6 : 0000_0000_0000_0000_0000_0000 1375: nop 04E7 : 0000_0000_0000_0000_0000_0000 1376: nop 04E8 : 0000_0000_0000_0000_0000_0000 1377: nop 04E9 : 0000_0000_0000_0000_0000_0000 1378: #ifdef DBANKscsn 1379: nop 1380: nop 1381: #endif; 1382: #endif; 1383: 1384: 1385: ;############################################## 1386: ;# Slow down NI transmission if NI_tmsn_delay != 1387: ;############################################## 1388: 1389: raw_complete_ni_tmsn: 1390: #ifdef cpu3 1391: mov NI_tmsn_delay, r1 ; mov does 1392: andt r1, r1 1393: jmp cc_zero, raw_end_ni_tmsn 1394: cli 1395: lgio 0, IRQHW3 1396: jmpr cc_busy, 0 1397: lpio 0x300, r11 1398: mov 0x415, r0 ; the new 1399: sgio r0, IRQHW3 ; modify t 1400: jmpr cc_busy, 0 1401: sgio r0, IRQHL3 1402: jmpr cc_busy, 0 1403: jmp cc_uncond, raw_coff 1404: #else 1405: nop 04EA : 0000_0000_0000_0000_0000_0000 1406: nop 04EB : 0000_0000_0000_0000_0000_0000 1407: nop 04EC : 0000_0000_0000_0000_0000_0000 1408: nop 04ED : 0000_0000_0000_0000_0000_0000 1409: nop 04EE : 0000_0000_0000_0000_0000_0000 1410: nop 04EF : 0000_0000_0000_0000_0000_0000 1411: nop 04F0 : 0000_0000_0000_0000_0000_0000 1412: nop 04F1 : 0000_0000_0000_0000_0000_0000 1413: nop 04F2 : 0000_0000_0000_0000_0000_0000 1414: nop 04F3 : 0000_0000_0000_0000_0000_0000 1415: nop 04F4 : 0000_0000_0000_0000_0000_0000 1416: nop 04F5 : 0000_0000_0000_0000_0000_0000 1417: nop 04F6 : 0000_0000_0000_0000_0000_0000 1418: #endif 1419: 1420: ;############################################## 1421: ;# CPU0, CPU1: start CPU2 and CPU3 for delayed t 1422: ;############################################## 1423: 1424: raw_end_ni_tmsn: 1425: 1426: ;############################################## 1427: ;# CPU3: Increment Event Counter 1428: ;############################################## 1429: 1430: #ifdef cpu3 1431: 1432: mov EventCounter, r0 1433: add r0, c1, r0 1434: jmpr cc_busy, 0 1435: sgio r0 EvtCtrGIOAdr 1436: #else 1437: nop 04F7 : 0000_0000_0000_0000_0000_0000 1438: nop 04F8 : 0000_0000_0000_0000_0000_0000 1439: nop 04F9 : 0000_0000_0000_0000_0000_0000 1440: nop 04FA : 0000_0000_0000_0000_0000_0000 1441: #endif 1442: 1443: ;############################################## 1444: ;# NI&SCSN transfer end marker 1445: ;############################################## 1446: 1447: swp endsig_rr_tr, r0 ; the uppe 04FB : 0111_1010_0000_0011_1110_0000 1448: spio r0 NODP 04FC : 0010_0000_0000_0000_0000_0000 1449: #ifdef DBANKscsn 1450: swp rio, rio 1451: jmpr cc_busy, 0 1452: sgio+ r0 1453: swp rio, rio 1454: #else 1455: sra+ r0 04FD : 0011_1000_0000_0000_0000_0000 1456: #endif 1457: 1458: 1459: ;############################################## 1460: ;# switch off own clock after transfer 1461: ;############################################## 1462: 1463: raw_coff: 1464: mov 0, r0 04FE : 1100_0110_0000_0000_0000_0000 1465: 1466: jmpr cc_busy, 0 04FF : 0000_0100_1001_1111_1111_0111 1467: sgio r0 clk_onoff 0500 : 0010_1000_0000_1010_0010_0001 1468: jmpr cc_busy, 0 0501 : 0000_0100_1010_0000_0011_0111 1469: 1470: jmp cc_uncond, clr_endloop 0502 : 0000_0100_0000_0000_0000_1111 1471: nop 0503 : 0000_0000_0000_0000_0000_0000 1472: nop 0504 : 0000_0000_0000_0000_0000_0000 1473: nop 0505 : 0000_0000_0000_0000_0000_0000 1474: nop 0506 : 0000_0000_0000_0000_0000_0000 1475: nop 0507 : 0000_0000_0000_0000_0000_0000 1476: nop 0508 : 0000_0000_0000_0000_0000_0000 1477: nop 0509 : 0000_0000_0000_0000_0000_0000 1478: nop 050A : 0000_0000_0000_0000_0000_0000 1479: nop 050B : 0000_0000_0000_0000_0000_0000 1480: nop 050C : 0000_0000_0000_0000_0000_0000 1481: nop 050D : 0000_0000_0000_0000_0000_0000 1482: nop 050E : 0000_0000_0000_0000_0000_0000 1483: nop 050F : 0000_0000_0000_0000_0000_0000 1484: nop 0510 : 0000_0000_0000_0000_0000_0000 1485: nop 0511 : 0000_0000_0000_0000_0000_0000 1486: nop 0512 : 0000_0000_0000_0000_0000_0000 1487: nop 0513 : 0000_0000_0000_0000_0000_0000 1488: nop 0514 : 0000_0000_0000_0000_0000_0000 1489: nop 0515 : 0000_0000_0000_0000_0000_0000 1490: #ifdef cpu3 1491: jmp cc_uncond, clr_endloop 1492: #else 1493: jmp cc_uncond, raw_coff 0516 : 0000_0100_0000_0000_0000_1111 1494: #endif 1495: nop 0517 : 0000_0000_0000_0000_0000_0000 1496: 1497: 1498: ;################################################# 1499: ;# 1500: ;# NI transmission of one channel 1501: ;# 1502: ;################################################# 1503: ;# 1504: ;# Interface: 1505: ;# 1506: ;# Input: r14 start address of event buf 1507: ;# r1 number of time bins to rea 1508: ;# r7 OR mask for the 32 bit wor 1509: ;# r2 Readout Flags 1510: ;# r6 address in LIO of the outp 1511: ;# r8 rstack, return address 1512: ;# r9 the begin address of the p 1513: ;# 1514: ;# Output: sends data to the NI outpu 1515: ;# Modifies: r3, r4, r5, r14, r1, r13 1516: ;# 1517: ;################################################# 1518: 1519: ;################# 1520: ;# BEGIN data tran 1521: 1522: raw_ChTML_p0: ; (0x0800+i) < 1523: mov 0xFF, r3 0518 : 1100_0110_0001_1111_1110_0011 1524: and r3, ChipPOS, r3 ; for mode 0 0519 : 1010_0110_0011_0111_1100_0011 1525: shl 8, rio, r5 051A : 1011_0010_1000_0001_1100_0101 1526: or r3, r5, r5 051B : 1010_1010_0011_0000_1010_0101 1527: shl 8, r5, r5 051C : 1011_0010_1000_0000_1010_0101 1528: or r5, c5, r5 051D : 1010_1010_0101_0110_1010_0101 1529: add r5, c1, r5 051E : 1000_0010_0101_0110_0010_0101 1530: add rio, c1, rio 051F : 1000_0010_1110_0110_0010_1110 1531: jmp cc_uncond, raw_wadc 0520 : 0000_0100_0000_0000_0000_1111 1532: 1533: raw_ChTML_p1: ; ADCs replace 1534: lpio CTPDOUT, r3 0521 : 1110_0110_0100_0000_0100_0011 1535: mov 0x3FF, r5 ; mask for 10 0522 : 1100_0110_0111_1111_1110_0101 1536: and r3, r5, r3 0523 : 1010_0110_0011_0000_1010_0011 1537: lpio CTPDOUT, r4 0524 : 1110_0110_0100_0000_0100_0100 1538: and r4, r5, r4 0525 : 1010_0110_0100_0000_1010_0100 1539: shl 10, r4, r4 0526 : 1011_0010_1010_0000_1000_0100 1540: or r4, r3, r3 0527 : 1010_1010_0100_0000_0110_0011 1541: lpio CTPDOUT, r5 0528 : 1110_0110_0100_0000_0100_0101 1542: shl 10, r5, r5 0529 : 1011_0010_1010_0000_1010_0101 1543: jmp cc_uncond, raw_ADCcor 052A : 0000_0100_0000_0000_0000_1111 1544: 1545: raw_ChTML_p2: 1546: shl 10, EventCounter, r5 052B : 1011_0010_1010_0111_1000_0101 1547: shl 10, r5, r5 052C : 1011_0010_1010_0000_1010_0101 1548: or r5, r13, r5 ; evncnt(6)/se 052D : 1010_1010_0101_0001_1010_0101 1549: shl 6, r5, r5 052E : 1011_0010_0110_0000_1010_0101 1550: add r3, c1, r3 ; counter++, f 052F : 1000_0010_0011_0110_0010_0011 1551: or r5, r3, r5 ; ... counter( 0530 : 1010_1010_0101_0000_0110_0101 1552: jmp cc_uncond, raw_wadc 0531 : 0000_0100_0000_0000_0000_1111 1553: 1554: raw_ChTML_p3: 1555: shl 10, EventCounter, r5 0532 : 1011_0010_1010_0111_1000_0101 1556: shl 10, r5, r5 0533 : 1011_0010_1010_0000_1010_0101 1557: or r5, r13, r5 ; evncnt(12)/s 0534 : 1010_1010_0101_0001_1010_0101 1558: jmp cc_uncond, raw_wadc 0535 : 0000_0100_0000_0000_0000_1111 1559: 1560: raw_ChTML_adcS: 1561: lpio+ r3 ; initial 0536 : 1110_1110_0000_0000_0000_0011 1562: lpio+ r3 ; memory d 0537 : 1110_1110_0000_0000_0000_0011 1563: lpio+ r4 0538 : 1110_1110_0000_0000_0000_0100 1564: lpio rio, r5 0539 : 1110_0010_0000_0001_1100_0101 1565: mul32 r3, r3, r0 ; calculat 053A : 1001_0000_0011_0000_0110_1000 1566: add r11, r3, r11 ; accumula 053B : 1000_0010_1011_0000_0110_1011 1567: add r13, r0, r13 ; accumula 053C : 1000_0010_1101_0000_0000_1101 1568: mul32 r4, r4, r0 ; calculat 053D : 1001_0000_0100_0000_1000_1000 1569: add r11, r4, r11 ; accumula 053E : 1000_0010_1011_0000_1000_1011 1570: add r13, r0, r13 ; accumula 053F : 1000_0010_1101_0000_0000_1101 1571: mul32 r5, r5, r0 ; calculat 0540 : 1001_0000_0101_0000_1010_1000 1572: add r11, r5, r11 ; accumula 0541 : 1000_0010_1011_0000_1010_1011 1573: add r13, r0, r13 ; accumula 0542 : 1000_0010_1101_0000_0000_1101 1574: jmp cc_uncond, raw_ChTML_shift 0543 : 0000_0100_0000_0000_0000_1111 1575: 1576: raw_ChTML_adc: 1577: lpio+ r3 ; initial 0544 : 1110_1110_0000_0000_0000_0011 1578: lpio+ r3 ; memory d 0545 : 1110_1110_0000_0000_0000_0011 1579: lpio+ r4 0546 : 1110_1110_0000_0000_0000_0100 1580: lpio rio, r5 0547 : 1110_0010_0000_0001_1100_0101 1581: 1582: raw_ChTML_shift: 1583: shl 10, r5, r5 ; combine 0548 : 1011_0010_1010_0000_1010_0101 1584: or r5, r4, r5 ; to one ( 0549 : 1010_1010_0101_0000_1000_0101 1585: jmp cc_zero, raw_ADCzero ; correct 054A : 0000_0100_0000_0000_0001_0001 1586: 1587: raw_ADCcor: 1588: shl 10, r5, r5 054B : 1011_0010_1010_0000_1010_0101 1589: or r5, r3, r5 054C : 1010_1010_0101_0000_0110_0101 1590: shl 2, r5, r5 054D : 1011_0010_0010_0000_1010_0101 1591: or r5, r7, r5 ; set the 054E : 1010_1010_0101_0000_1110_0101 1592: 1593: raw_wadc: 1594: spio r5, r6 ; write to 054F : 0100_0100_0101_0000_1100_0000 1595: 1596: ;raw_scsn_readout: 1597: #ifdef DBANKscsn 1598: swp rio, rio ; switch t 1599: jmpr cc_busy, 0 1600: sgio+ r5 ; write to 1601: swp rio, rio ; switch b 1602: #else 1603: sra+ r5 0550 : 0011_1000_0101_0000_0000_0000 1604: #endif 1605: 1606: sub r1, c3, r1 ; decrease 0551 : 1000_1010_0001_0110_0110_0001 1607: jmp cc_gtu, r9 ; loop, th 0552 : 0000_1000_1001_0000_0000_1000 1608: 1609: xor r7, c1, r7 ; turn the 0553 : 1010_0010_0111_0110_0010_0111 1610: cmp r9, raw_ChTML_adcS ; check if 0554 : 1100_1000_1001_0000_0000_0000 1611: jmp cc_neq, rstack ; return f 0555 : 0000_1000_1000_0000_0000_0001 1612: swp r15, r15 ; swap the 0556 : 0111_1010_0000_0001_1110_1111 1613: nop 0557 : 0000_0000_0000_0000_0000_0000 1614: lra4 r4 ; read the 0558 : 1101_0010_0000_0000_0000_0100 1615: lra4 r4 0559 : 1101_0010_0000_0000_0000_0100 1616: add r11, r4, r11 ; add the 055A : 1000_0010_1011_0000_1000_1011 1617: sra+ r11 ; and writ 055B : 0011_1000_1011_0000_0000_0000 1618: nop ; the reg 055C : 0000_0000_0000_0000_0000_0000 1619: lra4 r4 ; read the 055D : 1101_0010_0000_0000_0000_0100 1620: lra4 r4 055E : 1101_0010_0000_0000_0000_0100 1621: add r13, r4, r13 ; add the 055F : 1000_0010_1101_0000_1000_1101 1622: sra+ r13 ; and stor 0560 : 0011_1000_1101_0000_0000_0000 1623: nop 0561 : 0000_0000_0000_0000_0000_0000 1624: lra4 r4 ; load the 0562 : 1101_0010_0000_0000_0000_0100 1625: lra4 r4 0563 : 1101_0010_0000_0000_0000_0100 1626: adc r4, c0, r4 ; add the 0564 : 1000_0110_0100_0110_0000_0100 1627: sra+ r4 ; and writ 0565 : 0011_1000_0100_0000_0000_0000 1628: swp r15, r15 ; swap the 0566 : 0111_1010_0000_0001_1110_1111 1629: jmp cc_uncond, rstack ; return f 0567 : 0000_1000_1000_0000_0000_1111 1630: 1631: raw_ADCzero: 1632: mov 0x400, r4 ; set the 0568 : 1100_0110_1000_0000_0000_0100 1633: or r5, r4, r5 ; to preve 0569 : 1010_1010_0101_0000_1000_0101 1634: jmp cc_uncond, raw_ADCcor 056A : 0000_0100_0000_0000_0000_1111 1635: ;################# 1636: ;# END data transf 1637: ;################# 1638: 1639: nop 056B : 0000_0000_0000_0000_0000_0000 1640: 1641: 1642: ;############################################## 1643: ;# This is our HCM header[0], stored always in D 1644: ;############################################## 1645: 1646: raw_hc0: 1647: #ifdef cpu0 1648: iext 0xF0F0 056C : 0101_0000_0000_0000_0000_1111 1649: mov 0xF0F0, rio ; the HC h 056D : 1100_0110_0001_1110_0000_1110 1650: shl 2, h_0, r0 ; the head 056E : 1011_0010_0010_0111_1110_0000 1651: or r0, c1, r0 ; last two 056F : 1010_1010_0000_0110_0010_0000 1652: sgio+ r0 0570 : 0011_1100_0000_0000_0000_0000 1653: mov 0x7, r1 ; prepare 0571 : 1100_0110_0000_0000_1110_0001 1654: spio r0 NODP ; NI trans 0572 : 0010_0000_0000_0000_0000_0000 1655: shl -12, h_0, r0 ; the numb 0573 : 1011_0011_0100_0111_1110_0000 1656: and r0, r1, r1 0574 : 1010_0110_0000_0000_0010_0001 1657: jmp cc_zero, raw_no_add_header 0575 : 0000_0100_0000_0000_0001_0001 1658: 1659: ; prepare h[1] 1660: shl 8, nsamples, r0 ; timebins 0576 : 1011_0010_1000_0111_1010_0000 1661: shl 8, r0, r0 0577 : 1011_0010_1000_0000_0000_0000 1662: 1663: or r0, g5, r0 ; timebins 0578 : 1010_1010_0000_0010_1010_0000 1664: shl 4, r0, r0 0579 : 1011_0010_0100_0000_0000_0000 1665: 1666: or r0, g7, r0 ; timebins 057A : 1010_1010_0000_0010_1110_0000 1667: shl 4, r0, r0 057B : 1011_0010_0100_0000_0000_0000 1668: 1669: or r0, g6, r0 ; timebins 057C : 1010_1010_0000_0010_1100_0000 1670: shl 2, r0, r0 057D : 1011_0010_0010_0000_0000_0000 1671: 1672: or r0, c1, r0 ; timebins 057E : 1010_1010_0000_0110_0010_0000 1673: 1674: spio r0 NODP ; NI trans 057F : 0010_0000_0000_0000_0000_0000 1675: sgio+ r0 0580 : 0011_1100_0000_0000_0000_0000 1676: 1677: cmp r1, 2 0581 : 1100_1000_0001_0000_0000_0010 1678: jmp cc_ltu, raw_no_add_header 0582 : 0000_0100_0000_0000_0001_0000 1679: ; SVN revisions header h[3] 1680: mov FIT_SVN_REV, r0 0583 : 1100_0110_1111_0011_1010_0000 1681: shl 13, r0, r0 0584 : 1011_0010_1101_0000_0000_0000 1682: mov ASM_SVN_REV, r1 0585 : 1100_0110_0000_0000_0000_0001 1683: or r0, r1, r0 0586 : 1010_1010_0000_0000_0010_0000 1684: shl 6, r0, r0 0587 : 1011_0010_0110_0000_0000_0000 1685: mov 0x35, r1 0588 : 1100_0110_0000_0110_1010_0001 1686: or r0, r1, r0 0589 : 1010_1010_0000_0000_0010_0000 1687: spio r0 NODP ; NI trans 058A : 0010_0000_0000_0000_0000_0000 1688: sgio+ r0 058B : 0011_1100_0000_0000_0000_0000 1689: raw_no_add_header: 1690: nop 058C : 0000_0000_0000_0000_0000_0000 1691: #endif 1692: 1693: #ifdef cpu1 1694: ; prepare the BC counter 1695: lpio CTPDOUT, r0 1696: iext 0xFFFF 1697: mov 0xFFFF, r1 1698: and r0, r1, g5 1699: #endif 1700: 1701: #ifdef cpu2 1702: ; prepare the pretrigger phase 1703: lpio CTPDOUT, r0 1704: mov 0xF, r1 1705: and r0, r1, g6 1706: #endif 1707: 1708: #ifdef cpu3 1709: ; prepare the pretrigger counter 1710: lpio CTPDOUT, r0 1711: mov 0xF, r1 1712: and r0, r1, g7 1713: #endif 1714: 1715: #ifdef DBANKscsn 1716: swp rio, rio ; swap DBA 1717: #endif 1718: andt r2, c3 058D : 1010_0100_0010_0110_0110_0000 1719: jmp cc_zero, raw_complete_ni_tmsn ; check fo 058E : 0000_0100_0000_0000_0001_0001 1720: 1721: 1722: ;################################################# 1723: ;# 1724: ;# 0x5A0: Interrupt NI FIFO empty, irq10 1725: ;# 1726: ;################################################# 1727: 1728: ORG 0x5A0 1729: 1730: #ifdef cpu3 1731: nififoe: 1732: 1733: sgio r11, IRQHL3 1734: jmpr cc_busy, 0 1735: sgio r11, IRQHW3 1736: jmpr cc_busy, 0 1737: 1738: ; program the delay 1739: mov NI_tmsn_delay, r1 1740: spio r1, 0x200 1741: mov b1010_0101_1111, r1 ; counter, 1742: spio r1, 0x201 1743: ; enable IRQ local timer 1744: mov b0101_0101, r1 1745: sgio r1, IRQHL3 1746: jmpr cc_busy, 0 1747: sgio r1, IRQHW3 1748: jmpr cc_busy, 0 1749: jmp cc_uncond, raw_coff 1750: #endif 1751: 1752: ;################################################# 1753: ;# 1754: ;# 0x600: Interrupt Local Counter/Timer 1755: ;# 1756: ;################################################# 1757: 1758: ORG 0x600 1759: 1760: localtm: 1761: 1762: ; restore the interrupt mask 1763: sgio r11, IRQHL3 0600 : 0010_1000_1011_1011_0110_1111 1764: jmpr cc_busy, 0 0601 : 0000_0100_1100_0000_0011_0111 1765: sgio r11, IRQHW3 0602 : 0010_1000_1011_1011_0110_1110 1766: jmpr cc_busy, 0 0603 : 0000_0100_1100_0000_0111_0111 1767: 1768: ; send end signature 1769: jmp cc_uncond, raw_end_ni_tmsn 0604 : 0000_0100_0000_0000_0000_1111 1770: nop 0605 : 0000_0000_0000_0000_0000_0000 1771: 1772: ORG 0x700 1773: ; Style recommendations 1774: ; 1775: ; 1) use include for the different parts of the CP 1776: ; 1777: ; 2) use prefix in the labels, e.g. 1778: ; 1779: ; -- start of the acq subroutine 1780: ; acq: ... 1781: ; ... 1782: ; acq_store: 1783: ; ... 1784: ; acq_delay: 1785: ; ... 1786: ; -- end of the acq subroutine 1787: 1788: ; ADDITIONAL PROGRAMS 1789: ; 1790: ; GENERAL RULES 1791: ; 1792: ; 1) The programs do not use any programmable cons 1793: ; 2) CPU3 is never used 1794: ; 3) The programs use for data exchange a small re 1795: ; or DMEM or IMEM3, accessible through GIO. The 1796: ; must be defined in the main program as follow 1797: ; 1798: ; srv_command - command from the SCSN master, 1799: ; srv_indata - input data, stored by the SCSN 1800: ; srv_outdata - output data, stored by the TRA 1801: ; 1802: ; 4) The programs may modify all registers (privat 1803: ; 1804: ; 5) The programs end with command low power to th 1805: ; This can be changed later - may be is reasona 1806: ; IRT (interrupt return) or just jump to some a 1807: ; 1808: ; 6) By default the configuration of the main prog 1809: ; but sets the start address to a small assembl 1810: ; 1811: ; 7) When the SCSN master wants to start some serv 1812: ; TRAP to the low power state, then modify the 1813: ; - store the correct start address of the serv 1814: ; stores its request at srv_command and activat 1815: ; the state of the TRAP and sends it to low pow 1816: ; After finishing the service operation (which 1817: ; the SCSN master restores the IVT to the origi 1818: 1819: 1820: ; J2C 1821: #ifdef cpu0 *** Include file "j2c.asm" 1: ; TCK is bit 0, TMS is bit 1, TDI/O is bit 2 2: 3: 4: #def tdi_off = b011; 5: 6: ; TMS is bit 1 7: #def tms_1 = b010; 8: #def tms_0 = b101; 9: 10: ; TCK is bit 0 11: #def tck_1 = b001; 12: #def tck_0 = b110; 13: 14: ; TDI is bit 2 15: #def tdi_1 = b100; 16: #def tdi_0 = b011; 17: 18: ; TDO is bit 2 19: #def tdo_msk = b100; 20: #def tdo_pos = -2; 21: 22: ;#def j2c_timed = 10; 23: #def MaxLoop = 0xFFF 24: ;#def looptest = 1; 25: 26: #def oportd = r15; 27: #def j2c_wrk = r0; 28: #def return1 = r8; 29: #def return2 = r7; 30: #def return3 = r6; 31: #def dat2send = r2; 32: #def bit2send = r3; 33: #def rec_data = r4; 34: 35: tst: 36: 37: #ifdef looptest 38: mov MaxLoop, r12 39: shl 8, r12, r12 40: mov 0, r14 ; error counter 41: 42: j2c_loop: 43: mov 0xFF, r13 44: and r12, r13, r13 45: 46: ; only to see the LEDs 47: mov 0x80, j2c_wrk 48: or j2c_wrk, r13, r13 49: 50: shl 4, r13, r13 51: mov b1001, r11 52: or r11, r13, r11 ; data to 53: iext srv_command ; the addr 54: sgio r11, srv_command 55: jmpr cc_busy, 0 56: ; start, write 57: mvpcr +2, return1 58: jmp cc_uncond, j2c_cmd 59: 60: mov b0101, r11 61: iext srv_command ; the addr 62: sgio r11, srv_command 63: jmpr cc_busy, 0 64: ; start, read 65: mvpcr +2, return1 66: jmp cc_uncond, j2c_cmd 67: 68: shl -4, r13, r13 69: cmp r13, rec_data 70: jmpr cc_eq, +2 71: add r14, c1, r14 72: 73: ; delay just to see the LEDs 74: mov 0xFFF, j2c_wrk 75: shl 8, j2c_wrk, j2c_wrk 76: sub j2c_wrk, c1, j2c_wrk 77: jmpr cc_nzero, -1 78: 79: sub r12, c1, r12 80: jmp cc_nzero, j2c_loop 81: 82: iext srv_outdata ; the addr 83: sgio r14, srv_outdata ; the addr 84: jmpr cc_busy, 0 85: 86: #else 87: mvpcr +2, return1 0700 : 1100_0110_1110_0000_0100_1000 88: jmp cc_uncond, j2c_cmd 0701 : 0000_0100_0000_0000_0000_1111 89: #endif 90: 91: ; low power 92: mov CMD_LP, j2c_wrk 0702 : 1100_0110_0000_0010_0100_0000 93: sgio j2c_wrk, SMCMD 0703 : 0010_1000_0000_1010_0000_0100 94: jmpr cc_uncond, 0 0704 : 0000_0100_1110_0000_1000_1111 95: nop 0705 : 0000_0000_0000_0000_0000_0000 96: 97: j2c_cmd: 98: ; INIT 99: mov tms_1, oportd 0706 : 1100_0110_0000_0000_0100_1111 100: iext SEBDOU 0707 : 0101_0000_0000_0000_0000_0011 101: sgio oportd, SEBDOU ; TCK=0, T 0708 : 0010_1000_1111_0001_0111_1001 102: 103: mov 7, j2c_wrk ; all enab 0709 : 1100_0110_0000_0000_1110_0000 104: jmpr cc_busy, 0 070A : 0000_0100_1110_0001_0101_0111 105: iext SEBDEN 070B : 0101_0000_0000_0000_0000_0011 106: sgio j2c_wrk, SEBDEN 070C : 0010_1000_0000_0001_0111_1000 107: jmpr cc_busy, 0 070D : 0000_0100_1110_0001_1011_0111 108: 109: ; copy the command & data 110: iext srv_command 070E : 0101_0000_0000_0000_0000_1111 111: lgio 0, srv_command 070F : 1110_1100_1111_0000_1110_0000 112: jmpr cc_busy, 0 0710 : 0000_0100_1110_0010_0001_0111 113: lpio 0x300, dat2send 0711 : 1110_0110_0110_0000_0000_0010 114: 115: ; send the command 116: mov 4, bit2send ; 4 bits t 0712 : 1100_0110_0000_0000_1000_0011 117: mvpcr +2, return2 ; return a 0713 : 1100_0110_1110_0010_1010_0111 118: jmp cc_uncond, j2c_sendd ; send 4 b 0714 : 0000_0100_0000_0000_0000_1111 119: 120: ; set TDI high 121: mvpcr +2, return3 0715 : 1100_0110_1110_0010_1110_0110 122: jmp cc_uncond, j2c_set_tdi ; TDI=1 0716 : 0000_0100_0000_0000_0000_1111 123: 124: mvpcr +2, return2 ; return a 0717 : 1100_0110_1110_0011_0010_0111 125: jmp cc_uncond, j2c_tmsp ; tms puls 0718 : 0000_0100_0000_0000_0000_1111 126: 127: ; send/receive data 128: mov 8, bit2send ; 8 bits t 0719 : 1100_0110_0000_0001_0000_0011 129: mvpcr +2, return2 ; return a 071A : 1100_0110_1110_0011_1000_0111 130: jmp cc_uncond, j2c_sendd ; send 8 b 071B : 0000_0100_0000_0000_0000_1111 131: 132: ; enable the data output, TDI=0 and make a 133: ; set TDI low 134: mvpcr +2, return3 071C : 1100_0110_1110_0011_1100_0110 135: jmp cc_uncond, j2c_clr_tdi ; TDI=0 071D : 0000_0100_0000_0000_0000_1111 136: 137: mvpcr +2, return2 ; return a 071E : 1100_0110_1110_0100_0000_0111 138: jmp cc_uncond, j2c_tmsp ; tms puls 071F : 0000_0100_0000_0000_0000_1111 139: 140: ; store the result back 141: jmpr cc_busy, 0 0720 : 0000_0100_1110_0100_0001_0111 142: iext srv_outdata 0721 : 0101_0000_0000_0000_0000_1111 143: sgio rec_data, srv_outdata 0722 : 0010_1000_0100_0000_1111_0000 144: jmpr cc_busy, 0 0723 : 0000_0100_1110_0100_0111_0111 145: jmp cc_uncond, return1 0724 : 0000_1000_1000_0000_0000_1111 146: nop 0725 : 0000_0000_0000_0000_0000_0000 147: 148: ; send a bitstream using TCK and TDI and receive t 149: ; 150: ; The slave pulls TDI low only when TCK=1 and its 151: ; 152: ; The master pulls TDI low before the rising edge 153: ; 154: ; The master stores the TDI before the falling edg 155: ; 156: ; data to be sent : dat2send 157: ; bits to be sent : bit2send 158: ; received data : rec_data 159: ; 160: ; Data are sent LSB first, 4 bit command and 8 bit 161: j2c_sendd: 162: 163: mvpcr +2, return3 0726 : 1100_0110_1110_0101_0000_0110 164: jmp cc_uncond, j2c_ena_tdi 0727 : 0000_0100_0000_0000_0000_1111 165: 166: mvpcr +4, return3 0728 : 1100_0110_1110_0101_1000_0110 167: shl -1, dat2send, dat2send 0729 : 1011_0011_1111_0000_0100_0010 168: jmp cc_carry, j2c_set_tdi 072A : 0000_0100_0000_0000_0001_0000 169: jmp cc_uncond, j2c_clr_tdi 072B : 0000_0100_0000_0000_0000_1111 170: 171: #ifdef j2c_timed 172: mvpcr +2, return3 173: jmp cc_uncond, j2c_delay 174: #endif 175: 176: ; rising edge of TCK -- TDI must be active 177: ; TDO in simulation must be weak pull up/d 178: 179: mvpcr +2, return3 072C : 1100_0110_1110_0101_1100_0110 180: jmp cc_uncond, j2c_set_tck 072D : 0000_0100_0000_0000_0000_1111 181: 182: mvpcr +2, return3 072E : 1100_0110_1110_0110_0000_0110 183: jmp cc_uncond, j2c_dis_tdi 072F : 0000_0100_0000_0000_0000_1111 184: 185: #ifdef j2c_timed 186: mvpcr +2, return3 187: jmp cc_uncond, j2c_delay 188: #endif 189: 190: iext SEBDIN ; read the 0730 : 0101_0000_0000_0000_0000_0011 191: lgio 0, SEBDIN 0731 : 1110_1100_0011_0001_0111_1010 192: jmpr cc_busy, 0 0732 : 0000_0100_1110_0110_0101_0111 193: lpio 0x300, j2c_wrk 0733 : 1110_0110_0110_0000_0000_0000 194: ; mov tdo_msk, r4 195: ; and r4, j2c_wrk, j2c_wrk 196: #ifdef tdo_pos 197: shl tdo_pos, j2c_wrk, j2c_wrk 0734 : 1011_0011_1110_0000_0000_0000 198: #endif 199: and j2c_wrk, c1, j2c_wrk 0735 : 1010_0110_0000_0110_0010_0000 200: shl 7, j2c_wrk, j2c_wrk ; now the 0736 : 1011_0010_0111_0000_0000_0000 201: shl -1, rec_data, rec_data ; shift ri 0737 : 1011_0011_1111_0000_1000_0100 202: or j2c_wrk, rec_data, rec_data ; put the 0738 : 1010_1010_0000_0000_1000_0100 203: 204: ; falling edge of TCK 205: mvpcr +2, return3 0739 : 1100_0110_1110_0111_0110_0110 206: jmp cc_uncond, j2c_clr_tck 073A : 0000_0100_0000_0000_0000_1111 207: 208: sub bit2send, c1, bit2send ; dec the 073B : 1000_1010_0011_0110_0010_0011 209: jmp cc_nzero, j2c_sendd ; loop 073C : 0000_0100_0000_0000_0000_0001 210: 211: mvpcr +2, return3 073D : 1100_0110_1110_0111_1110_0110 212: jmp cc_uncond, j2c_ena_tdi 073E : 0000_0100_0000_0000_0000_1111 213: 214: jmp cc_uncond, return2 ; return 073F : 0000_1000_0111_0000_0000_1111 215: 216: 217: ; make a negative strobe pulse at TMS 218: ; return address in return2 219: j2c_tmsp: 220: ; falling edge of TCK 221: mvpcr +2, return3 0740 : 1100_0110_1110_1000_0100_0110 222: jmp cc_uncond, j2c_clr_tms 0741 : 0000_0100_0000_0000_0000_1111 223: 224: #ifdef j2c_timed 225: mvpcr +2, return3 226: jmp cc_uncond, j2c_delay 227: #endif 228: 229: mvpcr +2, return3 0742 : 1100_0110_1110_1000_1000_0110 230: jmp cc_uncond, j2c_set_tms 0743 : 0000_0100_0000_0000_0000_1111 231: 232: jmp cc_uncond, return2 ; return 0744 : 0000_1000_0111_0000_0000_1111 233: 234: #ifdef j2c_timed 235: j2c_delay: 236: mov j2c_timed, j2c_wrk 237: sub j2c_wrk, c1, j2c_wrk 238: jmpr cc_nzero, -1 239: jmp cc_uncond, return3 240: #endif 241: 242: j2c_set_tck: 243: mov tck_1, j2c_wrk 0745 : 1100_0110_0000_0000_0010_0000 244: jmp cc_uncond, j2c_set_ttt 0746 : 0000_0100_0000_0000_0000_1111 245: 246: j2c_clr_tck: 247: mov tck_0, j2c_wrk 0747 : 1100_0110_0000_0000_1100_0000 248: jmp cc_uncond, j2c_clr_ttt 0748 : 0000_0100_0000_0000_0000_1111 249: 250: j2c_set_tms: 251: mov tms_1, j2c_wrk 0749 : 1100_0110_0000_0000_0100_0000 252: jmp cc_uncond, j2c_set_ttt 074A : 0000_0100_0000_0000_0000_1111 253: 254: j2c_clr_tms: 255: mov tms_0, j2c_wrk 074B : 1100_0110_0000_0000_1010_0000 256: jmp cc_uncond, j2c_clr_ttt 074C : 0000_0100_0000_0000_0000_1111 257: 258: j2c_set_tdi: 259: mov tdi_1, j2c_wrk 074D : 1100_0110_0000_0000_1000_0000 260: jmp cc_uncond, j2c_set_ttt 074E : 0000_0100_0000_0000_0000_1111 261: 262: j2c_clr_tdi: 263: mov tdi_0, j2c_wrk 074F : 1100_0110_0000_0000_0110_0000 264: jmp cc_uncond, j2c_clr_ttt 0750 : 0000_0100_0000_0000_0000_1111 265: 266: j2c_set_ttt: 267: or oportd, j2c_wrk, oportd 0751 : 1010_1010_1111_0000_0000_1111 268: iext SEBDOU 0752 : 0101_0000_0000_0000_0000_0011 269: sgio oportd, SEBDOU 0753 : 0010_1000_1111_0001_0111_1001 270: jmpr cc_busy, 0 0754 : 0000_0100_1110_1010_1001_0111 271: jmp cc_uncond, return3 ; return 0755 : 0000_1000_0110_0000_0000_1111 272: 273: j2c_clr_ttt: 274: and oportd, j2c_wrk, oportd 0756 : 1010_0110_1111_0000_0000_1111 275: iext SEBDOU 0757 : 0101_0000_0000_0000_0000_0011 276: sgio oportd, SEBDOU 0758 : 0010_1000_1111_0001_0111_1001 277: jmpr cc_busy, 0 0759 : 0000_0100_1110_1011_0011_0111 278: jmp cc_uncond, return3 ; return 075A : 0000_1000_0110_0000_0000_1111 279: 280: j2c_ena_tdi: 281: mov 7, j2c_wrk 075B : 1100_0110_0000_0000_1110_0000 282: iext SEBDEN 075C : 0101_0000_0000_0000_0000_0011 283: sgio j2c_wrk, SEBDEN 075D : 0010_1000_0000_0001_0111_1000 284: jmpr cc_busy, 0 075E : 0000_0100_1110_1011_1101_0111 285: jmp cc_uncond, return3 ; return 075F : 0000_1000_0110_0000_0000_1111 286: 287: j2c_dis_tdi: 288: mov tdi_off, j2c_wrk 0760 : 1100_0110_0000_0000_0110_0000 289: iext SEBDEN 0761 : 0101_0000_0000_0000_0000_0011 290: sgio j2c_wrk, SEBDEN 0762 : 0010_1000_0000_0001_0111_1000 291: jmpr cc_busy, 0 0763 : 0000_0100_1110_1100_0111_0111 292: jmp cc_uncond, return3 ; return 0764 : 0000_1000_0110_0000_0000_1111 293: nop 0765 : 0000_0000_0000_0000_0000_0000 *** End of include file src/j2c.asm 1823: #endif 1824: 1825: #ifdef cpu1 1826: #inc "I2C.asm" 1827: #endif 1828: 1829: org 0xE00 *** Include file "adc2cpu.asm" Error reading src/adc2cpu.asm