// 1-pretrigger, 2-clear, 3-reserved, 4-low power, 5-acq, 6-test, 7-pasa pulse
//pretrigger 2
include src/scsn_ids.tcs
include src/defines.tcs
include src/parameters.tcs
include wrk/cpu0_labels.tcs
include wrk/cpu1_labels.tcs
include wrk/cpu2_labels.tcs
include wrk/cpu3_labels.tcs
nop
// read status
//expect 127, 0x0A04, 0x300000a0
// start
restrict PASAPULSE
pretrigger 7
restrict 1-PASAPULSE
pretrigger 1
restrict 1
wait 200;
// read status
//expect 127, 0x0A04, 0x300000a0
// read event counters
//read 127, C12CPUA
// clear
// 1-pretrigger, 2-clear, 3-reserved, 4-low power, 5-acq, 6-test, 7-pasa pulse
//pretrigger 2
// read status
//expect 127, NFSM, 1

restrict USE_J2C

write chip_jtag, FILCLK, 1;     // enable filter clock cont.
write chip_jtag, SMCMD, CMD_LP; // stop

// not correct!
//const   nw16 = npackets*2*(nwords*4+2+2);
//Nrob=1+(1-SINGLEROB)*3;
Nrob=1;
//                            MCMhd      tracklet endm rawdata endm hchd
const   nw16 = (16*(nsamples*21/3+1)*Nrob + 2          +2           +1 + hc_0_add_hd_words)*2;

expect chip_jtag, SMCMD, lp_state

write chip_mode, SEBDOU, mode_jtag;
//write chip_mode, SEBDEN, 11b;

// set the IRQ tst to J2C routine
write chip_jtag,  IA0+IRQ_TST, lbl_TST_cpu0;   // set int_clr start addr for cpu0

cmd = 0000b;            // read at address 0
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
expect chip_jtag, srv_outdata, nw16 & 0xFF
expect chip_jtag, SMCMD, lp_state

cmd = 0001b;            // read at address 1
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
expect chip_jtag, srv_outdata, (fault_ltc << 7) | (nw16 >> 8);
expect chip_jtag, SMCMD, lp_state

cmd = 0010b;            // read at address 2
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
expect chip_jtag, srv_outdata, (fault_ltc << 7)
expect chip_jtag, SMCMD, lp_state

cmd = 0011b;            // read at address 3
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
expect chip_jtag, srv_outdata, (fault_ltc << 7)
expect chip_jtag, SMCMD, lp_state

restrict 0
cmd = 0100b;            // read at address 4
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
expect chip_jtag, srv_outdata, reg_j2c
expect chip_jtag, SMCMD, lp_state

// clear the counters

cmd = 1001b;            // write at address 0
data = reg_j2c;         // sel_p/s
write chip_jtag, srv_command, cmd | (data << 4);
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
wait 15
expect chip_jtag, SMCMD, lp_state

// restore the IRQ tst address => switch CPU clock off
write chip_jtag, IA0+IRQ_TST, lbl_LPW_cpu0;   // set int_clr start addr for cpu0
write chip_jtag, SMCMD, CMD_ACQ; // start again
expect chip_jtag, SMCMD, 0x300000a0

restrict 1

read 127, 0x0B82