Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.3, Apr 2004 Please send any comments to: angelov@kip.uni-heidelberg.de 13:44:46 / 19 Aug 2006 Source code file: src/DDDtst.asm Memory initialisation file: Log file: wrk/cpu1.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU1 = 2 CC_SIGNED = 0X14 3 CC_NSIGNED = 0X04 4 CC_ZERO = 0X11 5 CC_NZERO = 0X01 6 CC_OVERFL = 0X13 7 CC_NOVERFL = 0X03 8 CC_NEG = 0X12 9 CC_NNEG = 0X02 10 CC_CARRY = 0X10 11 CC_NCARRY = 0X00 12 CC_BUSY = 0X17 13 CC_NBUSY = 0X07 14 CC_DIVB = 0X15 15 CC_NDIVB = 0X05 16 CC_ERRDIV = 0X16 17 CC_NERRDIV = 0X06 18 CC_UNCOND = 0X0F 19 CC_EQ = 0X11 20 CC_NEQ = 0X01 21 CC_NEG = 0X12 22 CC_POS0 = 0X02 23 CC_LTS = 0X14 24 CC_GES = 0X04 25 CC_LTU = 0X10 26 CC_GEU = 0X00 27 CC_LES = 0X19 28 CC_GTS = 0X09 29 CC_LEU = 0X18 30 CC_GTU = 0X08 31 RR_BYTE = 3 32 RR_WORD = 1 33 RR_DWORD = 0 34 LRA1 = LRA 3, 35 LRA2 = LRA 1, 36 LRA4 = LRA 0, 37 LRA4+ = LRA+ 0, 38 XOR = EOR 39 NOT = COM 40 SHLT = SHL 41 ANDT = AND 42 R0 = PRF[0] 43 R1 = PRF[1] 44 R2 = PRF[2] 45 R3 = PRF[3] 46 R4 = PRF[4] 47 R5 = PRF[5] 48 R6 = PRF[6] 49 R7 = PRF[7] 50 R8 = PRF[8] 51 R9 = PRF[9] 52 R10 = PRF[10] 53 R11 = PRF[11] 54 R12 = PRF[12] 55 R13 = PRF[13] 56 R14 = PRF[14] 57 R15 = PRF[15] 58 G0 = GRF[0] 59 G1 = GRF[1] 60 G2 = GRF[2] 61 G3 = GRF[3] 62 G4 = GRF[4] 63 G5 = GRF[5] 64 G6 = GRF[6] 65 G7 = GRF[7] 66 G8 = GRF[8] 67 G9 = GRF[9] 68 G10 = GRF[10] 69 G11 = GRF[11] 70 G12 = GRF[12] 71 G13 = GRF[13] 72 G14 = GRF[14] 73 G15 = GRF[15] 74 F0 = FIT[0] 75 F1 = FIT[1] 76 F2 = FIT[2] 77 F3 = FIT[3] 78 F4 = FIT[4] 79 F5 = FIT[5] 80 F6 = FIT[6] 81 F7 = FIT[7] 82 F8 = FIT[8] 83 F9 = FIT[9] 84 F10 = FIT[10] 85 F11 = FIT[11] 86 F12 = FIT[12] 87 F13 = FIT[13] 88 F14 = FIT[14] 89 F15 = FIT[15] 90 C0 = CON[0] 91 C1 = CON[1] 92 C2 = CON[2] 93 C3 = CON[3] 94 C4 = CON[4] 95 C5 = CON[5] 96 C6 = CON[6] 97 C7 = CON[7] 98 C8 = CON[8] 99 C9 = CON[9] 100 C10 = CON[10] 101 C11 = CON[11] 102 C12 = CON[12] 103 C13 = CON[13] 104 C14 = CON[14] 105 C15 = CON[15] 1: 2: ; Test program for simultaneous reading of the DME 3: ; all DMEM lockations by cpu3 via local bus. Then 4: ; the data red to grf[3]. All cpus simultaneously 5: ; the result with grf[3]. The errors occured are a 6: ; for cpu(n). 7: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 31: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 32: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 33: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 34: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 35: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 36: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 37: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 38: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 39: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 40: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 41: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 42: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 43: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 44: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 45: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 46: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 47: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 48: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 49: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 50: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 51: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 52: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 53: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 54: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 55: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 56: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 57: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 58: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 59: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 60: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 61: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 62: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 63: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 64: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 65: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 66: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 67: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 68: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 69: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 70: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 71: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 72: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 73: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 74: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 75: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 76: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 77: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 78: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 79: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 80: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 81: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 82: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 83: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 84: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 85: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 86: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 87: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 88: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 89: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 90: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 91: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 92: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 93: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 94: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 95: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 96: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 97: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 98: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 99: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 100: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 101: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 102: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 103: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 104: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 105: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 106: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 107: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 108: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 109: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 110: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 111: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 112: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 113: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 114: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 115: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 116: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 117: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 118: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 119: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 120: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 121: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 122: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 123: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 124: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 125: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 126: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 127: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 128: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 129: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 130: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 131: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 132: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 133: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 134: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 135: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 136: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 137: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 138: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 139: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 140: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 141: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 142: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 143: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 144: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 145: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 146: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 147: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 148: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 149: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 150: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 151: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 152: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 153: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 154: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 155: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 156: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 157: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 158: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 159: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 160: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 161: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 162: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 163: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 164: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 165: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 166: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 167: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 168: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 169: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 170: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 171: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 172: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 173: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 174: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 175: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 176: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 177: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 178: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 179: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 180: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 181: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 182: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 183: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 184: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 185: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 186: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 187: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 188: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 189: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 190: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 191: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 192: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 193: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 194: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 195: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 196: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 197: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 198: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 199: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 200: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 201: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 202: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 203: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 204: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 205: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 206: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 207: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 208: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 209: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 210: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- *** End of include file /cad/tools/bin/conf_va.inc 9: 10: #def DALAST=0xFFC 11: #def DAFIRST=0x0 12: #def DBFIRST=0xF000 13: #def DBLAST=0xF100 14: #def DMDELA_val = 8; 15: #def DMDELS_val = 11; 16: 17: #def dmdel = r14; DMDELA=r14 & 0xF, DMDELS=r14 18: 19: 20: nop 0000 : 0000_0000_0000_0000_0000_0000 21: iext 0xF000 0001 : 0101_0000_0000_0000_0000_1111 22: mov 0xF000 r14 0002 : 1100_0110_0000_0000_0000_1110 23: #ifdef cpu3 24: not c0, r0 25: wini: sgio+ r0 26: nop 27: nop 28: iext 0xF100 29: cmp r14, 0xF100 30: jmp cc_leu, wini 31: iext DBFIRST 32: mov DBFIRST r14 33: ; jmp cc_uncond, go_lp 34: #endif 35: 36: ; LOOP for DMDELA and DMDELS 37: nextpar: 38: nop 0003 : 0000_0000_0000_0000_0000_0000 39: #ifdef cpu3 40: mov DMDELA_val, r0 ; write with fixed values 41: mov r14, r0 ; or write with the loop values 42: iext DMDELA 43: sgio r0, DMDELA 44: jmpr cc_busy, 0 45: mov DMDELS_val, r0 ; write with the fixed values 46: shl -4, r14, r0 ; or write with the loop values 47: iext DMDELS 48: sgio r0, DMDELS 49: #endif 50: 51: mov 0 r10 ; error counter 0004 : 1100_0110_0000_0000_0000_1010 52: sem 0x8 ; mask for synch 0005 : 0001_0000_0000_0000_0000_1000 53: #ifdef cpu3 54: 55: mov b1_0_0_00_01_11111 r0 ; initializ 56: spio r0 0x201 ; generator 57: iext 0xAAAAAAAA 58: mov 0xAAAAAAAA r0 59: spio r0 0x200 60: 61: mov DALAST r13 62: mov DAFIRST r15 63: 64: nxt0: sra+ r0 65: not r0, r0 66: cmp r13 r15 67: jmp cc_nzero nxt0 68: 69: mov DALAST r13 70: mov DAFIRST r15 71: 72: nxt: lpio 0x202 r0 73: sra+ r0 74: nop 75: cmp r13 r15 76: jmp cc_nzero nxt 77: mov c0 g3 78: #else 79: syn 0006 : 0000_1100_0000_0000_0000_0000 80: #endif ; all cpus expec 81: 82: mov DAFIRST r15 0007 : 1100_0110_0000_0000_0000_1111 83: mov DALAST r13 0008 : 1100_0111_1111_1111_1000_1101 84: sem 0x8 0009 : 0001_0000_0000_0000_0000_1000 85: #ifdef cpu3 86: mov b1_0_0_00_01_11111 r0 ; initializ 87: spio r0 0x201 ; generator 88: iext 0xAAAAAAAA 89: mov 0xAAAAAAAA r0 90: spio r0 0x200 91: ; init the DMDELA and S 92: iext DMDELA 93: sgio r14, DMDELA 94: shl -4, r14, r0 95: jmpr cc_busy, 0 96: iext DMDELS 97: sgio r0, DMDELS 98: 99: nop 100: mov c0 g3 101: #else 102: syn 000A : 0000_1100_0000_0000_0000_0000 103: #endif ; all cpus expec 104: 105: cyc: sem 0x8 000B : 0001_0000_0000_0000_0000_1000 106: 107: #ifdef cpu3 ; generate again the pseudorandom seq 108: 109: 110: lpio 0x202 r0 111: nop 112: 113: mov r0 g3 114: #else 115: syn 000C : 0000_1100_0000_0000_0000_0000 116: #endif 117: 118: #ifdef cpu0qq 119: nop 120: #endif 121: lra4 r0 000D : 1101_0010_0000_0000_0000_0000 122: lra4+ r0 000E : 1111_0010_0000_0000_0000_0000 123: cmp r0 g3 000F : 1000_1000_0000_0010_0110_0000 124: jmpr cc_zero 2 0010 : 0000_0100_0000_0010_0101_0001 125: add r10 c1 r10 0011 : 1000_0010_1010_0110_0010_1010 126: cmp r13 r15 0012 : 1000_1000_1101_0001_1110_0000 127: jmp cc_nzero cyc 0013 : 0000_0100_0000_0000_0000_0001 128: 129: ; truncate the result (number of errors) to 8 bits 130: cmp r10, 255 0014 : 1100_1000_1010_0000_1111_1111 131: jmpr cc_leu, +2 0015 : 0000_0100_0000_0010_1111_1000 132: mov 255, r10 0016 : 1100_0110_0001_1111_1110_1010 133: 134: #ifdef cpu0 135: sem 0x8 ; mask for synch 136: mov r10, g0 137: syn 138: jmp cc_uncond, nextpar 139: #endif 140: #ifdef cpu1 141: sem 0x8 ; mask for synch 0017 : 0001_0000_0000_0000_0000_1000 142: shl 8, r10, g1 0018 : 1011_0010_1000_0001_0101_0001 143: syn 0019 : 0000_1100_0000_0000_0000_0000 144: jmp cc_uncond, nextpar 001A : 0000_0100_0000_0000_0000_1111 145: #endif 146: #ifdef cpu2 147: sem 0x8 ; mask for synch 148: shl 8, r10, r10 149: shl 8, r10, g2 150: syn 151: jmp cc_uncond, nextpar 152: #endif 153: #ifdef cpu3 154: ; wait a bit... 155: nop 156: nop 157: nop 158: nop 159: nop 160: shl 8, r10, r10 161: shl 8, r10, r10 162: shl 8, r10, r10 163: ; put all error counters into r10 164: or r10, g0, r10 165: or r10, g1, r10 166: or r10, g2, r10 167: ; store the error counter in DBK 168: sgio+ r10 169: nop 170: nop 171: mov c0, g3 172: ; check if all combinations are tested 173: iext DBLAST 174: cmp r14, DBLAST 175: jmp cc_ltu, nextpar 176: go_lp: 177: ; switch off 178: mov 0x12 r0 179: jmpr cc_busy 0 180: sgio r0 0xA04 181: #endif 182: jmpr cc_uncond 0 001B : 0000_0100_0000_0011_0110_1111 Source file read, 0 error(s), 0 warning(s).