Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.7, Jul 2008 SVN Revision 2158, SVN Date 2008-07-17 Please send any comments to: angelov@kip.uni-heidelberg.de 10:26:04 / 19 Nov 2008 Source code file: src/fit.asm Memory initialisation file: Log file: wrk/cpu2.log Program memory size in words: 4096 Default constants, read from /usr/share/trap/asm_mimd.inc 1 CPU2 = 2 CC_SIGNED = 0X14 3 CC_NSIGNED = 0X04 4 CC_ZERO = 0X11 5 CC_NZERO = 0X01 6 CC_OVERFL = 0X13 7 CC_NOVERFL = 0X03 8 CC_NEG = 0X12 9 CC_NNEG = 0X02 10 CC_CARRY = 0X10 11 CC_NCARRY = 0X00 12 CC_BUSY = 0X17 13 CC_NBUSY = 0X07 14 CC_DIVB = 0X15 15 CC_NDIVB = 0X05 16 CC_ERRDIV = 0X16 17 CC_NERRDIV = 0X06 18 CC_UNCOND = 0X0F 19 CC_EQ = 0X11 20 CC_NEQ = 0X01 21 CC_NEG = 0X12 22 CC_POS0 = 0X02 23 CC_LTS = 0X14 24 CC_GES = 0X04 25 CC_LTU = 0X10 26 CC_GEU = 0X00 27 CC_LES = 0X19 28 CC_GTS = 0X09 29 CC_LEU = 0X18 30 CC_GTU = 0X08 31 RR_BYTE = 3 32 RR_WORD = 1 33 RR_DWORD = 0 34 LRA1 = LRA 3, 35 LRA2 = LRA 1, 36 LRA4 = LRA 0, 37 LRA4+ = LRA+ 0, 38 XOR = EOR 39 NOT = COM 40 SHLT = SHL 41 ANDT = AND 42 R0 = PRF[0] 43 R1 = PRF[1] 44 R2 = PRF[2] 45 R3 = PRF[3] 46 R4 = PRF[4] 47 R5 = PRF[5] 48 R6 = PRF[6] 49 R7 = PRF[7] 50 R8 = PRF[8] 51 R9 = PRF[9] 52 R10 = PRF[10] 53 R11 = PRF[11] 54 R12 = PRF[12] 55 R13 = PRF[13] 56 R14 = PRF[14] 57 R15 = PRF[15] 58 G0 = GRF[0] 59 G1 = GRF[1] 60 G2 = GRF[2] 61 G3 = GRF[3] 62 G4 = GRF[4] 63 G5 = GRF[5] 64 G6 = GRF[6] 65 G7 = GRF[7] 66 G8 = GRF[8] 67 G9 = GRF[9] 68 G10 = GRF[10] 69 G11 = GRF[11] 70 G12 = GRF[12] 71 G13 = GRF[13] 72 G14 = GRF[14] 73 G15 = GRF[15] 74 F0 = FIT[0] 75 F1 = FIT[1] 76 F2 = FIT[2] 77 F3 = FIT[3] 78 F4 = FIT[4] 79 F5 = FIT[5] 80 F6 = FIT[6] 81 F7 = FIT[7] 82 F8 = FIT[8] 83 F9 = FIT[9] 84 F10 = FIT[10] 85 F11 = FIT[11] 86 F12 = FIT[12] 87 F13 = FIT[13] 88 F14 = FIT[14] 89 F15 = FIT[15] 90 C0 = CON[0] 91 C1 = CON[1] 92 C2 = CON[2] 93 C3 = CON[3] 94 C4 = CON[4] 95 C5 = CON[5] 96 C6 = CON[6] 97 C7 = CON[7] 98 C8 = CON[8] 99 C9 = CON[9] 100 C10 = CON[10] 101 C11 = CON[11] 102 C12 = CON[12] 103 C13 = CON[13] 104 C14 = CON[14] 105 C15 = CON[15] 106 ASM_SVN_REV = 2158 *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt tttt tttt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt tttt tttt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt tttt tttt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snme eeee ddd 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc cccc cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- ---- --St oam 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- ---- --St oam 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- ---- --St oam 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- ---- --St oam 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- ---- --St oam 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- ---- --St oam 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- ---- --St oam 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- ---- --St oam 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- ---- --St oam 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- ---- --St oam 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- ---- --St oam 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- ---- --St oam 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- ---- ---- --- 30: 31: #def CTGDINI=0x0B80; dddd dddd dddd dddd dddd dddd dddd dddd 32: #def CTGCTRL=0x0B81; ---- ---- ---- ---- ---S idce essb bbbb 33: #def CTGDOUT=0x0B82; DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 34: #def CTPDINI=0x0200; dddd dddd dddd dddd dddd dddd dddd dddd 35: #def CTPCTRL=0x0201; ---- ---- ---- ---- ---S idce essb bbbb 36: #def CTPDOUT=0x0202; DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 37: 38: #def PASADEL=0x3158; ---- ---- ---- ---- ---- ---- aaaa aaa 39: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- ---- --aa aaa 40: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- ---- --aa aaa 41: #def PASADAC=0x315B; ---- ---- ---- ---- ---- ---- aaaa aaa 42: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaaa aaaa aaa 43: #def PASASTL=0x315D; ---- ---- ---- ---- ---- ---- aaaa aaa 44: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- ---- ---- --- 45: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- ---- ---- --- 46: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaaa aaaa aaa 47: #def ADCINB=0x3051; ---- ---- ---- ---- ---- ---- ---- --m 48: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- ---- ---d ddd 49: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssbz hhhe app 50: #def ADCTST=0x3054; ---- ---- ---- ---- ---- ---- ---- --t 51: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- ---- ---- --- 52: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- ---- ---- --- 53: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- ---- ---- --- 54: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- ---- ---- -aa 55: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- ---- -ret aii 56: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaaa aaaa aaa 57: #def SADCEC=0x3166; ---- ---- ---- ---- ---- ---- -daa ate 58: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --AA AAAA AAA 59: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --AA AAAA AAA 60: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --AA AAAA AAA 61: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --AA AAAA AAA 62: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --AA AAAA AAA 63: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --AA AAAA AAA 64: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --AA AAAA AAA 65: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --AA AAAA AAA 66: #def SADCMC=0x3170; ---- ---- ---- ---- ---- ---- aaaa aaa 67: #def SADCOC=0x3171; ---- ---- ---- ---- ---- ---- aaaa aaa 68: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd cccc bbbb aaa 69: #def SADCTC=0x3173; ---- ---- ---- ---- ---- ---- ---- -aa 70: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -eaa aaaa aaa 71: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- ---- ---- -ee 72: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- ---- ---- -oo 73: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- ---- ---- -ii 74: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAAA AAAA AAA 75: #def TPPT0=0x3000; ---- ---- ---- ---- ---- ---- -ddd ddd 76: #def TPPAE=0x3004; ---- ---- ---- ---- ---- ---- -ddd ddd 77: #def TPPGR=0x3003; ---- ---- ---- ---- ---- ---- -ddd ddd 78: #def FLBY=0x3018; ---- ---- ---- ---- ---- ---- ---- --- 79: #def FLL=0x3100; ---- ---- ---- ---- ---- ---- --dd ddd 80: #def FPBY=0x3019; ---- ---- ---- ---- ---- ---- ---- --- 81: #def FPTC=0x3020; ---- ---- ---- ---- ---- ---- ---- --d 82: #def FPNP=0x3021; ---- ---- ---- ---- ---- ---d dddd ddd 83: #def FPCL=0x3022; ---- ---- ---- ---- ---- ---- ---- --- 84: #def FPA=0x3060; --dd dddd dddd dddd dddd dddd dddd ddd 85: #def FGBY=0x301A; ---- ---- ---- ---- ---- ---- ---- --- 86: #def FGFn=0x3080; ---- ---- ---- ---- ---- ---d dddd ddd 87: #def FGAn=0x30A0; ---- ---- ---- ---- ---- ---- --dd ddd 88: #def FGTA=0x3028; ---- ---- ---- ---- ---- dddd dddd ddd 89: #def FGTB=0x3029; ---- ---- ---- ---- ---- dddd dddd ddd 90: #def FGCL=0x302A; ---- ---- ---- ---- ---- ---- ---- --- 91: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd dddd dddd ddd 92: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd dddd dddd ddd 93: #def FTBY=0x301B; ---- ---- ---- ---- ---- ---- ---- --- 94: #def FTAL=0x3030; ---- ---- ---- ---- ---- --dd dddd ddd 95: #def FTLL=0x3031; ---- ---- ---- ---- ---- --dd dddd ddd 96: #def FTLS=0x3032; ---- ---- ---- ---- ---- --dd dddd ddd 97: #def FCBY=0x301C; ---- ---- ---- ---- ---- ---- ---- --- 98: #def FCWn=0x3038; ---- ---- ---- ---- ---- ---- dddd ddd 99: #def TPFS=0x3001; ---- ---- ---- ---- ---- ---- -ddd ddd 100: #def TPFE=0x3002; ---- ---- ---- ---- ---- ---- -ddd ddd 101: #def TPQS0=0x3005; ---- ---- ---- ---- ---- ---- -ddd ddd 102: #def TPQE0=0x3006; ---- ---- ---- ---- ---- ---- -ddd ddd 103: #def TPQS1=0x3007; ---- ---- ---- ---- ---- ---- -ddd ddd 104: #def TPQE1=0x3008; ---- ---- ---- ---- ---- ---- -ddd ddd 105: #def TPHT=0x3041; ---- ---- ---- ---- --dd dddd dddd ddd 106: #def TPVBY=0x3043; ---- ---- ---- ---- ---- ---- ---- --- 107: #def TPVT=0x3042; ---- ---- ---- ---- ---- ---- --dd ddd 108: #def TPFP=0x3040; ---- ---- ---- ---- ---- ---- --dd ddd 109: #def TPL=0x3180; ---- ---- ---- ---- ---- ---- ---d ddd 110: #def TPCL=0x3045; ---- ---- ---- ---- ---- ---- ---d ddd 111: #def TPCT=0x3044; ---- ---- ---- ---- ---- ---- ---d ddd 112: #def TPD=0x3047; ---- ---- ---- ---- ---- ---- ---- ddd 113: #def TPH=0x3140; ---- ---- ---- ---- ---- ---- ---d ddd 114: #def TPCBY=0x3046; ---- ---- ---- ---- ---- ---- ---- --- 115: #def TPCI0=0x3048; ---- ---- ---- ---- ---- ---- ---d ddd 116: #def TPCI1=0x3049; ---- ---- ---- ---- ---- ---- ---d ddd 117: #def TPCI2=0x304A; ---- ---- ---- ---- ---- ---- ---d ddd 118: #def TPCI3=0x304B; ---- ---- ---- ---- ---- ---- ---d ddd 119: #def EBD=0x3009; ---- ---- ---- ---- ---- ---- ---- -dd 120: #def EBSF=0x300C; ---- ---- ---- ---- ---- ---- ---- --- 121: #def EBAQA=0x300A; ---- ---- ---- ---- ---- ---- -ddd ddd 122: #def EBSIM=0x300D; ---- ---- ---- ---- ---- ---- ---- --- 123: #def EBSIA=0x300B; ---- ---- ---- ---- ---- ---- -ddd ddd 124: #def EBR=0x0800; ---- ---- ---- ---- ---- -pdd dddd ddd 125: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pdd dddd ddd 126: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pdd dddd ddd 127: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pdd dddd ddd 128: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pdd dddd ddd 129: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pdd dddd ddd 130: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pdd dddd ddd 131: #def EBW=0x2000; ---- ---- ---- ---- ---- --dd dddd ddd 132: #def EBPP=0x300E; ---- ---- ---- ---- ---- ---- ---- --- 133: #def EBPC=0x300F; ---- ---- ---- ---- ---- ---- ---- --- 134: #def EBP0=0x3010; ---- ---- ---- ---- ---- ---d dddd ddd 135: #def EBP1=0x3011; ---- ---- ---- ---- ---- ---d dddd ddd 136: #def EBP2=0x3012; ---- ---- ---- ---- ---- ---d dddd ddd 137: #def EBP3=0x3013; ---- ---- ---- ---- ---- ---d dddd ddd 138: #def EBIS=0x3014; ---- ---- ---- ---- ---- --dd dddd ddd 139: #def EBIT=0x3015; ---- ---- ---- ---- ---- dddd dddd ddd 140: #def EBIL=0x3016; ---- ---- ---- ---- ---- ---- dddd ddd 141: #def EBIN=0x3017; ---- ---- ---- ---- ---- ---- ---- --- 142: #def EBI=0x0980; dddd dddd dddd dddd dddd dddd dddd ddd 143: #def EBI0=0x0980; dddd dddd dddd dddd dddd dddd dddd dd 144: #def EBI1=0x0981; dddd dddd dddd dddd dddd dddd dddd dd 145: #def EBI2=0x0982; dddd dddd dddd dddd dddd dddd dddd dd 146: #def EBI3=0x0983; dddd dddd dddd dddd dddd dddd dddd dd 147: #def EBI4=0x0984; dddd dddd dddd dddd dddd dddd dddd dd 148: #def EBI5=0x0985; dddd dddd dddd dddd dddd dddd dddd dd 149: #def EBI6=0x0986; dddd dddd dddd dddd dddd dddd dddd dd 150: #def EBI7=0x0987; dddd dddd dddd dddd dddd dddd dddd dd 151: #def EBI8=0x0988; dddd dddd dddd dddd dddd dddd dddd dd 152: #def EBI9=0x0989; dddd dddd dddd dddd dddd dddd dddd dd 153: #def EBIA=0x098A; dddd dddd dddd dddd dddd dddd dddd dd 154: #def EBIB=0x098B; dddd dddd dddd dddd dddd dddd dddd dd 155: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- ---- ---- wwr 156: #def MEMRW=0xD000; ---- ---- ---- ---- ---- ---- -www wrr 157: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- ---b dddd iii 158: #def DMDELA=0xD002; ---- ---- ---- ---- ---- ---- ---- aaa 159: #def DMDELS=0xD003; ---- ---- ---- ---- ---- ---- ---- sss 160: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 161: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 162: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 163: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 164: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 165: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 166: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 167: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 168: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaaa aaaa aaa 169: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaaa aaaa aaa 170: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaaa aaaa aaa 171: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaaa aaaa aaa 172: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmmm mmmm mmm 173: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmmm mmmm mmm 174: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmmm mmmm mmm 175: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmmm mmmm mmm 176: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmmm mmmm mmm 177: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmmm mmmm mmm 178: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmmm mmmm mmm 179: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmmm mmmm mmm 180: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmmm mmmm mmm 181: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmmm mmmm mmm 182: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmmm mmmm mmm 183: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmmm mmmm mmm 184: #def NMOD=0x0D40; ---- ---- ---- ---- ---- ---- ---i cmm 185: #def NTRO=0x0D43; ---- ---- ---- --ii iddd cccb bbaa aff 186: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt tttt tttt ttt 187: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbbb aaaa aaa 188: #def NRRO=0x0D44; ---- ---- ---- --ii iddd cccb bbaa aff 189: #def NTP=0x0D46; pppp pppp pppp pppp pppp pppp pppp ppp 190: #def NP0=0x0D48; ---- ---- ---- ---- ---- -ppp pfff fec 191: #def NP1=0x0D49; ---- ---- ---- ---- ---- -ppp pfff fec 192: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -ppp pfff fec 193: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -ppp pfff fec 194: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLLL CCCC CCC 195: #def NED=0x0D42; ---- ---- ---- ---- orpp ppff ffcc css 196: #def NDLY=0x0D41; --jj jiii hhhg ggff feee dddc ccbb baa 197: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhhh llll lll 198: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DSS EHLZ YXW 199: #def NLE=0x00C2; ---- ---- ---- ---- ---- ---- EEEE EEE 200: #def NFE=0x0DC1; ---- ---- ---- ---- ---- ---- ---- DCB 201: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- ---- ---- --- 202: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- ---- ---S SSS 203: #def NITM0=0x0A08; ---- ---- ---- ---- --tt tttt tttt ttt 204: #def NITM1=0x0A09; ---- ---- ---- ---- --tt tttt tttt ttt 205: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt tttt tttt ttt 206: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt tttt tttt ttt 207: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd dddd dddd ddd 208: #def SMON=0x0A06; ---- ---- ---- ---- ---- dddd dddd ddd 209: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- dddd dddd ddd 210: #def NODP=0x0000; dddd dddd dddd dddd dddd dddd dddd ddd 211: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- ---- ---- 212: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- ---- ---- 213: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- ---- ---- 214: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- ---- ---- 215: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- ---- ---- 216: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- ---- ---- 217: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- ---- ---- 218: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- ---- ---- 219: #def GBUSR0=0x0300; -- readonly 220: #def GBUSR1=0x0301; -- readonly *** End of include file /usr/share/trap//conf_va.inc 2: 3: ; ---------------------------------------------------------- 4: ; -- 5: ; -- Test program for the readout board 6: ; -- For the ALICE TR-Detector at LHC 7: ; -- Kirchhoff Institut für Physik 8: ; -- Univesity of Heidelberg 9: ; -- Germany 10: ; -- 11: ; -- 03.09.2004 VA 12: ; ---------------------------------------------------------- 13: ; 14: ;#def ByteMode=1 15: #def fullprog=1 16: #def srv_command = 0xF0E0 17: #def srv_indata = 0xF0E1 18: #def srv_outdata = 0xF0F0 19: 20: ; number of words to send 21: #def nsamples =c12 22: ; the configuration reg of the psr_counter 23: #def psr_mode =c14 24: 25: ; start value for the data generation 26: #def psrg_ini =c8; 27: 28: #def endsig_rr= c15 ; end signature for raw data readout 29: #def endsig_tr= c10 ; end signature for tracklet data rea 30: 31: #ifdef cpu0 32: #def clk_onoff = CPU0SS; 33: #def psr_ini_gio = 0x0C00; 34: #endif 35: #ifdef cpu1 36: #def clk_onoff = CPU1SS; 37: #def psr_ini_gio = 0x0C08; 38: #endif 39: #ifdef cpu2 40: #def clk_onoff = CPU2SS; 41: #def psr_ini_gio = 0x0C10; 42: #endif 43: #ifdef cpu3 44: #def clk_onoff = CPU3SS; 45: #def psr_ini_gio = 0x0C18; 46: #endif 47: 48: ORG 0x0 49: lpw: 50: nop 0000 : 0000_0000_0000_0000_0000_0000 51: nop 0001 : 0000_0000_0000_0000_0000_0000 52: nop 0002 : 0000_0000_0000_0000_0000_0000 53: ; low power 54: mov 0, r0 0003 : 1100_0110_0000_0000_0000_0000 55: sgio r0, clk_onoff 0004 : 0010_1000_0000_1010_0010_0101 56: jmpr cc_uncond, 0 0005 : 0000_0100_0000_0000_1010_1111 57: nop 0006 : 0000_0000_0000_0000_0000_0000 58: 59: #ifdef fullprog 60: ; IRQ clr 61: ORG 0x100; 62: clr: nop 0100 : 0000_0000_0000_0000_0000_0000 63: #ifdef cpu0 64: mov cmd_ext_clr r0 65: mov c9 r5 66: or r5, r5, r5 67: jmp cc_zero clr_wt 68: sub r5 c1 r5 69: sgio r5 0xC01 70: jmpr cc_busy 0 71: or r5, r5, r5 72: jmp cc_zero clr_wt 73: sgio r0 SMCMD ; clear ready 74: mov cmd_pretrigg r0 75: nop 76: sgio r0 SMCMD 77: #endif 78: #ifdef cpu2 79: mov b1111_0101_0000, r1 0101 : 1100_0111_1110_1010_0000_0001 80: jmpr cc_busy, 0 0102 : 0000_0100_0010_0000_0101_0111 81: ; sgio r1, SMOFF ; switch off all NI LVDS cells 82: #endif 83: clr_wt: 84: jmpr cc_uncond, 0 0103 : 0000_0100_0010_0000_0110_1111 85: nop 0104 : 0000_0000_0000_0000_0000_0000 86: 87: ORG 0x200; 88: acq: nop 0200 : 0000_0000_0000_0000_0000_0000 89: shl 8, c5, r8 0201 : 1011_0010_1000_0110_1010_1000 90: add r8, c13, r8 0202 : 1000_0010_1000_0111_1010_1000 91: 92: ; -- some delay 93: mov 31, r0 0203 : 1100_0110_0000_0011_1110_0000 94: acq_delay: 95: sub r0, c1, r0 0204 : 1000_1010_0000_0110_0010_0000 96: jmp cc_nzero, acq_delay 0205 : 0000_0100_0000_0000_0000_0001 97: 98: mov c10 r0 0206 : 1100_0010_0000_0111_0100_0000 99: shl 8, r0, r0 0207 : 1011_0010_1000_0000_0000_0000 100: shl 8, r0, r0 0208 : 1011_0010_1000_0000_0000_0000 101: add r0, c10, r0 0209 : 1000_0010_0000_0111_0100_0000 102: ; or r0, r8, r0 103: ; start address in GIO of the DBANK 104: iext 0xF000 020A : 0101_0000_0000_0000_0000_1111 105: mov 0xF000, r14 020B : 1100_0110_0000_0000_0000_1110 106: add r14, c5, r14 020C : 1000_0010_1110_0110_1010_1110 107: ; start address in DMEM 108: shl 2, c5, r15 020D : 1011_0010_0010_0110_1010_1111 109: 110: ;acq_send: 111: spio r0 NODP ; then send to the NI 020E : 0010_0000_0000_0000_0000_0000 112: #ifdef cpu0 113: sgio+ r0 ; store to DBANK 114: sra+ r0 ; store to DMEM 115: #endif 116: #ifdef cpu1 117: sgio+ r0 ; store to DBANK 118: sra+ r0 ; store to DMEM 119: #endif 120: 121: jmpr cc_uncond 0 020F : 0000_0100_0100_0001_1110_1111 122: nop 0210 : 0000_0000_0000_0000_0000_0000 123: 124: ORG 0x400 125: raw: nop 0400 : 0000_0000_0000_0000_0000_0000 126: ; IRQ raw data read 127: #ifdef cpu0 128: mov cmd_CPU_done r0 129: sgio r0 SMCMD; 130: #endif 131: ; start address in GIO of DBANK 132: mov nsamples, r1 0401 : 1100_0010_0000_0111_1000_0001 133: mul32 r1, c5, r1 0402 : 1001_0000_0001_0110_1010_1001 134: iext 0xF002 0403 : 0101_0000_0000_0000_0000_1111 135: mov 0xF002, r14 0404 : 1100_0110_0000_0000_0100_1110 136: add r14, r1, r14 0405 : 1000_0010_1110_0000_0010_1110 137: 138: #ifdef ByteMode 139: mov 0x0FF, r3; mask 140: #else 141: iext 0xFFFF; 0406 : 0101_0000_0000_0000_0000_1111 142: mov 0xFFFF, r3; mask 0407 : 1100_0111_1111_1111_1110_0011 143: #endif 144: ; start address in DMEM 145: mov 8, r15 0408 : 1100_0110_0000_0001_0000_1111 146: shl 2, r1, r1 0409 : 1011_0010_0010_0000_0010_0001 147: add r1, r15, r15 040A : 1000_0010_0001_0001_1110_1111 148: 149: mov 0, r4; number of words 040B : 1100_0110_0000_0000_0000_0100 150: mov nsamples, r9 040C : 1100_0010_0000_0111_1000_1001 151: ; configure the psr_counter 152: mov psr_mode, r1 040D : 1100_0010_0000_0111_1100_0001 153: spio r1, 0x201; 040E : 0010_0000_0001_0010_0000_0001 154: mov psrg_ini, r1 040F : 1100_0010_0000_0111_0000_0001 155: andt r1, r3 0410 : 1010_0100_0001_0000_0110_0000 156: #ifndef ByteMode 157: jmp cc_zero, raw_smp_test 0411 : 0000_0100_0000_0000_0001_0001 158: #endif 159: spio r1, 0x200; initial data 0412 : 0010_0000_0001_0010_0000_0000 160: nop 0413 : 0000_0000_0000_0000_0000_0000 161: 162: raw_wfull: 163: #ifdef ByteMode 164: and r1, r3, r1; bits 7..0 165: mov r1, r2 166: add r1, c1, r1 167: and r1, r3, r1; bits 7..0 168: shl 8, r1, r5 169: or r5, r2, r2; bits 15..8 170: 171: add r1, c1, r1 172: and r1, r3, r1; bits 7..0 173: shl 8, r1, r5 174: shl 8, r5, r5 175: or r5, r2, r2; bits 23..16 176: 177: add r1, c1, r1 178: and r1, r3, r1; bits 7..0 179: shl 8, r1, r5 180: shl 8, r5, r5 181: shl 8, r5, r5 182: or r5, r2, r2; bits 31..24 183: add r1, c1, r1 184: #else 185: lpio 0x202, r1; read from PSRG 0414 : 1110_0110_0100_0000_0100_0001 186: and r1, r3, r1; take only bits 0..15 0415 : 1010_0110_0001_0000_0110_0001 187: nop 0416 : 0000_0000_0000_0000_0000_0000 188: lpio 0x202, r2; read from PSRG 0417 : 1110_0110_0100_0000_0100_0010 189: shl 8, r2, r2; shift to 16..31 0418 : 1011_0010_1000_0000_0100_0010 190: shl 8, r2, r2 0419 : 1011_0010_1000_0000_0100_0010 191: or r2, r1, r2; merge with bits 16..31 041A : 1010_1010_0010_0000_0010_0010 192: #endif 193: spio r2, NODP; store to NI 041B : 0010_0000_0010_0000_0000_0000 194: sgio+ r2; store to DBANK 041C : 0011_1100_0010_0000_0000_0000 195: sra+ r2; store to DMEM 041D : 0011_1000_0010_0000_0000_0000 196: add r4, c1, r4; inc the number of words 041E : 1000_0010_0100_0110_0010_0100 197: 198: ; !!! In some TRAPs we have timing problems with the compare 199: ; Therefore here is double 200: 201: cmp r4, nsamples; check if ready 041F : 1000_1000_0100_0111_1000_0000 202: cmp r4, r9 ; check if ready 0420 : 1000_1000_0100_0001_0010_0000 203: 204: jmp cc_ltu, raw_wfull 0421 : 0000_0100_0000_0000_0001_0000 205: ; store the next word as start for the next pretrigg 206: lpio 0x202, r2 0422 : 1110_0110_0100_0000_0100_0010 207: jmpr cc_busy, 0 0423 : 0000_0100_1000_0100_0111_0111 208: sgio r2, psr_ini_gio 0424 : 0010_1000_0010_1100_0001_0000 209: 210: jmp cc_uncond, raw_sendem 0425 : 0000_0100_0000_0000_0000_1111 211: 212: raw_smp_test: 213: shl -1, r9, r8; the half of the data words t 0426 : 1011_0011_1111_0001_0010_1000 214: shl -8 r1, r1 0427 : 1011_0011_1000_0000_0010_0001 215: shl -8 r1, r2 0428 : 1011_0011_1000_0000_0010_0010 216: swp r2, r1 0429 : 0111_1010_0000_0000_0100_0001 217: or r2, r1, r1 042A : 1010_1010_0010_0000_0010_0001 218: raw_wfulls: 219: spio r1, NODP; store to NI 042B : 0010_0000_0001_0000_0000_0000 220: sgio+ r1; store to DBANK 042C : 0011_1100_0001_0000_0000_0000 221: sra+ r1; store to DMEM 042D : 0011_1000_0001_0000_0000_0000 222: add r4, c1, r4; inc the number of words 042E : 1000_0010_0100_0110_0010_0100 223: cmp r4, r8 042F : 1000_1000_0100_0001_0000_0000 224: jmpr cc_nzero, +2 0430 : 0000_0100_1000_0110_0100_0001 225: not r1, r1 0431 : 1011_1110_0000_0000_0010_0001 226: cmp r4, r9 0432 : 1000_1000_0100_0001_0010_0000 227: jmp cc_ltu, raw_wfulls 0433 : 0000_0100_0000_0000_0001_0000 228: 229: ; send end mark 230: raw_sendem: 231: mov endsig_rr, r0 0434 : 1100_0010_0000_0111_1110_0000 232: spio r0, NODP 0435 : 0010_0000_0000_0000_0000_0000 233: #ifdef cpu3 ; only cpu3 to get the end marker at the 234: jmpr cc_busy, 0 235: sgio+ r0; store to DBANK 236: sra+ r0; store to DMEM 237: jmpr cc_busy, 0 238: sgio+ r0; store to DBANK 239: sra+ r0; store to DMEM 240: #endif 241: jmpr cc_busy, 0 0436 : 0000_0100_1000_0110_1101_0111 242: 243: ; switch power off 244: mov 0, r0 0437 : 1100_0110_0000_0000_0000_0000 245: sgio r0 clk_onoff ; each cpu stops its clock 0438 : 0010_1000_0000_1010_0010_0101 246: jmpr cc_uncond 0 0439 : 0000_0100_1000_0111_0010_1111 247: nop 043A : 0000_0000_0000_0000_0000_0000 248: 249: #else 250: clr: nop 251: acq: nop 252: raw: nop 253: jmpr cc_uncond, 0 254: #endif 255: 256: 257: ORG 0x700 258: ; Style recommendations 259: ; 260: ; 1) use include for the different parts of the CPU program 261: ; 262: ; 2) use prefix in the labels, e.g. 263: ; 264: ; -- start of the acq subroutine 265: ; acq: ... 266: ; ... 267: ; acq_store: 268: ; ... 269: ; acq_delay: 270: ; ... 271: ; -- end of the acq subroutine 272: 273: ; ADDITIONAL PROGRAMS 274: ; 275: ; GENERAL RULES 276: ; 277: ; 1) The programs do not use any programmable constants 278: ; 2) CPU3 is never used 279: ; 3) The programs use for data exchange a small region in th 280: ; or DMEM or IMEM3, accessible through GIO. The start add 281: ; must be defined in the main program as follows: 282: ; 283: ; srv_command - command from the SCSN master, code of th 284: ; srv_indata - input data, stored by the SCSN master 285: ; srv_outdata - output data, stored by the TRAP CPU 286: ; 287: ; 4) The programs may modify all registers (privat and globa 288: ; 289: ; 5) The programs end with command low power to the global s 290: ; This can be changed later - may be is reasonable to hav 291: ; IRT (interrupt return) or just jump to some address. 292: ; 293: ; 6) By default the configuration of the main program enable 294: ; but sets the start address to a small assembler code to 295: ; 296: ; 7) When the SCSN master wants to start some service progra 297: ; TRAP to the low power state, then modify the IVT (inter 298: ; - store the correct start address of the service progra 299: ; stores its request at srv_command and activates IRQ TST 300: ; the state of the TRAP and sends it to low power state i 301: ; After finishing the service operation (which can consis 302: ; the SCSN master restores the IVT to the original. 303: 304: 305: ; J2C 306: #ifdef cpu0 307: #inc "j2c.asm" 308: #endif 309: 310: #ifdef cpu1 311: #inc "I2C.asm" 312: #endif 313: 314: #ifdef cpu2 315: ;#inc "jtag.asm" 316: tst: nop 0700 : 0000_0000_0000_0000_0000_0000 317: #endif Source file read, 0 error(s), 0 warning(s).