Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.7, Jul 2008 SVN Revision 2158, SVN Date 2008-07-17 Please send any comments to: angelov@kip.uni-heidelberg.de 17:11:19 / 12 Nov 2008 Source code file: src/IRQtst.asm Memory initialisation file: Log file: wrk/cpu2.log Program memory size in words: 4096 Default constants, read from /usr/share/trap/asm_mimd.inc 1 CPU2 = 2 CC_SIGNED = 0X14 3 CC_NSIGNED = 0X04 4 CC_ZERO = 0X11 5 CC_NZERO = 0X01 6 CC_OVERFL = 0X13 7 CC_NOVERFL = 0X03 8 CC_NEG = 0X12 9 CC_NNEG = 0X02 10 CC_CARRY = 0X10 11 CC_NCARRY = 0X00 12 CC_BUSY = 0X17 13 CC_NBUSY = 0X07 14 CC_DIVB = 0X15 15 CC_NDIVB = 0X05 16 CC_ERRDIV = 0X16 17 CC_NERRDIV = 0X06 18 CC_UNCOND = 0X0F 19 CC_EQ = 0X11 20 CC_NEQ = 0X01 21 CC_NEG = 0X12 22 CC_POS0 = 0X02 23 CC_LTS = 0X14 24 CC_GES = 0X04 25 CC_LTU = 0X10 26 CC_GEU = 0X00 27 CC_LES = 0X19 28 CC_GTS = 0X09 29 CC_LEU = 0X18 30 CC_GTU = 0X08 31 RR_BYTE = 3 32 RR_WORD = 1 33 RR_DWORD = 0 34 LRA1 = LRA 3, 35 LRA2 = LRA 1, 36 LRA4 = LRA 0, 37 LRA4+ = LRA+ 0, 38 XOR = EOR 39 NOT = COM 40 SHLT = SHL 41 ANDT = AND 42 R0 = PRF[0] 43 R1 = PRF[1] 44 R2 = PRF[2] 45 R3 = PRF[3] 46 R4 = PRF[4] 47 R5 = PRF[5] 48 R6 = PRF[6] 49 R7 = PRF[7] 50 R8 = PRF[8] 51 R9 = PRF[9] 52 R10 = PRF[10] 53 R11 = PRF[11] 54 R12 = PRF[12] 55 R13 = PRF[13] 56 R14 = PRF[14] 57 R15 = PRF[15] 58 G0 = GRF[0] 59 G1 = GRF[1] 60 G2 = GRF[2] 61 G3 = GRF[3] 62 G4 = GRF[4] 63 G5 = GRF[5] 64 G6 = GRF[6] 65 G7 = GRF[7] 66 G8 = GRF[8] 67 G9 = GRF[9] 68 G10 = GRF[10] 69 G11 = GRF[11] 70 G12 = GRF[12] 71 G13 = GRF[13] 72 G14 = GRF[14] 73 G15 = GRF[15] 74 F0 = FIT[0] 75 F1 = FIT[1] 76 F2 = FIT[2] 77 F3 = FIT[3] 78 F4 = FIT[4] 79 F5 = FIT[5] 80 F6 = FIT[6] 81 F7 = FIT[7] 82 F8 = FIT[8] 83 F9 = FIT[9] 84 F10 = FIT[10] 85 F11 = FIT[11] 86 F12 = FIT[12] 87 F13 = FIT[13] 88 F14 = FIT[14] 89 F15 = FIT[15] 90 C0 = CON[0] 91 C1 = CON[1] 92 C2 = CON[2] 93 C3 = CON[3] 94 C4 = CON[4] 95 C5 = CON[5] 96 C6 = CON[6] 97 C7 = CON[7] 98 C8 = CON[8] 99 C9 = CON[9] 100 C10 = CON[10] 101 C11 = CON[11] 102 C12 = CON[12] 103 C13 = CON[13] 104 C14 = CON[14] 105 C15 = CON[15] 106 ASM_SVN_REV = 2158 1: ; Full test of IRQ-locations. Each cpu tests its IRQ-locatio 2: ; DEFINITIONS, USED IN THE PROGRAM CODE: 3: 4: #def work=PRF[1] ; register for current operations (CO) 5: #def rdata=PRF[2] ; data red by test_programs and CO 6: #def tdata=PRF[3] ; test_vector to be writen 7: #def errnum=PRF[4] ; contains the number of err_ors 8: #def return1=PRF[5] ; return address (at first level) 9: #def return2=PRF[6] ; return address (at second level) 10: #def return3=PRF[7] ; return address (at third level) 11: #def tdgen=PRF[8] ; test data generator code label 12: #def itdgen=PRF[9] ; init tdgen code label 13: #def psrmask=PRF[10] ; mask for test_vector 14: #def bitnum=PRF[12] ; =32 minus the number of bits of the 15: ; prf11 and prf13 are used inside the testing routine 16: 17: #def ioaddr=PRF[14] ; contains the autoincrementing addres 18: #def errstore=PRF[15] ; autoincrement address for RAM-access 19: 20: #def firstaddress=grf[1] ; first address of the tested area 21: #def lastaddress=grf[2] ; last address of the tested area 22: 23: #def MEMRW=0xD000 ; the address of the register, control 24: #def IAFIRST=0xE000 ; first address of IMEM 25: #def IADEND =0xEFFF ; last address of IMEM 26: #def DAFRSTG=0xE000 ; first address of DMEM via GIO 27: #def DADENDG=0xE3FF ; last address of DMEM via GIO 28: #def DAFIRST=0x0000 ; first address of DMEM as RAM 29: #def DADEND =0x0FFC ; last address of DMEM as RAM 30: #def DBFST=0xF000 ; first address of DBANK (trap3) 31: #def DBEND=0xF0FF ; last address of DBANK (trap3) 32: 33: ; masks of certain length 34: #def BITMASK24=0x0FFFFFF 35: #def BITMASK32=0xFFFFFFFF 36: #def BITMASK12=0x00000FFF 37: #def BITMASK13=0x00001FFF 38: 39: #ifdef cpu0 40: #def BEGAD12=0xB20 41: #def EAD12=0xB2D 42: #def BEGAD13=0xB2D 43: #def EAD13=0xB30 44: #endif 45: #ifdef cpu1 46: #def BEGAD12=0xB40 47: #def EAD12=0xB4D 48: #def BEGAD13=0xB4D 49: #def EAD13=0xB50 50: #endif 51: #ifdef cpu2 52: #def BEGAD12=0xB60 53: #def EAD12=0xB6D 54: #def BEGAD13=0xB6D 55: #def EAD13=0xB70 56: #endif 57: #ifdef cpu3 58: #def BEGAD12=0xB00 59: #def EAD12=0xB0D 60: #def BEGAD13=0xB0D 61: #def EAD13=0xB10 62: #endif 63: 64: start: nop 0000 : 0000_0000_0000_0000_0000_0000 65: mov c0 errnum ; clear the err_or_ 0001 : 1100_0010_0000_0110_0000_0100 66: mov 0xB00 g0 0002 : 1100_0111_0110_0000_0001_0000 67: 68: iext 0xF000 0003 : 0101_0000_0000_0000_0000_1111 69: mov 0xF000 ioaddr 0004 : 1100_0110_0000_0000_0000_1110 70: mov EAD13 r0 0005 : 1100_0111_0110_1110_0000_0000 71: add ioaddr r0 r0 0006 : 1000_0010_1110_0000_0000_0000 72: sub r0 g0 r0 0007 : 1000_1010_0000_0010_0000_0000 73: 74: mov BEGAD12 work 0008 : 1100_0111_0110_1100_0000_0001 75: add ioaddr work ioaddr 0009 : 1000_0010_1110_0000_0010_1110 76: sub ioaddr g0 ioaddr 000A : 1000_1010_1110_0010_0000_1110 77: 78: mov c0 work 000B : 1100_0010_0000_0110_0000_0001 79: sgio+ work 000C : 0011_1100_0001_0000_0000_0000 80: jmpr cc_busy 0 000D : 0000_0100_0000_0001_1011_0111 81: cmp ioaddr r0 000E : 1000_1000_1110_0000_0000_0000 82: jmpr cc_leu -3 000F : 0000_0100_0000_0001_1001_1000 83: 84: iext BITMASK12 ; initiate for ICB1 0010 : 0101_0000_0000_0000_0000_0000 85: mov BITMASK12 psrmask 0011 : 1100_0111_1111_1111_1110_1010 86: mov 20 bitnum 0012 : 1100_0110_0000_0010_1000_1100 87: mov BEGAD12 firstaddress 0013 : 1100_0111_0110_1100_0001_0001 88: mov EAD12 lastaddress 0014 : 1100_0111_0110_1101_1011_0010 89: mvpcr +2 return1 ; call testing routi 0015 : 1100_0110_0000_0010_1110_0101 90: jmp cc_uncond cltst 0016 : 0000_0100_0000_0000_0000_1111 91: 92: ; jmpr cc_busy 0 ; storage of the num 93: ; iext 0xF000 94: ; mov 0xF000 work 95: ; add work c5 work 96: ; sgio errnum work 97: 98: iext BITMASK13 ; initiate for ICB1 0017 : 0101_0000_0000_0000_0000_0001 99: mov BITMASK13, psrmask 0018 : 1100_0111_1111_1111_1110_1010 100: mov 19 bitnum 0019 : 1100_0110_0000_0010_0110_1100 101: mov BEGAD13 firstaddress 001A : 1100_0111_0110_1101_1011_0001 102: mov EAD13 lastaddress 001B : 1100_0111_0110_1110_0001_0010 103: mvpcr +2 return1 ; call testing routi 001C : 1100_0110_0000_0011_1100_0101 104: jmp cc_uncond cltst 001D : 0000_0100_0000_0000_0000_1111 105: 106: ; jmpr cc_busy 0 ; storage of the num 107: ; iext 0xF004 108: ; mov 0xF004 work 109: ; add work c5 work 110: ; sgio errnum work 111: 112: jmpr cc_busy 0 ; begin reset the IC 001E : 0000_0100_0000_0011_1101_0111 113: mov c0 work 001F : 1100_0010_0000_0110_0000_0001 114: com work work 0020 : 1011_1110_0000_0000_0010_0001 115: sgio work BEGAD13 ; ... otherwise unc 0021 : 0010_1000_0001_1011_0110_1101 116: jmpr cc_busy 0 0022 : 0000_0100_0000_0100_0101_0111 117: mov c0 work 0023 : 1100_0010_0000_0110_0000_0001 118: mov EAD13 errnum 0024 : 1100_0111_0110_1110_0000_0100 119: sub errnum c2 errnum 0025 : 1000_1010_0100_0110_0100_0100 120: sgio work errnum 0026 : 0010_0100_0001_0000_1000_0000 121: jmpr cc_busy 0 0027 : 0000_0100_0000_0100_1111_0111 122: add errnum c1 errnum 0028 : 1000_0010_0100_0110_0010_0100 123: sgio work errnum ; ... end 0029 : 0010_0100_0001_0000_1000_0000 124: 125: #ifdef cpu3 126: jmpr cc_busy 0 127: mov b0_0111 work 128: sgio work 0xA26 129: jmpr cc_busy 0 130: mov 0x012 work 131: sgio work 0xA04 132: jmpr cc_uncond 0 133: #else 134: ; turns on cpu N+1 ... 135: mov c1 rdata 002A : 1100_0010_0000_0110_0010_0010 136: jmpr cc_busy 0 002B : 0000_0100_0000_0101_0111_0111 137: mov c1 ioaddr 002C : 1100_0010_0000_0110_0010_1110 138: add ioaddr c5 ioaddr 002D : 1000_0010_1110_0110_1010_1110 139: shl 1 ioaddr ioaddr 002E : 1011_0010_0001_0001_1100_1110 140: mov 0xA20 work 002F : 1100_0111_0100_0100_0000_0001 141: add ioaddr work ioaddr 0030 : 1000_0010_1110_0000_0010_1110 142: sgio rdata ioaddr 0031 : 0010_0100_0010_0001_1100_0000 143: jmpr cc_busy 0 0032 : 0000_0100_0000_0110_0101_0111 144: sub ioaddr c2 ioaddr 0033 : 1000_1010_1110_0110_0100_1110 145: mov c0 rdata 0034 : 1100_0010_0000_0110_0000_0010 146: sgio rdata ioaddr 0035 : 0010_0100_0010_0001_1100_0000 147: jmpr cc_uncond 0 0036 : 0000_0100_0000_0110_1100_1111 148: ; ... and stops itself 149: #endif cpu3 150: 151: ; SUBROUTINES BELOW 152: ; BEGIN THE TESTING ROUTINE (uses testing 153: cltst: mov 1 r11 0037 : 1100_0110_0000_0000_0010_1011 154: mov 1 r13 0038 : 1100_0110_0000_0000_0010_1101 155: 156: nt: mov wlk0 tdgen ; call walking 0 test_ro 0039 : 1100_0110_0000_0000_0000_1000 157: mov iwlk0 itdgen 003A : 1100_0110_0000_0000_0000_1001 158: mvpcr +2 return2 003B : 1100_0110_0000_0111_1010_0110 159: jmp cc_uncond tstgio 003C : 0000_0100_0000_0000_0000_1111 160: 161: mov wlk1 tdgen ; call walking 1 test_ro 003D : 1100_0110_0000_0000_0000_1000 162: mov iwlk1 itdgen ; 003E : 1100_0110_0000_0000_0000_1001 163: mvpcr +2 return2 003F : 1100_0110_0000_1000_0010_0110 164: jmp cc_uncond tstgio 0040 : 0000_0100_0000_0000_0000_1111 165: 166: mov psr tdgen ; call pseudo random vec 0041 : 1100_0110_0000_0000_0000_1000 167: mov ipsr itdgen 0042 : 1100_0110_0000_0000_0000_1001 168: mvpcr +2 return2 0043 : 1100_0110_0000_1000_1010_0110 169: jmp cc_uncond tstgio 0044 : 0000_0100_0000_0000_0000_1111 170: 171: add r13 c3 r13 ; next initial vectors for all 0045 : 1000_0010_1101_0110_0110_1101 172: shl 1 r11 r11 ; testing routines 0046 : 1011_0010_0001_0001_0110_1011 173: jmp cc_carry return1 0047 : 0000_1000_0101_0000_0001_0000 174: mov bitnum work 0048 : 1100_0010_0000_0001_1000_0001 175: mov 15 rdata 0049 : 1100_0110_0000_0001_1110_0010 176: mov r11 r0 004A : 1100_0010_0000_0001_0110_0000 177: cmp rdata bitnum 004B : 1000_1000_0010_0001_1000_0000 178: jmpr cc_ncarry 3 004C : 0000_0100_0000_1001_1110_0000 179: shl 15 r0 r0 004D : 1011_0010_1111_0000_0000_0000 180: sub work rdata work 004E : 1000_1010_0001_0000_0100_0001 181: shlt work r0 ; if MSB of the current regis 004F : 0111_0000_0001_0000_0000_0000 182: jmp cc_ncarry nt 0050 : 0000_0100_0000_0000_0000_0000 183: jmp cc_uncond return1 0051 : 0000_1000_0101_0000_0000_1111 184: 185: ; END OF THE TESTING ROUTINE 186: 187: 188: 189: ; BEGIN OF THE SUBROUTINE (used by testing routine 190: ; rolls all addresses and tests by w/r through GIO 191: tstgio: mvpcr +2 return3 0052 : 1100_0110_0000_1010_1000_0111 192: jmp cc_uncond itdgen ; go to init the test 0053 : 0000_1000_1001_0000_0000_1111 193: ; BEGIN WRITING THE T 194: mov firstaddress ioaddr 0054 : 1100_0010_0000_0010_0010_1110 195: wd: jmpr cc_busy 0 0055 : 0000_0100_0000_1010_1011_0111 196: sgio+ tdata ; writing the test da 0056 : 0011_1100_0011_0000_0000_0000 197: mvpcr +2 return3 ; runs the generator r 0057 : 1100_0110_0000_1011_0010_0111 198: jmp cc_uncond tdgen 0058 : 0000_1000_1000_0000_0000_1111 199: cmp ioaddr lastaddress ;IADEND ; is t 0059 : 1000_1000_1110_0010_0100_0000 200: jmp cc_carry wd ; if yes: 005A : 0000_0100_0000_0000_0001_0000 201: 202: ; BEGIN COMPARING PAR 203: mov firstaddress ioaddr 005B : 1100_0010_0000_0010_0010_1110 204: 205: mvpcr +2 return3 005C : 1100_0110_0000_1011_1100_0111 206: jmp cc_uncond itdgen ; and go to init for t 005D : 0000_1000_1001_0000_0000_1111 207: 208: wc: jmpr cc_busy 0 ; here is the body of 005E : 0000_0100_0000_1011_1101_0111 209: lgio+ 0 ; reading each address 005F : 1111_0100_0000_0000_0000_0000 210: jmpr cc_busy 0 ; comparing the result 0060 : 0000_0100_0000_1100_0001_0111 211: lpio 0x300 rdata ; data stored befor 0061 : 1110_0110_0110_0000_0000_0010 212: cmp rdata tdata ; 0062 : 1000_1000_0010_0000_0110_0000 213: jmp cc_zero noerr ; if err_or detected 0063 : 0000_0100_0000_0000_0001_0001 214: 215: 216: iext 0xF000 0064 : 0101_0000_0000_0000_0000_1111 217: mov 0xF000 work 0065 : 1100_0110_0000_0000_0000_0001 218: sub work c1 work 0066 : 1000_1010_0001_0110_0010_0001 219: add work ioaddr work 0067 : 1000_0010_0001_0001_1100_0001 220: sub work g0 work 0068 : 1000_1010_0001_0010_0000_0001 221: jmpr cc_busy 0 0069 : 0000_0100_0000_1101_0011_0111 222: lgio 0 work 006A : 1110_1000_0000_0000_0010_0000 223: jmpr cc_busy 0 006B : 0000_0100_0000_1101_0111_0111 224: lpio 0x300 errnum 006C : 1110_0110_0110_0000_0000_0100 225: nop 006D : 0000_0000_0000_0000_0000_0000 226: add errnum, c1, errnum ; 006E : 1000_0010_0100_0110_0010_0100 227: jmpr cc_busy 0 006F : 0000_0100_0000_1101_1111_0111 228: sgio errnum work 0070 : 0010_0100_0100_0000_0010_0000 229: 230: noerr: mvpcr +2 return3 0071 : 1100_0110_0000_1110_0110_0111 231: jmp cc_uncond tdgen ; get next test_data 0072 : 0000_1000_1000_0000_0000_1111 232: 233: cmp ioaddr lastaddress ; is tne last addres 0073 : 1000_1000_1110_0010_0100_0000 234: jmp cc_carry wc ; if not go to wc 0074 : 0000_0100_0000_0000_0001_0000 235: 236: jmp cc_uncond return2 0075 : 0000_1000_0110_0000_0000_1111 237: 238: ; prepares the next data - walking 1 239: wlk1: shl 1 tdata tdata 0076 : 1011_0010_0001_0000_0110_0011 240: and tdata psrmask tdata 0077 : 1010_0110_0011_0001_0100_0011 241: jmp cc_nzero return3 0078 : 0000_1000_0111_0000_0000_0001 242: mov c1 tdata 0079 : 1100_0010_0000_0110_0010_0011 243: jmp cc_uncond return3 007A : 0000_1000_0111_0000_0000_1111 244: ; end of walking 1 245: 246: ; prepares the next data - walking 0 247: wlk0: com tdata tdata 007B : 1011_1110_0000_0000_0110_0011 248: shl 1 tdata tdata 007C : 1011_0010_0001_0000_0110_0011 249: and tdata psrmask tdata 007D : 1010_0110_0011_0001_0100_0011 250: jmpr cc_nzero +2 007E : 0000_0100_0001_0000_0000_0001 251: mov 1 tdata 007F : 1100_0110_0000_0000_0010_0011 252: com tdata tdata 0080 : 1011_1110_0000_0000_0110_0011 253: and tdata psrmask tdata 0081 : 1010_0110_0011_0001_0100_0011 254: jmp cc_uncond return3 0082 : 0000_1000_0111_0000_0000_1111 255: ; end of walking 0 256: 257: ; prepares the next data by pseudo random generator 258: psr: lpio 0x202 tdata 0083 : 1110_0110_0100_0000_0100_0011 259: and tdata psrmask tdata 0084 : 1010_0110_0011_0001_0100_0011 260: jmp cc_uncond return3 0085 : 0000_1000_0111_0000_0000_1111 261: ; end random generator 262: 263: ; init walking 1 264: iwlk1: mov r11 tdata 0086 : 1100_0010_0000_0001_0110_0011 265: jmp cc_uncond return3 0087 : 0000_1000_0111_0000_0000_1111 266: 267: ; init walking 0 268: iwlk0: com r11 tdata 0088 : 1011_1110_0000_0001_0110_0011 269: and tdata psrmask tdata 0089 : 1010_0110_0011_0001_0100_0011 270: jmp cc_uncond return3 008A : 0000_1000_0111_0000_0000_1111 271: 272: ; init psr 273: ;#ifdef trap3 274: ipsr: mov b1_0_0_00_01_11111 tdata 008B : 1100_0111_0000_0111_1110_0011 275: ;#else 276: ;ipsr: mov b1_0_0_00_01_1111 tdata 277: ;#endif 278: mov 31 r0 008C : 1100_0110_0000_0011_1110_0000 279: sub r0 bitnum r0 008D : 1000_1010_0000_0001_1000_0000 280: ;#ifdef trap3 281: ;#else 282: ; cmp r0 16 283: ; jmpr cc_carry 2 284: ; mov 15 r0 285: ;#endif 286: or tdata r0 tdata 008E : 1010_1010_0011_0000_0000_0011 287: spio tdata 0x201 008F : 0010_0000_0011_0010_0000_0001 288: mov r13 tdata 0090 : 1100_0010_0000_0001_1010_0011 289: spio tdata 0x200 0091 : 0010_0000_0011_0010_0000_0000 290: nop 0092 : 0000_0000_0000_0000_0000_0000 291: nop 0093 : 0000_0000_0000_0000_0000_0000 292: lpio 0x202 tdata 0094 : 1110_0110_0100_0000_0100_0011 293: jmp cc_uncond return3 0095 : 0000_1000_0111_0000_0000_1111 Source file read, 0 error(s), 0 warning(s).