By this program cpu0 performs full test of separate GIO-locations via GIO-bus.
  The number of bits tested and the address of corresponding readable/writable register are encoded
  initially and stored in IMEM1, by GIO.tcs file. The number of errors occured while testing certain register is
  finally stored in IMEM2 at the same position as encoded data are in IMEM1.
  The format of the data stored in IMEM1 is 0xBBAAAA, where BB represents the number of bits
  tested while AAAA is the GIO-address of the tested location.
  The number of bits in the last data in IMEM1 have to be 0, in order the chip to go into Low Power!
  In order to understand the result from the test, additional GIO_chk.tcs file is prepared, where
  reading of IMEM2 is performed. Comments are added with the name of the register in GIO, that corresponds
  to the current IMEM2 location.
  There is an option allowing the test in single chip, in all chips in ROB, or MCM-tester.
  Choosing the "type" variable in scsn_ids.tcs file to be 0, we select test in single chip. Otherwise -
  test in ROB.