; DATE: 15.12.2003 ; This program performs full test of separate GIO-locations via GIO-bus. ; The number of bits tested and the address of corresponding readable/writable register are encoded ; initially and stored in IMEM1. The number of err_ors occured while testing certain register is ; finally stored in IMEM2 at the same position as encoded data are in IMEM1. Reading IMEM2 after ; the test is performed, the result could be seen. ; The format of the data stored in IMEM1 is 0xBBAAAA, where BB represents the number of bits ; tested while AAAA is the GIO-address of the tested location. ; The number of bits in the last data in IMEM1 have to be 0, in order the chip to go into Low Power! ; DEFINITIONS, USED IN THE PROGRAM CODE: #def work=PRF[1] ; register for current operations (CO) #def rdata=PRF[2] ; data red by test_programs and CO #def tdata=PRF[3] ; test_vector to be writen #def errnum=PRF[4] ; contains the number of err_ors #def return1=PRF[5] ; return address (at first level) #def return2=PRF[6] ; return address (at second level) #def return3=PRF[7] ; return address (at third level) #def tdgen=PRF[8] ; test data generator code label #def itdgen=PRF[9] ; init tdgen code label #def psrmask=PRF[10] ; mask for test_vector #def bitnum=PRF[12] ; =32 minus the number of bits of the tested area ; prf11 and prf13 are used inside the testing routine #def ioaddr=PRF[14] ; contains the autoincrementing address of I/O operations through GIO #def firstaddress=grf[1] ; first address of the tested area #def lastaddress=grf[2] ; last address of the tested area #def MEMRW=0xD000 ; the address of the register, controling R/W operations of IMEM/DMEMs #def IAFIRST=0xE000 ; first address of IMEM nop #ifdef cpu0 start: nop mov b0100_01_1, work ; initiate for Read from IMEM1 and Write to IMEM2 jmpr cc_busy, 0 iext MEMRW sgio work , MEMRW iext 0x0000FFFF ; prepare a mask to derive the GIO-address mov 0x0000FFFF grf[4] ; of the location to be tested. The mask is stored ; in grf[4] iext IAFIRST mov IAFIRST grf[3] ; reading the data encoded and stored initially nxt: jmpr cc_busy, 0 ; in IMEM1 ... lgio 0 grf[3] jmpr cc_busy, 0 lpio 0x300, work and work grf[4] firstaddress ; ... decoding of the data red from IMEM1 mov firstaddress errnum ; and initiating the input parameters for add errnum c1 lastaddress ; the full test procedure shl -16, work bitnum ; if the number of bits tested is 0, or bitnum bitnum bitnum ; then going to Low-Power mode jmp cc_zero lp mov c0 work ; in this code a mask is preparing mov c1 psrmask ; for the testing of the register up: add work c1 work ; with certain length (bitnum). cmp bitnum work jmp cc_zero bits shl 1 psrmask psrmask add psrmask c1 psrmask jmp cc_uncond up bits: mov 32 work ; the input parameter for the testin procedure sub work bitnum bitnum ; is 32 minus bitnum. mov c0, errnum lgio 0 firstaddress ; storing the initial state of the lockation tested jmpr cc_busy 0 lpio 0x300 work ; NEW!!! mov work g0 mvpcr +2, return1 ; call testing routine - cltst jmp cc_uncond cltst ;add errnum c1 errnum jmpr cc_busy 0 mov g0 work sgio work firstaddress jmpr cc_busy, 0 sgio errnum grf[3] ; writing the result of the test (errnum) ; in IMEM2 at address stored in grf[3] mov grf[3] work ; ... geting the next data from IMEM1 and add work c1 grf[3] ; go to decode and test the next location jmp cc_uncond nxt lp: jmpr cc_busy, 0 ; ... transition into ... mov 0xA21, work mov c0 rdata sgio rdata, work mov 0x012, work sgio work, 0xA04 ; ... low power mode end: jmp cc_uncond, end ; END OF THE ENTIRE PROGRAM ; SUBROUTINES BELOW ; BEGIN THE TESTING ROUTINE (uses testing subroutine) cltst: mov 1, prf[11] mvpcr +2, return3 jmp cc_uncond, iwlk0 nt0: mov wlk0, tdgen ; call walking 0 test_routine mvpcr +2, return2 jmp cc_uncond, tstgio shl 1, prf[11], prf[11] jmp cc_carry, it1 sub bitnum c1 work mov 15 rdata mov prf[11] prf[0] cmp rdata work jmpr cc_ncarry 3 shl 15 prf[0] prf[0] sub work rdata work shlt work, prf[0] ; if MSB of the current register tested is set - stop! jmp cc_ncarry, nt0 it1: mov 1, prf[11] mvpcr +2, return3 jmp cc_uncond, iwlk1 nt1: mov wlk1, tdgen ; call walking 1 test_routine mvpcr +2, return2 jmp cc_uncond, tstgio shl 1, prf[11], prf[11] jmp cc_carry, it2 sub bitnum c1 work mov 15 rdata mov prf[11] prf[0] cmp rdata work jmpr cc_ncarry 3 shl 15 prf[0] prf[0] sub work rdata work shlt work, prf[0] ; if MSB of the current register tested is set - stop! jmp cc_ncarry, nt1 it2: mov 1, prf[11] mvpcr +2, return3 jmp cc_uncond, ipsr ; #ifdef psr_test nt2: mov psr, tdgen ; call pseudo random vector test_routine mvpcr +2, return2 jmp cc_uncond, tstgio shl 1, prf[11], prf[11] jmp cc_carry, return1 sub bitnum c1 work mov 15 rdata mov prf[11] prf[0] cmp rdata work jmpr cc_ncarry 3 shl 15 prf[0] prf[0] sub work rdata work shlt work, prf[0] ; if MSB of the current register tested is set - stop! jmp cc_ncarry, nt2 ; #endif jmp cc_uncond return1 ; END OF THE TESTING ROUTINE ; BEGIN OF THE SUBROUTINE (used by testing routine above) tstgio: sgio tdata, firstaddress ; writing the test data in current address ; BEGIN COMPARING PART OF CODE jmpr cc_busy, 0 lgio 0, firstaddress jmpr cc_busy, 0 ; here is the body of the cycle lpio 0x300, rdata ; reading each address and and rdata psrmask rdata ; comparing the result with cmp rdata, tdata ; data stored befor jmp cc_zero, nextt add errnum, c1, errnum ; nextt: mvpcr +2, return3 ; if err_or detected jmp cc_uncond, tdgen ; errnum is incremented jmp cc_uncond, return2 ; prepares the next data - walking 1 wlk1: shl 1, tdata, tdata and tdata, psrmask, tdata jmp cc_nzero, return3 mov 1, tdata jmp cc_uncond, return3 ; end of walking 1 ; prepares the next data - walking 0 wlk0: com tdata, tdata shl 1, tdata, tdata and tdata, psrmask, tdata jmpr cc_nzero, +2 mov 1, tdata com tdata, tdata and tdata, psrmask, tdata jmp cc_uncond, return3 ; end of walking 0 ; prepares the next data by pseudo random generator psr: lpio 0x202, tdata and tdata, psrmask, tdata jmp cc_uncond, return3 ; end random generator ; init walking 1 iwlk1: and prf[11], psrmask, tdata jmp cc_uncond, return3 ; init walking 0 iwlk0: com prf[11], tdata and tdata, psrmask, tdata jmp cc_uncond, return3 ; init psr ;#ifdef trap3 ipsr: mov b1_0_0_00_01_11111, tdata ;#else ;ipsr: mov b1_0_0_00_01_1111, tdata ;#endif mov 31 work sub work bitnum work ;#ifdef trap3 ;#else ; cmp work 16 ; jmpr cc_carry 2 ; mov 15 work ;#endif or tdata work tdata spio tdata, 0x201 mov 0xABC, tdata spio tdata, 0x200 nop nop lpio 0x202, tdata and tdata, psrmask, tdata jmp cc_uncond, return3 org 0xFFF ; this code is only for surety, if PC points at the jmp cc_uncond start ; END of IMEM #endif