expect 127, IM, 0x0; // SML0 expect 127, IM+1, 0x0; // SML1 expect 127, IM+2, 0x0; // SML2 expect 127, IM+3, 0x0; // NITM0 expect 127, IM+4, 0x0; // NITM1 expect 127, IM+5, 0x0; // NITM2 expect 127, IM+6, 0x0; // NICLK expect 127, IM+7, 0x0; // PRECLK expect 127, IM+8, 0x0; // ADCEN expect 127, IM+9, 0x0; // NIODE expect 127, IM+10, 0x0; // NIOCE expect 127, IM+11, 0x0; // NIIDE expect 127, IM+12, 0x0; // NIICE expect 127, IM+13, 0x0; // PASADEL expect 127, IM+14, 0x0; // PASAPHA expect 127, IM+15, 0x0; // PASAPRA expect 127, IM+16, 0x0; // PASADAC expect 127, IM+17, 0x0; // PASACHM expect 127, IM+18, 0x0; // PASASTL expect 127, IM+19, 0x0; // PASAPR1 expect 127, IM+20, 0x0; // PASAPR0 expect 127, IM+21, 0x0; // ADCMSK expect 127, IM+22, 0x0; // ADCINB expect 127, IM+23, 0x0; // ADCDAC expect 127, IM+24, 0x0; // ADCPAR expect 127, IM+25, 0x0; // ADCTST expect 127, IM+26, 0x0; // SADCAZ expect 127, IM+27, 0x0; // SADCTRG expect 127, IM+28, 0x0; // SADCRUN expect 127, IM+29, 0x0; // SADCPWR expect 127, IM+30, 0x0; // LOTSIM expect 127, IM+31, 0x0; // SADCEC expect 127, IM+32, 0x0; // SADCMS expect 127, IM+33, 0x0; // SADCOC expect 127, IM+34, 0x0; // SADCGTB expect 127, IM+35, 0x0; // TPPTO expect 127, IM+36, 0x0; // TPPAE expect 127, IM+37, 0x0; // TPPGR expect 127, IM+38, 0x0; // FLBY expect 127, IM+39, 0x0; // FPBY expect 127, IM+40, 0x0; // FPTC expect 127, IM+41, 0x0; // FPNP expect 127, IM+42, 0x0; // FPCL expect 127, IM+43, 0x0; // FGBY expect 127, IM+44, 0x0; // FGF0 expect 127, IM+45, 0x0; // FGF1 expect 127, IM+46, 0x0; // FGF2 expect 127, IM+47, 0x0; // FGF3 expect 127, IM+48, 0x0; // FGF4 expect 127, IM+49, 0x0; // FGF5 expect 127, IM+50, 0x0; // FGF6 expect 127, IM+51, 0x0; // FGF7 expect 127, IM+52, 0x0; // FGF8 expect 127, IM+53, 0x0; // FGF9 expect 127, IM+54, 0x0; // FGF10 expect 127, IM+55, 0x0; // FGF11 expect 127, IM+56, 0x0; // FGF12 expect 127, IM+57, 0x0; // FGF13 expect 127, IM+58, 0x0; // FGF14 expect 127, IM+59, 0x0; // FGF15 expect 127, IM+60, 0x0; // FGF16 expect 127, IM+61, 0x0; // FGF17 expect 127, IM+62, 0x0; // FGF18 expect 127, IM+63, 0x0; // FGF19 expect 127, IM+64, 0x0; // FGF20 expect 127, IM+65, 0x0; // FGA0 expect 127, IM+66, 0x0; // FGA1 expect 127, IM+67, 0x0; // FGA2 expect 127, IM+68, 0x0; // FGA3 expect 127, IM+69, 0x0; // FGA4 expect 127, IM+70, 0x0; // FGA5 expect 127, IM+71, 0x0; // FGA6 expect 127, IM+72, 0x0; // FGA7 expect 127, IM+73, 0x0; // FGA8 expect 127, IM+74, 0x0; // FGA9 expect 127, IM+75, 0x0; // FGA10 expect 127, IM+76, 0x0; // FGA11 expect 127, IM+77, 0x0; // FGA12 expect 127, IM+78, 0x0; // FGA13 expect 127, IM+79, 0x0; // FGA14 expect 127, IM+80, 0x0; // FGA15 expect 127, IM+81, 0x0; // FGA16 expect 127, IM+82, 0x0; // FGA17 expect 127, IM+83, 0x0; // FGA18 expect 127, IM+84, 0x0; // FGA19 expect 127, IM+85, 0x0; // FGA20 expect 127, IM+86, 0x0; // FGTA expect 127, IM+87, 0x0; // FGTB expect 127, IM+88, 0x0; // FGCL expect 127, IM+89, 0x0; // FTBY expect 127, IM+90, 0x0; // FTAL expect 127, IM+91, 0x0; // FTLL expect 127, IM+92, 0x0; // FTLS expect 127, IM+93, 0x0; // FCBY expect 127, IM+94, 0x0; // FCW1 expect 127, IM+95, 0x0; // FCW2 expect 127, IM+96, 0x0; // FCW3 expect 127, IM+97, 0x0; // FCW4 expect 127, IM+98, 0x0; // FCW5 expect 127, IM+99, 0x0; // TPFS expect 127, IM+100, 0x0; // TPFE expect 127, IM+101, 0x0; // TPQS0 expect 127, IM+102, 0x0; // TPQE0 expect 127, IM+103, 0x0; // TPQS1 expect 127, IM+104, 0x0; // TPQE1 expect 127, IM+105, 0x0; // TPHT expect 127, IM+106, 0x0; // TPVBY expect 127, IM+107, 0x0; // TPVT expect 127, IM+108, 0x0; // TPFP expect 127, IM+109, 0x0; // TPCL expect 127, IM+110, 0x0; // TPCT expect 127, IM+111, 0x0; // TPD expect 127, IM+112, 0x0; // TPCBY expect 127, IM+113, 0x0; // TPCI0 expect 127, IM+114, 0x0; // TPCI1 expect 127, IM+115, 0x0; // TPCI2 expect 127, IM+116, 0x0; // TPCI3 expect 127, IM+117, 0x0; // EBD expect 127, IM+118, 0x0; // EBSF expect 127, IM+119, 0x0; // EBAQA expect 127, IM+120, 0x0; // EBSIM expect 127, IM+121, 0x0; // EBSIA expect 127, IM+122, 0x0; // EBPP expect 127, IM+123, 0x0; // EBPC expect 127, IM+124, 0x0; // EBIS expect 127, IM+125, 0x0; // EBIT expect 127, IM+126, 0x0; // EBIL expect 127, IM+127, 0x0; // EBIN expect 127, IM+128, 0x0; // MEMCOR expect 127, IM+129, 0x0; // DMDELA expect 127, IM+130, 0x0; // DMDELS expect 127, IM+131, 0x0; // CTGDINI expect 127, IM+132, 0x0; // CTGCTRL expect 127, IM+133, 0x0; // NMOD expect 127, IM+134, 0x0; // NTRO expect 127, IM+135, 0x0; // NES expect 127, IM+136, 0x0; // NCUT expect 127, IM+137, 0x0; // NRRO expect 127, IM+138, 0x0; // NP0 expect 127, IM+139, 0x0; // NP1 expect 127, IM+140, 0x0; // NP2 expect 127, IM+141, 0x0; // NP3 expect 127, IM+142, 0x0; // NED expect 127, IM+143, 0x0; // NDLY expect 127, IM+144, 0x0; // NBND // if ( single chip tested) { restrict MCM | WAFER expect dut, IM+145, 0x0; // SMMODE expect dut, IM+146, 0x0; // FILCLK expect dut, IM+147, 0x0; // SEBDEN expect dut, IM+148, 0x0; // SEBDOU expect dut, IM+149, 0x000D47; // END_MARK } restrict MCM expect ni0, IM+145, 0x000D47; // END_MARK } expect ni1, IM+145, 0x000D47; // END_MARK } expect ni2, IM+145, 0x000D47; // END_MARK } expect ni3, IM+145, 0x000D47; // END_MARK } restrict (MCM | WAFER) == 0 expect 127, IM+145, 0x000D47; // END_MARK } restrict 1