Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.6, Dec 2007 SVN Revision 0, SVN Date 2007-12-27 Please send any comments to: angelov@kip.uni-heidelberg.de 18:34:46 / 21 Apr 2008 Source code file: SignalProcessing.asm Memory initialisation file: Log file: ../work/cpu2.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU2 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 107 ASM_SVN_REV = 0 1: ;################################################# 2: ;# 3: ;# Test Program for nonlinearity filter. 4: ;# 5: ;# Input data is taken from event buffer and 6: ;# another memory region. 7: ;# 8: ;# Marcus Gutfleisch 9: ;# Ruprecht-Karls-Universität Heidelberg, Kir 10: ;# 11: ;# Heidelberg, 18.03.2005 12: ;# 13: ;################################################# 14: 15: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: 31: #def CTGDINI=0x0B80; dddd dddd dddd dddd dddd dddd 32: #def CTGCTRL=0x0B81; ---- ---- ---- ---- ---S idce 33: #def CTGDOUT=0x0B82; DDDD DDDD DDDD DDDD DDDD DDDD 34: #def CTPDINI=0x0200; dddd dddd dddd dddd dddd dddd 35: #def CTPCTRL=0x0201; ---- ---- ---- ---- ---S idce 36: #def CTPDOUT=0x0202; DDDD DDDD DDDD DDDD DDDD DDDD 37: 38: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 39: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 40: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 41: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 42: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 43: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 44: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 45: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 46: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 47: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 48: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 49: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 50: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 51: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 52: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 53: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 54: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 55: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 56: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 57: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 58: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 59: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 60: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 61: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 62: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 63: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 64: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 65: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 66: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 67: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 68: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 69: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 70: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 71: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 72: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 73: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 74: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 75: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 76: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 77: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 78: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 79: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 80: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 81: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 82: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 83: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 84: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 85: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 86: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 87: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 88: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 89: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 90: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 91: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 92: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 93: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 94: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 95: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 96: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 97: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 98: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 99: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 100: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 101: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 102: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 103: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 104: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 105: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 106: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 107: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 108: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 109: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 110: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 111: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 112: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 113: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 114: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 115: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 116: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 117: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 118: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 119: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 120: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 121: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 122: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 123: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 124: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 125: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 126: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 127: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 128: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 129: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 130: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 131: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 132: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 133: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 134: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 135: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 136: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 137: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 138: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 139: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 140: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 141: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 142: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 143: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 144: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 145: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 146: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 147: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 148: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 149: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 150: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 151: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 152: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 153: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 154: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 155: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 156: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 157: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 158: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 159: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 160: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 161: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 162: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 163: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 164: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 165: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 166: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 167: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 168: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 169: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 170: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 171: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 172: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 173: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 174: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 175: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 176: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 177: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 178: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 179: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 180: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 181: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 182: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 183: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 184: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 185: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 186: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 187: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 188: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 189: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 190: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 191: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 192: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 193: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 194: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 195: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 196: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 197: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 198: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 199: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 200: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 201: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 202: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 203: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 204: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 205: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 206: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 207: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 208: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 209: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 210: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 211: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 212: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 213: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 214: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 215: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 216: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 217: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 218: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- 219: #def GBUSR0=0x0300; -- readonly 220: #def GBUSR1=0x0301; -- readonly *** End of include file /cad/tools/bin//conf_va.inc *** Include file ../../assembler.inc 1: ;#define MCM=1; 2: ;#define WAFER=1; 3: #define ROB=1; *** End of include file ../../assembler.inc 18: 19: 20: 21: ;######################################### 22: ;# 23: ;# defines 24: ;# 25: ;######################################### 26: 27: 28: #def CPU_SYNC = g0 29: 30: 31: #def ERROR_CTR = c8 32: #def OFFSET_CTR = c12 33: #def LL_CTR = c13 34: 35: #def OFFSET_ADR = 0xC04 36: #def AL_ADR = 0xC05 37: 38: #ifdef cpu0 39: #def ERROR_ADR = 0xC00 40: #endif 41: #ifdef cpu1 42: #def ERROR_ADR = 0xC08 43: #endif 44: #ifdef cpu2 45: #def ERROR_ADR = 0xC10 46: #endif 47: #ifdef cpu3 48: #def ERROR_ADR = 0xC18 49: #endif 50: 51: 52: 53: ;######################################### 54: ;# 55: ;# 0x0000: Infinite Loop at Instructi 56: ;# 57: ;######################################### 58: 59: 60: org 0x0000 61: 62: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 63: nop 0001 : 0000_0000_0000_0000_0000_0000 64: 65: 66: 67: ;######################################### 68: ;# 69: ;# 0x0010: Interrrupt Clear Jump Addr 70: ;# 71: ;# CPU0: switch off all NI 72: ;# switch off NI cloc 73: ;# switch off preproc 74: ;# switch on filter 75: ;# 76: ;# CPU1: end clear state, a 77: ;# 78: ;# CPU2: get tracklet end s 79: ;# 80: ;# CPU3: get data end signa 81: ;# 82: ;######################################### 83: 84: 85: org 0x0010 86: 87: mov 0, r12 0010 : 1100_0110_0000_0000_0000_1100 88: mov 4, r13 0011 : 1100_0110_0000_0000_1000_1101 89: 90: #ifdef cpu0 91: 92: mov 0, r0 93: iext EBD 94: mov EBD, r1 95: jmpr cc_busy, 0 96: sgio r0, r1 97: 98: mov 0, CPU_SYNC 99: 100: mov CMD_EXT_CLR, r0 101: mov CMD_PRETRIGG, r1 102: mov 1024, r2 103: jmpr cc_busy, 0 104: cmp r2, OFFSET_CTR 105: jmp cc_leu, end_lp 106: sgio r0, SMCMD 107: 108: nop 109: nop 110: sgio r1, SMCMD 111: 112: #else 113: 114: #ifdef MCM 115: #ifdef cpu1 116: mov 0, r0 117: iext SEBDOU 118: sgio r0, SEBDOU 119: #else 120: nop 121: nop 122: nop 123: #endif 124: #endif 125: 126: nop 0012 : 0000_0000_0000_0000_0000_0000 127: nop 0013 : 0000_0000_0000_0000_0000_0000 128: 129: nop 0014 : 0000_0000_0000_0000_0000_0000 130: 131: nop 0015 : 0000_0000_0000_0000_0000_0000 132: nop 0016 : 0000_0000_0000_0000_0000_0000 133: nop 0017 : 0000_0000_0000_0000_0000_0000 134: nop 0018 : 0000_0000_0000_0000_0000_0000 135: nop 0019 : 0000_0000_0000_0000_0000_0000 136: nop 001A : 0000_0000_0000_0000_0000_0000 137: nop 001B : 0000_0000_0000_0000_0000_0000 138: 139: nop 001C : 0000_0000_0000_0000_0000_0000 140: nop 001D : 0000_0000_0000_0000_0000_0000 141: nop 001E : 0000_0000_0000_0000_0000_0000 142: 143: #endif 144: 145: end_cl: jmpr cc_uncond, 0 001F : 0000_0100_0000_0011_1110_1111 146: nop 0020 : 0000_0000_0000_0000_0000_0000 147: 148: end_lp: 149: #ifdef MCM 150: mov 5, r0 151: iext SEBDEN 152: sgio r0, SEBDEN 153: jmpr cc_busy, 0 154: #endif 155: 156: mov CMD_LP, r0 0021 : 1100_0110_0000_0010_0100_0000 157: sgio r0, SMCMD 0022 : 0010_1000_0000_1010_0000_0100 158: 159: jmpr cc_uncond, 0 0023 : 0000_0100_0000_0100_0110_1111 160: nop 0024 : 0000_0000_0000_0000_0000_0000 161: 162: 163: 164: ;######################################### 165: ;# 166: ;# 0x0100: Interrrupt Tracklet Proces 167: ;# 168: ;# send delayed tracklet end 169: ;# 170: ;######################################### 171: 172: 173: org 0x0100 174: 175: #ifdef cpu0 176: mov 6, r0 177: iext EBD 178: mov EBD, r1 179: jmpr cc_busy, 0 180: sgio r0, r1 181: #endif 182: 183: #ifdef cpu1 184: nop 185: nop 186: nop 187: nop 188: nop 189: #endif 190: 191: #ifdef cpu2 192: nop 0100 : 0000_0000_0000_0000_0000_0000 193: nop 0101 : 0000_0000_0000_0000_0000_0000 194: nop 0102 : 0000_0000_0000_0000_0000_0000 195: nop 0103 : 0000_0000_0000_0000_0000_0000 196: nop 0104 : 0000_0000_0000_0000_0000_0000 197: #endif 198: 199: #ifdef cpu3 200: mov 1, r0 201: iext EBSIM 202: mov EBSIM, r1 203: jmpr cc_busy, 0 204: sgio r0, r1 205: #endif 206: 207: 208: 209: ;################################# 210: ;# 211: ;# check result 212: ;# 213: ;################################# 214: 215: 216: mov EBR0, r8 ; load cha 0105 : 1100_0111_0000_0000_0000_1000 217: add r8, c1, r8 ; add +1 d 0106 : 1000_0010_1000_0110_0010_1000 218: mov EBR1, r9 0107 : 1100_0111_0000_1000_0000_1001 219: add r9, c1, r9 0108 : 1000_0010_1001_0110_0010_1001 220: mov EBR2, r10 0109 : 1100_0111_0001_0000_0000_1010 221: add r10, c1, r10 010A : 1000_0010_1010_0110_0010_1010 222: mov EBR3, r11 010B : 1100_0111_0001_1000_0000_1011 223: add r11, c1, r11 010C : 1000_0010_1011_0110_0010_1011 224: mov EBR4, r12 010D : 1100_0111_0010_0000_0000_1100 225: add r12, c1, r12 010E : 1000_0010_1100_0110_0010_1100 226: mov EBR5, r13 010F : 1100_0111_0010_1000_0000_1101 227: add r13, c1, r13 0110 : 1000_0010_1101_0110_0010_1101 228: 229: mov 0, r0 ; r0: time 0111 : 1100_0110_0000_0000_0000_0000 230: 231: mov 0, r14 ; r14: slo 0112 : 1100_0110_0000_0000_0000_1110 232: mov 0, r15 ; r15: fas 0113 : 1100_0110_0000_0000_0000_1111 233: 234: mov 0x3FF, r7 ; r7: curr 0114 : 1100_0110_0111_1111_1110_0111 235: 236: mov 0x600, r1 ; r1: curr 0115 : 1100_0110_1100_0000_0000_0001 237: add r1, LL_CTR, r1 0116 : 1000_0010_0001_0111_1010_0001 238: 239: mov 0x200, r2 ; r2: curr 0117 : 1100_0110_0100_0000_0000_0010 240: 241: loopTT: mov 0, r6 ; r6: erro 0118 : 1100_0110_0000_0000_0000_0110 242: 243: ;######################### 244: ;# 245: ;# calculate expected 246: ;# 247: ;######################### 248: 249: mov 31, r3 0119 : 1100_0110_0000_0011_1110_0011 250: add r8, r3, r3 ; source o 011A : 1000_0010_1000_0000_0110_0011 251: add r0, r3, r3 ; source a 011B : 1000_0010_0000_0000_0110_0011 252: 253: lpio r3, r5 011C : 1110_0010_0000_0000_0110_0101 254: lpio r3, r5 ; input da 011D : 1110_0010_0000_0000_0110_0101 255: 256: shl 2, r5, r3 ; r3: expe 011E : 1011_0010_0010_0000_1010_0011 257: 258: add r14, r15, r4 ; r4: corr 011F : 1000_0010_1110_0001_1110_0100 259: cmp r4, 0xFFF 0120 : 1100_1000_0100_1111_1111_1111 260: jmp cc_leu, TTo0 0121 : 0000_0100_0000_0000_0001_1000 261: mov 0xFFF, r4 0122 : 1100_0111_1111_1111_1110_0100 262: 263: TTo0: sub r3, r4, r3 ; r3: expe 0123 : 1000_1010_0011_0000_1000_0011 264: jmp cc_gtu, TTo1 0124 : 0000_0100_0000_0000_0000_1000 265: mov 0, r3 0125 : 1100_0110_0000_0000_0000_0011 266: 267: TTo1: mul32 r7, r3, r4 ; r4: weig 0126 : 1001_0000_0111_0000_0110_1100 268: nop ; r5: stim 0127 : 0000_0000_0000_0000_0000_0000 269: shl -11, r4, r4 0128 : 1011_0011_0101_0000_1000_0100 270: add r4, r14, r5 0129 : 1000_0010_0100_0001_1100_0101 271: cmp r5, 0xFFF 012A : 1100_1000_0101_1111_1111_1111 272: jmp cc_leu, TTo2 012B : 0000_0100_0000_0000_0001_1000 273: mov 0xFFF, r5 012C : 1100_0111_1111_1111_1110_0101 274: 275: TTo2: mul32 r5, r1, r5 ; r14: upd 012D : 1001_0000_0101_0000_0010_1101 276: nop 012E : 0000_0000_0000_0000_0000_0000 277: shl -11, r5, r14 012F : 1011_0011_0101_0000_1010_1110 278: 279: sub r3, r4, r4 ; r4: weig 0130 : 1000_1010_0011_0000_1000_0100 280: add r4, r15, r5 ; r5: stim 0131 : 1000_0010_0100_0001_1110_0101 281: cmp r5, 0xFFF 0132 : 1100_1000_0101_1111_1111_1111 282: jmp cc_leu, TTo3 0133 : 0000_0100_0000_0000_0001_1000 283: mov 0xFFF, r5 0134 : 1100_0111_1111_1111_1110_0101 284: 285: TTo3: mul32 r5, r2, r5 ; r14: upd 0135 : 1001_0000_0101_0000_0100_1101 286: nop 0136 : 0000_0000_0000_0000_0000_0000 287: shl -11, r5, r15 0137 : 1011_0011_0101_0000_1010_1111 288: 289: shl -2, r3, r3 ; -> ( 0138 : 1011_0011_1110_0000_0110_0011 290: 291: ;######################### 292: ;# 293: ;# check value 294: ;# 295: ;######################### 296: 297: TTc0: add r0, r8, r4 ; r4: even 0139 : 1000_0010_0000_0001_0000_0100 298: lpio r4, r5 013A : 1110_0010_0000_0000_1000_0101 299: lpio r4, r5 ; r5: filt 013B : 1110_0010_0000_0000_1000_0101 300: 301: cmp r3, r5 013C : 1000_1000_0011_0000_1010_0000 302: jmp cc_eq, TTc1 013D : 0000_0100_0000_0000_0001_0001 303: add r6, c1, r6 013E : 1000_0010_0110_0110_0010_0110 304: 305: TTc1: add r0, r9, r4 ; r4: even 013F : 1000_0010_0000_0001_0010_0100 306: lpio r4, r5 0140 : 1110_0010_0000_0000_1000_0101 307: lpio r4, r5 ; r5: filt 0141 : 1110_0010_0000_0000_1000_0101 308: 309: cmp r3, r5 0142 : 1000_1000_0011_0000_1010_0000 310: jmp cc_eq, TTc2 0143 : 0000_0100_0000_0000_0001_0001 311: add r6, c1, r6 0144 : 1000_0010_0110_0110_0010_0110 312: 313: TTc2: add r0, r10, r4 ; r4: even 0145 : 1000_0010_0000_0001_0100_0100 314: lpio r4, r5 0146 : 1110_0010_0000_0000_1000_0101 315: lpio r4, r5 ; r5: filt 0147 : 1110_0010_0000_0000_1000_0101 316: 317: cmp r3, r5 0148 : 1000_1000_0011_0000_1010_0000 318: jmp cc_eq, TTc3 0149 : 0000_0100_0000_0000_0001_0001 319: add r6, c1, r6 014A : 1000_0010_0110_0110_0010_0110 320: 321: TTc3: add r0, r11, r4 ; r4: even 014B : 1000_0010_0000_0001_0110_0100 322: lpio r4, r5 014C : 1110_0010_0000_0000_1000_0101 323: lpio r4, r5 ; r5: filt 014D : 1110_0010_0000_0000_1000_0101 324: 325: cmp r3, r5 014E : 1000_1000_0011_0000_1010_0000 326: jmp cc_eq, TTc4 014F : 0000_0100_0000_0000_0001_0001 327: add r6, c1, r6 0150 : 1000_0010_0110_0110_0010_0110 328: 329: TTc4: add r0, r12, r4 ; r4: even 0151 : 1000_0010_0000_0001_1000_0100 330: lpio r4, r5 0152 : 1110_0010_0000_0000_1000_0101 331: lpio r4, r5 ; r5: filt 0153 : 1110_0010_0000_0000_1000_0101 332: 333: cmp r3, r5 0154 : 1000_1000_0011_0000_1010_0000 334: jmp cc_eq, TTc5 0155 : 0000_0100_0000_0000_0001_0001 335: add r6, c1, r6 0156 : 1000_0010_0110_0110_0010_0110 336: 337: #ifdef cpu3 338: TTc5: add r0, r13, r4 ; r4: event 339: lpio r4, r5 340: lpio r4, r5 ; r5: filte 341: 342: cmp r3, r5 343: jmp cc_eq, TTend 344: add r6, c1, r6 345: #else 346: nop 0157 : 0000_0000_0000_0000_0000_0000 347: nop 0158 : 0000_0000_0000_0000_0000_0000 348: nop 0159 : 0000_0000_0000_0000_0000_0000 349: 350: nop 015A : 0000_0000_0000_0000_0000_0000 351: nop 015B : 0000_0000_0000_0000_0000_0000 352: TTc5: nop 015C : 0000_0000_0000_0000_0000_0000 353: #endif 354: 355: TTend: add r6, ERROR_CTR, r6 015D : 1000_0010_0110_0111_0000_0110 356: jmpr cc_busy, 0 015E : 0000_0100_0010_1011_1101_0111 357: sgio r6, ERROR_ADR 015F : 0010_1000_0110_1100_0001_0000 358: 359: add r0, c1, r0 0160 : 1000_0010_0000_0110_0010_0000 360: cmp r0, 31 0161 : 1100_1000_0000_0000_0001_1111 361: jmp cc_ltu, loopTT 0162 : 0000_0100_0000_0000_0001_0000 362: nop 0163 : 0000_0000_0000_0000_0000_0000 363: 364: 365: 366: 367: ;################################# 368: ;# 369: ;# increase counters 370: ;# 371: ;################################# 372: 373: 374: #ifdef cpu3 375: 376: mov 1, r1 377: add r1, LL_CTR, r0 378: cmp r0, 496 379: jmp cc_ltu, ct_LUT 380: 381: mov 0, r0 382: mov 256, r1 383: add r1, OFFSET_CTR, r1 384: 385: jmpr cc_busy, 0 386: sgio r1, OFFSET_ADR 387: 388: ct_LUT: jmpr cc_busy, 0 389: sgio r0, AL_ADR 390: 391: #else 392: 393: nop 0164 : 0000_0000_0000_0000_0000_0000 394: nop 0165 : 0000_0000_0000_0000_0000_0000 395: nop 0166 : 0000_0000_0000_0000_0000_0000 396: nop 0167 : 0000_0000_0000_0000_0000_0000 397: 398: nop 0168 : 0000_0000_0000_0000_0000_0000 399: nop 0169 : 0000_0000_0000_0000_0000_0000 400: nop 016A : 0000_0000_0000_0000_0000_0000 401: 402: nop 016B : 0000_0000_0000_0000_0000_0000 403: nop 016C : 0000_0000_0000_0000_0000_0000 404: 405: nop 016D : 0000_0000_0000_0000_0000_0000 406: nop 016E : 0000_0000_0000_0000_0000_0000 407: 408: #endif 409: 410: jmpr cc_busy, 0 016F : 0000_0100_0010_1101_1111_0111 411: 412: 413: 414: ;################################# 415: ;# 416: ;# write next LUT test entrie 417: ;# 418: ;################################# 419: 420: 421: mov LL_CTR, r12 ; r12: nex 0170 : 1100_0010_0000_0111_1010_1100 422: 423: iext FTLL 0171 : 0101_0000_0000_0000_0000_0011 424: mov FTLL, r0 0172 : 1100_0110_0000_0110_0010_0000 425: 426: jmpr cc_busy, 0 0173 : 0000_0100_0010_1110_0111_0111 427: sgio r12, r0 0174 : 0010_0100_1100_0000_0000_0000 428: 429: 430: 431: ;################################# 432: ;# 433: ;# write next test pattern in 434: ;# 435: ;################################# 436: 437: 438: #ifdef cpu3 439: 440: mov 0, r0 441: cmp r0, LL_CTR 442: jmp cc_neq, endEB 443: 444: iext EBW 445: mov EBW, r0 446: mov 32, r1 447: add r0, r1, r0 ; r0: even 448: 449: mov EBR5, r6 450: add r6, r1, r6 ; r6: even 451: 452: mov 256, r7 ; data 453: 454: mov 0, r1 ; r1: chan 455: mov 1, r2 ; r2: time 456: 457: loopEB: 458: add r6, r2, r8 ; r8: sing 459: 460: lpio r8, r4 461: lpio r8, r4 ; r4: old 462: add r7, r4, r4 ; r4: new 463: 464: shl 7, r1, r3 465: add r0, r3, r3 466: add r2, r3, r3 467: 468: jmpr cc_busy, 0 ; r3: sing 469: sgio r4, r3 ; r4: data 470: 471: mov 10, r5 472: 473: waitD: sub r5, c1, r5 474: jmp cc_gts, waitD 475: 476: add r1, c1, r1 477: cmp r1, 21 478: jmp cc_ltu, loopEB 479: 480: mov 0, r1 481: add r2, c1, r2 482: cmp r2, 32 483: jmp cc_ltu, loopEB 484: nop 485: endEB: mov 1, CPU_SYNC 486: 487: #else 488: 489: nop 0175 : 0000_0000_0000_0000_0000_0000 490: 491: #endif 492: 493: 494: 495: ;################################# 496: ;# 497: ;# wait for data writing comp 498: ;# 499: ;################################# 500: 501: 502: wsy: mov CPU_SYNC, r0 0176 : 1100_0010_0000_0010_0000_0000 503: cmp r0, 1 0177 : 1100_1000_0000_0000_0000_0001 504: jmp cc_neq, wsy 0178 : 0000_0100_0000_0000_0000_0001 505: 506: 507: ;################################# 508: ;# 509: ;# copy lower indicator words 510: ;# 511: ;################################# 512: 513: 514: #ifdef cpu0 515: mov 0x7B8, r15 516: #endif 517: 518: #ifdef cpu1 519: mov 0x7CC, r15 520: #endif 521: 522: #ifdef cpu2 523: mov 0x7E0, r15 0179 : 1100_0110_1111_1100_0000_1111 524: #endif 525: 526: #ifdef cpu3 527: mov 0x7F4, r15 528: #endif 529: 530: lpio EBI0, r0 017A : 1110_0111_0011_0000_0000_0000 531: lpio EBI0, r0 017B : 1110_0111_0011_0000_0000_0000 532: sra+ r0 017C : 0011_1000_0000_0000_0000_0000 533: 534: lpio EBI2, r0 017D : 1110_0111_0011_0000_0100_0000 535: lpio EBI2, r0 017E : 1110_0111_0011_0000_0100_0000 536: sra+ r0 017F : 0011_1000_0000_0000_0000_0000 537: 538: lpio EBI4, r0 0180 : 1110_0111_0011_0000_1000_0000 539: lpio EBI4, r0 0181 : 1110_0111_0011_0000_1000_0000 540: sra+ r0 0182 : 0011_1000_0000_0000_0000_0000 541: 542: lpio EBI6, r0 0183 : 1110_0111_0011_0000_1100_0000 543: lpio EBI6, r0 0184 : 1110_0111_0011_0000_1100_0000 544: sra+ r0 0185 : 0011_1000_0000_0000_0000_0000 545: 546: lpio EBI8, r0 0186 : 1110_0111_0011_0001_0000_0000 547: lpio EBI8, r0 0187 : 1110_0111_0011_0001_0000_0000 548: sra+ r0 0188 : 0011_1000_0000_0000_0000_0000 549: 550: #ifdef cpu3 551: lpio EBIA, r0 552: lpio EBIA, r0 553: sra+ r0 554: #else 555: nop 0189 : 0000_0000_0000_0000_0000_0000 556: nop 018A : 0000_0000_0000_0000_0000_0000 557: nop 018B : 0000_0000_0000_0000_0000_0000 558: #endif 559: 560: 561: ;################################# 562: ;# 563: ;# DMEM address to copy event 564: ;# beware: byte address = 4 * 565: ;# 566: ;################################# 567: 568: #ifdef cpu0 569: mov 0x080, r15 570: #endif 571: 572: #ifdef cpu1 573: mov 0x238, r15 574: #endif 575: 576: #ifdef cpu2 577: mov 0x3F0, r15 018C : 1100_0110_0111_1110_0000_1111 578: #endif 579: 580: #ifdef cpu3 581: mov 0x5A8, r15 582: #endif 583: 584: ;################################# 585: ;# 586: ;# channel check bits, absolu 587: ;# 588: ;################################# 589: 590: #ifdef cpu0 591: mov 3, r3 592: #endif 593: 594: #ifdef cpu1 595: mov 2, r3 596: #endif 597: 598: #ifdef cpu2 599: mov 3, r3 018D : 1100_0110_0000_0000_0110_0011 600: #endif 601: 602: #ifdef cpu3 603: mov 2, r3 604: #endif 605: 606: ;################################# 607: ;# 608: ;# copy event buffer data of 609: ;# 610: ;################################# 611: 612: mov EBR0, r14 018E : 1100_0111_0000_0000_0000_1110 613: mov 66, r5 018F : 1100_0110_0000_1000_0100_0101 614: 615: loop0: lpio+ r0 0190 : 1110_1110_0000_0000_0000_0000 616: lpio+ r0 0191 : 1110_1110_0000_0000_0000_0000 617: lpio+ r1 0192 : 1110_1110_0000_0000_0000_0001 618: lpio r14, r2 0193 : 1110_0010_0000_0001_1100_0010 619: 620: shl 10, r2, r2 0194 : 1011_0010_1010_0000_0100_0010 621: or r1, r2, r2 0195 : 1010_1010_0001_0000_0100_0010 622: shl 10, r2, r2 0196 : 1011_0010_1010_0000_0100_0010 623: or r0, r2, r2 0197 : 1010_1010_0000_0000_0100_0010 624: shl 2, r2, r2 0198 : 1011_0010_0010_0000_0100_0010 625: or r3, r2, r2 0199 : 1010_1010_0011_0000_0100_0010 626: 627: sra+ r2 019A : 0011_1000_0010_0000_0000_0000 628: 629: sub r5, c3, r5 019B : 1000_1010_0101_0110_0110_0101 630: jmp cc_gtu, loop0 019C : 0000_0100_0000_0000_0000_1000 631: 632: ;################################# 633: ;# 634: ;# copy event buffer data of 635: ;# 636: ;################################# 637: 638: mov EBR1, r14 019D : 1100_0111_0000_1000_0000_1110 639: mov 66, r5 019E : 1100_0110_0000_1000_0100_0101 640: xor r3, c1, r3 019F : 1010_0010_0011_0110_0010_0011 641: 642: loop1: lpio+ r0 01A0 : 1110_1110_0000_0000_0000_0000 643: lpio+ r0 01A1 : 1110_1110_0000_0000_0000_0000 644: lpio+ r1 01A2 : 1110_1110_0000_0000_0000_0001 645: lpio r14, r2 01A3 : 1110_0010_0000_0001_1100_0010 646: 647: shl 10, r2, r2 01A4 : 1011_0010_1010_0000_0100_0010 648: or r1, r2, r2 01A5 : 1010_1010_0001_0000_0100_0010 649: shl 10, r2, r2 01A6 : 1011_0010_1010_0000_0100_0010 650: or r0, r2, r2 01A7 : 1010_1010_0000_0000_0100_0010 651: shl 2, r2, r2 01A8 : 1011_0010_0010_0000_0100_0010 652: or r3, r2, r2 01A9 : 1010_1010_0011_0000_0100_0010 653: 654: sra+ r2 01AA : 0011_1000_0010_0000_0000_0000 655: 656: sub r5, c3, r5 01AB : 1000_1010_0101_0110_0110_0101 657: jmp cc_gtu, loop1 01AC : 0000_0100_0000_0000_0000_1000 658: 659: ;################################# 660: ;# 661: ;# copy event buffer data of 662: ;# 663: ;################################# 664: 665: mov EBR2, r14 01AD : 1100_0111_0001_0000_0000_1110 666: mov 66, r5 01AE : 1100_0110_0000_1000_0100_0101 667: xor r3, c1, r3 01AF : 1010_0010_0011_0110_0010_0011 668: 669: loop2: lpio+ r0 01B0 : 1110_1110_0000_0000_0000_0000 670: lpio+ r0 01B1 : 1110_1110_0000_0000_0000_0000 671: lpio+ r1 01B2 : 1110_1110_0000_0000_0000_0001 672: lpio r14, r2 01B3 : 1110_0010_0000_0001_1100_0010 673: 674: shl 10, r2, r2 01B4 : 1011_0010_1010_0000_0100_0010 675: or r1, r2, r2 01B5 : 1010_1010_0001_0000_0100_0010 676: shl 10, r2, r2 01B6 : 1011_0010_1010_0000_0100_0010 677: or r0, r2, r2 01B7 : 1010_1010_0000_0000_0100_0010 678: shl 2, r2, r2 01B8 : 1011_0010_0010_0000_0100_0010 679: or r3, r2, r2 01B9 : 1010_1010_0011_0000_0100_0010 680: 681: sra+ r2 01BA : 0011_1000_0010_0000_0000_0000 682: 683: sub r5, c3, r5 01BB : 1000_1010_0101_0110_0110_0101 684: jmp cc_gtu, loop2 01BC : 0000_0100_0000_0000_0000_1000 685: 686: ;################################# 687: ;# 688: ;# copy event buffer data of 689: ;# 690: ;################################# 691: 692: mov EBR3, r14 01BD : 1100_0111_0001_1000_0000_1110 693: mov 66, r5 01BE : 1100_0110_0000_1000_0100_0101 694: xor r3, c1, r3 01BF : 1010_0010_0011_0110_0010_0011 695: 696: loop3: lpio+ r0 01C0 : 1110_1110_0000_0000_0000_0000 697: lpio+ r0 01C1 : 1110_1110_0000_0000_0000_0000 698: lpio+ r1 01C2 : 1110_1110_0000_0000_0000_0001 699: lpio r14, r2 01C3 : 1110_0010_0000_0001_1100_0010 700: 701: shl 10, r2, r2 01C4 : 1011_0010_1010_0000_0100_0010 702: or r1, r2, r2 01C5 : 1010_1010_0001_0000_0100_0010 703: shl 10, r2, r2 01C6 : 1011_0010_1010_0000_0100_0010 704: or r0, r2, r2 01C7 : 1010_1010_0000_0000_0100_0010 705: shl 2, r2, r2 01C8 : 1011_0010_0010_0000_0100_0010 706: or r3, r2, r2 01C9 : 1010_1010_0011_0000_0100_0010 707: 708: sra+ r2 01CA : 0011_1000_0010_0000_0000_0000 709: 710: sub r5, c3, r5 01CB : 1000_1010_0101_0110_0110_0101 711: jmp cc_gtu, loop3 01CC : 0000_0100_0000_0000_0000_1000 712: 713: ;################################# 714: ;# 715: ;# copy event buffer data of 716: ;# 717: ;################################# 718: 719: mov EBR4, r14 01CD : 1100_0111_0010_0000_0000_1110 720: mov 66, r5 01CE : 1100_0110_0000_1000_0100_0101 721: xor r3, c1, r3 01CF : 1010_0010_0011_0110_0010_0011 722: 723: loop4: lpio+ r0 01D0 : 1110_1110_0000_0000_0000_0000 724: lpio+ r0 01D1 : 1110_1110_0000_0000_0000_0000 725: lpio+ r1 01D2 : 1110_1110_0000_0000_0000_0001 726: lpio r14, r2 01D3 : 1110_0010_0000_0001_1100_0010 727: 728: shl 10, r2, r2 01D4 : 1011_0010_1010_0000_0100_0010 729: or r1, r2, r2 01D5 : 1010_1010_0001_0000_0100_0010 730: shl 10, r2, r2 01D6 : 1011_0010_1010_0000_0100_0010 731: or r0, r2, r2 01D7 : 1010_1010_0000_0000_0100_0010 732: shl 2, r2, r2 01D8 : 1011_0010_0010_0000_0100_0010 733: or r3, r2, r2 01D9 : 1010_1010_0011_0000_0100_0010 734: 735: sra+ r2 01DA : 0011_1000_0010_0000_0000_0000 736: 737: sub r5, c3, r5 01DB : 1000_1010_0101_0110_0110_0101 738: jmp cc_gtu, loop4 01DC : 0000_0100_0000_0000_0000_1000 739: 740: ;################################# 741: ;# 742: ;# copy event buffer data of 743: ;# 744: ;################################# 745: 746: #ifdef cpu3 747: mov EBR5, r14 748: mov 66, r5 749: xor r3, c1, r3 750: 751: loop5: lpio+ r0 752: lpio+ r0 753: lpio+ r1 754: lpio r14, r2 755: 756: shl 10, r2, r2 757: or r1, r2, r2 758: shl 10, r2, r2 759: or r0, r2, r2 760: shl 2, r2, r2 761: or r3, r2, r2 762: 763: sra+ r2 764: 765: sub r5, c3, r5 766: jmp cc_gtu, loop5 767: #else 768: nop 01DD : 0000_0000_0000_0000_0000_0000 769: nop 01DE : 0000_0000_0000_0000_0000_0000 770: nop 01DF : 0000_0000_0000_0000_0000_0000 771: nop 01E0 : 0000_0000_0000_0000_0000_0000 772: nop 01E1 : 0000_0000_0000_0000_0000_0000 773: nop 01E2 : 0000_0000_0000_0000_0000_0000 774: nop 01E3 : 0000_0000_0000_0000_0000_0000 775: nop 01E4 : 0000_0000_0000_0000_0000_0000 776: nop 01E5 : 0000_0000_0000_0000_0000_0000 777: nop 01E6 : 0000_0000_0000_0000_0000_0000 778: nop 01E7 : 0000_0000_0000_0000_0000_0000 779: nop 01E8 : 0000_0000_0000_0000_0000_0000 780: nop 01E9 : 0000_0000_0000_0000_0000_0000 781: nop 01EA : 0000_0000_0000_0000_0000_0000 782: nop 01EB : 0000_0000_0000_0000_0000_0000 783: nop 01EC : 0000_0000_0000_0000_0000_0000 784: #endif 785: 786: 787: ;################################# 788: ;# 789: ;# end current state, goto cl 790: ;# 791: ;################################# 792: 793: 794: #ifdef cpu3 795: 796: mov 0, r0 797: iext EBSIM 798: mov EBSIM, r1 799: jmpr cc_busy, 0 800: sgio r0, r1 801: 802: mov CMD_CLEAR, r0 803: jmpr cc_busy, 0 804: sgio r0, SMCMD 805: 806: #else 807: 808: nop 01ED : 0000_0000_0000_0000_0000_0000 809: nop 01EE : 0000_0000_0000_0000_0000_0000 810: nop 01EF : 0000_0000_0000_0000_0000_0000 811: nop 01F0 : 0000_0000_0000_0000_0000_0000 812: nop 01F1 : 0000_0000_0000_0000_0000_0000 813: 814: nop 01F2 : 0000_0000_0000_0000_0000_0000 815: nop 01F3 : 0000_0000_0000_0000_0000_0000 816: nop 01F4 : 0000_0000_0000_0000_0000_0000 817: 818: #endif 819: 820: 821: 822: ;################################# 823: ;# 824: ;# switch off own clock after 825: ;# 826: ;################################# 827: 828: 829: clkoff: mov 0, r0 01F5 : 1100_0110_0000_0000_0000_0000 830: jmpr cc_busy, 0 01F6 : 0000_0100_0011_1110_1101_0111 831: 832: #ifdef cpu0 833: sgio r0, CPU0SS 834: #endif 835: 836: #ifdef cpu1 837: sgio r0, CPU1SS 838: #endif 839: 840: #ifdef cpu2 841: sgio r0, CPU2SS 01F7 : 0010_1000_0000_1010_0010_0101 842: #endif 843: 844: #ifdef cpu3 845: sgio r0, CPU3SS 846: #endif 847: 848: jmp cc_uncond, clkoff 01F8 : 0000_0100_0000_0000_0000_1111 849: nop 01F9 : 0000_0000_0000_0000_0000_0000 850: 851: 852: 853: ;######################################### 854: ;# 855: ;# 0x0300: Interrrupt Raw Data Readou 856: ;# 857: ;# Nothing to be done here. 858: ;# 859: ;######################################### 860: 861: 862: org 0x300 863: 864: jmp cc_uncond, clkoff 0300 : 0000_0100_0000_0000_0000_1111 865: nop 0301 : 0000_0000_0000_0000_0000_0000 866: 867: 868: 869: 870: 871: 872: 873: 874: 875: 876: 877: 878: 879: 880: 881: 882: 883: 884: Source file read, 0 error(s), 0 warning(s).