Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.8, Jul 2008 SVN Revision 2158, SVN Date 2008-07-17 Please send any comments to: angelov@kip.uni-heidelberg.de 14:40:08 / 04 Mar 2009 Source code file: SignalProcessing.asm Memory initialisation file: Log file: ../work/cpu2.log Program memory size in words: 4096 Default constants, read from /usr/local/share/trap/asm_mimd.inc 1 CPU2 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 107 ASM_SVN_REV = 2158 1: ;########################################################### 2: ;# 3: ;# Test Program for nonlinearity filter. 4: ;# 5: ;# Input data is taken from event buffer and stored bac 6: ;# another memory region. 7: ;# 8: ;# Marcus Gutfleisch 9: ;# Ruprecht-Karls-Universität Heidelberg, Kirchhoff-Ins 10: ;# 11: ;# Heidelberg, 18.03.2005 12: ;# 13: ;########################################################### 14: 15: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt tttt tttt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt tttt tttt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt tttt tttt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snme eeee ddd 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc cccc cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- ---- --St oam 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- ---- --St oam 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- ---- --St oam 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- ---- --St oam 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- ---- --St oam 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- ---- --St oam 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- ---- --St oam 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- ---- --St oam 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- ---- --St oam 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- ---- --St oam 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- ---- --St oam 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- ---- --St oam 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- ---- ---- --- 30: 31: #def CTGDINI=0x0B80; dddd dddd dddd dddd dddd dddd dddd dddd 32: #def CTGCTRL=0x0B81; ---- ---- ---- ---- ---S idce essb bbbb 33: #def CTGDOUT=0x0B82; DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 34: #def CTPDINI=0x0200; dddd dddd dddd dddd dddd dddd dddd dddd 35: #def CTPCTRL=0x0201; ---- ---- ---- ---- ---S idce essb bbbb 36: #def CTPDOUT=0x0202; DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 37: 38: #def PASADEL=0x3158; ---- ---- ---- ---- ---- ---- aaaa aaa 39: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- ---- --aa aaa 40: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- ---- --aa aaa 41: #def PASADAC=0x315B; ---- ---- ---- ---- ---- ---- aaaa aaa 42: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaaa aaaa aaa 43: #def PASASTL=0x315D; ---- ---- ---- ---- ---- ---- aaaa aaa 44: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- ---- ---- --- 45: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- ---- ---- --- 46: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaaa aaaa aaa 47: #def ADCINB=0x3051; ---- ---- ---- ---- ---- ---- ---- --m 48: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- ---- ---d ddd 49: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssbz hhhe app 50: #def ADCTST=0x3054; ---- ---- ---- ---- ---- ---- ---- --t 51: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- ---- ---- --- 52: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- ---- ---- --- 53: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- ---- ---- --- 54: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- ---- ---- -aa 55: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- ---- -ret aii 56: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaaa aaaa aaa 57: #def SADCEC=0x3166; ---- ---- ---- ---- ---- ---- -daa ate 58: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --AA AAAA AAA 59: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --AA AAAA AAA 60: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --AA AAAA AAA 61: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --AA AAAA AAA 62: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --AA AAAA AAA 63: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --AA AAAA AAA 64: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --AA AAAA AAA 65: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --AA AAAA AAA 66: #def SADCMC=0x3170; ---- ---- ---- ---- ---- ---- aaaa aaa 67: #def SADCOC=0x3171; ---- ---- ---- ---- ---- ---- aaaa aaa 68: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd cccc bbbb aaa 69: #def SADCTC=0x3173; ---- ---- ---- ---- ---- ---- ---- -aa 70: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -eaa aaaa aaa 71: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- ---- ---- -ee 72: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- ---- ---- -oo 73: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- ---- ---- -ii 74: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAAA AAAA AAA 75: #def TPPT0=0x3000; ---- ---- ---- ---- ---- ---- -ddd ddd 76: #def TPPAE=0x3004; ---- ---- ---- ---- ---- ---- -ddd ddd 77: #def TPPGR=0x3003; ---- ---- ---- ---- ---- ---- -ddd ddd 78: #def FLBY=0x3018; ---- ---- ---- ---- ---- ---- ---- --- 79: #def FLL=0x3100; ---- ---- ---- ---- ---- ---- --dd ddd 80: #def FPBY=0x3019; ---- ---- ---- ---- ---- ---- ---- --- 81: #def FPTC=0x3020; ---- ---- ---- ---- ---- ---- ---- --d 82: #def FPNP=0x3021; ---- ---- ---- ---- ---- ---d dddd ddd 83: #def FPCL=0x3022; ---- ---- ---- ---- ---- ---- ---- --- 84: #def FPA=0x3060; --dd dddd dddd dddd dddd dddd dddd ddd 85: #def FGBY=0x301A; ---- ---- ---- ---- ---- ---- ---- --- 86: #def FGFn=0x3080; ---- ---- ---- ---- ---- ---d dddd ddd 87: #def FGAn=0x30A0; ---- ---- ---- ---- ---- ---- --dd ddd 88: #def FGTA=0x3028; ---- ---- ---- ---- ---- dddd dddd ddd 89: #def FGTB=0x3029; ---- ---- ---- ---- ---- dddd dddd ddd 90: #def FGCL=0x302A; ---- ---- ---- ---- ---- ---- ---- --- 91: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd dddd dddd ddd 92: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd dddd dddd ddd 93: #def FTBY=0x301B; ---- ---- ---- ---- ---- ---- ---- --- 94: #def FTAL=0x3030; ---- ---- ---- ---- ---- --dd dddd ddd 95: #def FTLL=0x3031; ---- ---- ---- ---- ---- --dd dddd ddd 96: #def FTLS=0x3032; ---- ---- ---- ---- ---- --dd dddd ddd 97: #def FCBY=0x301C; ---- ---- ---- ---- ---- ---- ---- --- 98: #def FCWn=0x3038; ---- ---- ---- ---- ---- ---- dddd ddd 99: #def TPFS=0x3001; ---- ---- ---- ---- ---- ---- -ddd ddd 100: #def TPFE=0x3002; ---- ---- ---- ---- ---- ---- -ddd ddd 101: #def TPQS0=0x3005; ---- ---- ---- ---- ---- ---- -ddd ddd 102: #def TPQE0=0x3006; ---- ---- ---- ---- ---- ---- -ddd ddd 103: #def TPQS1=0x3007; ---- ---- ---- ---- ---- ---- -ddd ddd 104: #def TPQE1=0x3008; ---- ---- ---- ---- ---- ---- -ddd ddd 105: #def TPHT=0x3041; ---- ---- ---- ---- --dd dddd dddd ddd 106: #def TPVBY=0x3043; ---- ---- ---- ---- ---- ---- ---- --- 107: #def TPVT=0x3042; ---- ---- ---- ---- ---- ---- --dd ddd 108: #def TPFP=0x3040; ---- ---- ---- ---- ---- ---- --dd ddd 109: #def TPL=0x3180; ---- ---- ---- ---- ---- ---- ---d ddd 110: #def TPCL=0x3045; ---- ---- ---- ---- ---- ---- ---d ddd 111: #def TPCT=0x3044; ---- ---- ---- ---- ---- ---- ---d ddd 112: #def TPD=0x3047; ---- ---- ---- ---- ---- ---- ---- ddd 113: #def TPH=0x3140; ---- ---- ---- ---- ---- ---- ---d ddd 114: #def TPCBY=0x3046; ---- ---- ---- ---- ---- ---- ---- --- 115: #def TPCI0=0x3048; ---- ---- ---- ---- ---- ---- ---d ddd 116: #def TPCI1=0x3049; ---- ---- ---- ---- ---- ---- ---d ddd 117: #def TPCI2=0x304A; ---- ---- ---- ---- ---- ---- ---d ddd 118: #def TPCI3=0x304B; ---- ---- ---- ---- ---- ---- ---d ddd 119: #def EBD=0x3009; ---- ---- ---- ---- ---- ---- ---- -dd 120: #def EBSF=0x300C; ---- ---- ---- ---- ---- ---- ---- --- 121: #def EBAQA=0x300A; ---- ---- ---- ---- ---- ---- -ddd ddd 122: #def EBSIM=0x300D; ---- ---- ---- ---- ---- ---- ---- --- 123: #def EBSIA=0x300B; ---- ---- ---- ---- ---- ---- -ddd ddd 124: #def EBR=0x0800; ---- ---- ---- ---- ---- -pdd dddd ddd 125: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pdd dddd ddd 126: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pdd dddd ddd 127: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pdd dddd ddd 128: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pdd dddd ddd 129: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pdd dddd ddd 130: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pdd dddd ddd 131: #def EBW=0x2000; ---- ---- ---- ---- ---- --dd dddd ddd 132: #def EBPP=0x300E; ---- ---- ---- ---- ---- ---- ---- --- 133: #def EBPC=0x300F; ---- ---- ---- ---- ---- ---- ---- --- 134: #def EBP0=0x3010; ---- ---- ---- ---- ---- ---d dddd ddd 135: #def EBP1=0x3011; ---- ---- ---- ---- ---- ---d dddd ddd 136: #def EBP2=0x3012; ---- ---- ---- ---- ---- ---d dddd ddd 137: #def EBP3=0x3013; ---- ---- ---- ---- ---- ---d dddd ddd 138: #def EBIS=0x3014; ---- ---- ---- ---- ---- --dd dddd ddd 139: #def EBIT=0x3015; ---- ---- ---- ---- ---- dddd dddd ddd 140: #def EBIL=0x3016; ---- ---- ---- ---- ---- ---- dddd ddd 141: #def EBIN=0x3017; ---- ---- ---- ---- ---- ---- ---- --- 142: #def EBI=0x0980; dddd dddd dddd dddd dddd dddd dddd ddd 143: #def EBI0=0x0980; dddd dddd dddd dddd dddd dddd dddd dd 144: #def EBI1=0x0981; dddd dddd dddd dddd dddd dddd dddd dd 145: #def EBI2=0x0982; dddd dddd dddd dddd dddd dddd dddd dd 146: #def EBI3=0x0983; dddd dddd dddd dddd dddd dddd dddd dd 147: #def EBI4=0x0984; dddd dddd dddd dddd dddd dddd dddd dd 148: #def EBI5=0x0985; dddd dddd dddd dddd dddd dddd dddd dd 149: #def EBI6=0x0986; dddd dddd dddd dddd dddd dddd dddd dd 150: #def EBI7=0x0987; dddd dddd dddd dddd dddd dddd dddd dd 151: #def EBI8=0x0988; dddd dddd dddd dddd dddd dddd dddd dd 152: #def EBI9=0x0989; dddd dddd dddd dddd dddd dddd dddd dd 153: #def EBIA=0x098A; dddd dddd dddd dddd dddd dddd dddd dd 154: #def EBIB=0x098B; dddd dddd dddd dddd dddd dddd dddd dd 155: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- ---- ---- wwr 156: #def MEMRW=0xD000; ---- ---- ---- ---- ---- ---- -www wrr 157: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- ---b dddd iii 158: #def DMDELA=0xD002; ---- ---- ---- ---- ---- ---- ---- aaa 159: #def DMDELS=0xD003; ---- ---- ---- ---- ---- ---- ---- sss 160: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 161: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 162: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 163: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 164: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 165: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 166: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 167: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 168: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaaa aaaa aaa 169: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaaa aaaa aaa 170: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaaa aaaa aaa 171: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaaa aaaa aaa 172: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmmm mmmm mmm 173: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmmm mmmm mmm 174: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmmm mmmm mmm 175: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmmm mmmm mmm 176: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmmm mmmm mmm 177: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmmm mmmm mmm 178: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmmm mmmm mmm 179: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmmm mmmm mmm 180: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmmm mmmm mmm 181: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmmm mmmm mmm 182: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmmm mmmm mmm 183: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmmm mmmm mmm 184: #def NMOD=0x0D40; ---- ---- ---- ---- ---- ---- ---i cmm 185: #def NTRO=0x0D43; ---- ---- ---- --ii iddd cccb bbaa aff 186: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt tttt tttt ttt 187: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbbb aaaa aaa 188: #def NRRO=0x0D44; ---- ---- ---- --ii iddd cccb bbaa aff 189: #def NTP=0x0D46; pppp pppp pppp pppp pppp pppp pppp ppp 190: #def NP0=0x0D48; ---- ---- ---- ---- ---- -ppp pfff fec 191: #def NP1=0x0D49; ---- ---- ---- ---- ---- -ppp pfff fec 192: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -ppp pfff fec 193: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -ppp pfff fec 194: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLLL CCCC CCC 195: #def NED=0x0D42; ---- ---- ---- ---- orpp ppff ffcc css 196: #def NDLY=0x0D41; --jj jiii hhhg ggff feee dddc ccbb baa 197: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhhh llll lll 198: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DSS EHLZ YXW 199: #def NLE=0x00C2; ---- ---- ---- ---- ---- ---- EEEE EEE 200: #def NFE=0x0DC1; ---- ---- ---- ---- ---- ---- ---- DCB 201: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- ---- ---- --- 202: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- ---- ---S SSS 203: #def NITM0=0x0A08; ---- ---- ---- ---- --tt tttt tttt ttt 204: #def NITM1=0x0A09; ---- ---- ---- ---- --tt tttt tttt ttt 205: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt tttt tttt ttt 206: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt tttt tttt ttt 207: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd dddd dddd ddd 208: #def SMON=0x0A06; ---- ---- ---- ---- ---- dddd dddd ddd 209: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- dddd dddd ddd 210: #def NODP=0x0000; dddd dddd dddd dddd dddd dddd dddd ddd 211: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- ---- ---- 212: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- ---- ---- 213: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- ---- ---- 214: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- ---- ---- 215: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- ---- ---- 216: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- ---- ---- 217: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- ---- ---- 218: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- ---- ---- 219: #def GBUSR0=0x0300; -- readonly 220: #def GBUSR1=0x0301; -- readonly *** End of include file /usr/local/share/trap/conf_va.inc *** Include file ../../assembler.inc 1: ;#define MCM=1; 2: ;#define WAFER=1; 3: #define ROB=1; *** End of include file ../../assembler.inc 18: 19: 20: 21: ;################################################### 22: ;# 23: ;# defines 24: ;# 25: ;################################################### 26: 27: 28: #def EBSIM_FAST = g0 29: #def CPU_SYNC = g1 30: 31: 32: #def ERROR_CTR = c8 33: #def ADD_CTR = c13 34: 35: #def ADD_ADR = 0xC05 36: 37: #ifdef cpu0 38: #def ERROR_ADR = 0xC00 39: #endif 40: #ifdef cpu1 41: #def ERROR_ADR = 0xC08 42: #endif 43: #ifdef cpu2 44: #def ERROR_ADR = 0xC10 45: #endif 46: #ifdef cpu3 47: #def ERROR_ADR = 0xC18 48: #endif 49: 50: 51: 52: ;################################################### 53: ;# 54: ;# 0x0000: Infinite Loop at Instruction Memory 55: ;# 56: ;################################################### 57: 58: 59: org 0x0000 60: 61: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 62: nop 0001 : 0000_0000_0000_0000_0000_0000 63: 64: 65: 66: ;################################################### 67: ;# 68: ;# 0x0010: Interrrupt Clear Jump Address 69: ;# 70: ;# CPU0: switch off all NI LVDS cells 71: ;# switch off NI clock 72: ;# switch off preprocessor cloc 73: ;# switch on filter clock 74: ;# 75: ;# CPU1: end clear state, arm state m 76: ;# 77: ;# CPU2: get tracklet end signature ( 78: ;# 79: ;# CPU3: get data end signature (???) 80: ;# 81: ;################################################### 82: 83: 84: org 0x0010 85: 86: mov 0, r12 0010 : 1100_0110_0000_0000_0000_1100 87: mov 4, r13 0011 : 1100_0110_0000_0000_1000_1101 88: 89: #ifdef cpu0 90: 91: iext EBSIM 92: mov EBSIM, EBSIM_FAST 93: mov 0, CPU_SYNC 94: 95: iext b1111_0101_0000_0000_0010_0000 96: mov b1111_0101_0000_0000_0010_0000, r0 97: jmpr cc_busy, 0 98: sgio r0, SMOFFON 99: 100: mov CMD_EXT_CLR, r0 101: sgio r0, SMCMD 102: 103: #else 104: 105: nop 0012 : 0000_0000_0000_0000_0000_0000 106: nop 0013 : 0000_0000_0000_0000_0000_0000 107: nop 0014 : 0000_0000_0000_0000_0000_0000 108: 109: nop 0015 : 0000_0000_0000_0000_0000_0000 110: nop 0016 : 0000_0000_0000_0000_0000_0000 111: nop 0017 : 0000_0000_0000_0000_0000_0000 112: nop 0018 : 0000_0000_0000_0000_0000_0000 113: 114: nop 0019 : 0000_0000_0000_0000_0000_0000 115: nop 001A : 0000_0000_0000_0000_0000_0000 116: 117: #endif 118: 119: end_cl: jmpr cc_uncond, 0 001B : 0000_0100_0000_0011_0110_1111 120: nop 001C : 0000_0000_0000_0000_0000_0000 121: 122: 123: 124: ;################################################### 125: ;# 126: ;# 0x0100: Interrrupt Tracklet Processing Jump 127: ;# 128: ;# send delayed tracklet end marker 129: ;# 130: ;################################################### 131: 132: 133: org 0x0100 134: 135: #ifdef cpu0 136: nop 137: nop 138: nop 139: nop 140: #endif 141: 142: #ifdef cpu1 143: nop 144: nop 145: nop 146: nop 147: #endif 148: 149: #ifdef cpu2 150: nop 0100 : 0000_0000_0000_0000_0000_0000 151: nop 0101 : 0000_0000_0000_0000_0000_0000 152: nop 0102 : 0000_0000_0000_0000_0000_0000 153: nop 0103 : 0000_0000_0000_0000_0000_0000 154: #endif 155: 156: #ifdef cpu3 157: mov 1, r0 158: jmpr cc_busy, 0 159: sgio r0, EBSIM_FAST 160: nop 161: #endif 162: 163: 164: 165: ;########################################### 166: ;# 167: ;# check result 168: ;# 169: ;########################################### 170: 171: 172: mov EBR0, r8 ; load channel speci 0104 : 1100_0111_0000_0000_0000_1000 173: add r8, c1, r8 ; add +1 due to shif 0105 : 1000_0010_1000_0110_0010_1000 174: mov EBR1, r9 0106 : 1100_0111_0000_1000_0000_1001 175: add r9, c1, r9 0107 : 1000_0010_1001_0110_0010_1001 176: mov EBR2, r10 0108 : 1100_0111_0001_0000_0000_1010 177: add r10, c1, r10 0109 : 1000_0010_1010_0110_0010_1010 178: mov EBR3, r11 010A : 1100_0111_0001_1000_0000_1011 179: add r11, c1, r11 010B : 1000_0010_1011_0110_0010_1011 180: mov EBR4, r12 010C : 1100_0111_0010_0000_0000_1100 181: add r12, c1, r12 010D : 1000_0010_1100_0110_0010_1100 182: mov EBR5, r13 010E : 1100_0111_0010_1000_0000_1101 183: add r13, c1, r13 010F : 1000_0010_1101_0110_0010_1101 184: 185: mov 0, r0 ; r0: time bin numbe 0110 : 1100_0110_0000_0000_0000_0000 186: mov 892, r1 ; r1: correction = | 0111 : 1100_0110_0110_1111_1000_0001 187: 188: loopTT: mov 0, r6 ; r6: error counter 0112 : 1100_0110_0000_0000_0000_0110 189: 190: mov 31, r3 0113 : 1100_0110_0000_0011_1110_0011 191: add r8, r3, r3 ; source offset addr 0114 : 1000_0010_1000_0000_0110_0011 192: add r0, r3, r3 ; source address 0115 : 1000_0010_0000_0000_0110_0011 193: 194: lpio r3, r5 0116 : 1110_0010_0000_0000_0110_0101 195: lpio r3, r5 ; input data word 0117 : 1110_0010_0000_0000_0110_0101 196: 197: shl 2, r5, r3 ; r3: expected input 0118 : 1011_0010_0010_0000_1010_0011 198: 199: sub r3, r1, r3 ; r2: iput - correct 0119 : 1000_1010_0011_0000_0010_0011 200: jmp cc_geu, TTo0 011A : 0000_0100_0000_0000_0000_0000 201: mov 0, r3 011B : 1100_0110_0000_0000_0000_0011 202: 203: TTo0: shl -2, r3, r3 011C : 1011_0011_1110_0000_0110_0011 204: 205: ; r3: expected value 206: 207: TTc0: add r0, r8, r4 ; r4: event buffer a 011D : 1000_0010_0000_0001_0000_0100 208: lpio r4, r5 011E : 1110_0010_0000_0000_1000_0101 209: lpio r4, r5 ; r5: filter result 011F : 1110_0010_0000_0000_1000_0101 210: 211: cmp r3, r5 0120 : 1000_1000_0011_0000_1010_0000 212: jmp cc_eq, TTc1 0121 : 0000_0100_0000_0000_0001_0001 213: add r6, c1, r6 0122 : 1000_0010_0110_0110_0010_0110 214: 215: TTc1: add r0, r9, r4 ; r4: event buffer a 0123 : 1000_0010_0000_0001_0010_0100 216: lpio r4, r5 0124 : 1110_0010_0000_0000_1000_0101 217: lpio r4, r5 ; r5: filter result 0125 : 1110_0010_0000_0000_1000_0101 218: 219: cmp r3, r5 0126 : 1000_1000_0011_0000_1010_0000 220: jmp cc_eq, TTc2 0127 : 0000_0100_0000_0000_0001_0001 221: add r6, c1, r6 0128 : 1000_0010_0110_0110_0010_0110 222: 223: TTc2: add r0, r10, r4 ; r4: event buffer a 0129 : 1000_0010_0000_0001_0100_0100 224: lpio r4, r5 012A : 1110_0010_0000_0000_1000_0101 225: lpio r4, r5 ; r5: filter result 012B : 1110_0010_0000_0000_1000_0101 226: 227: cmp r3, r5 012C : 1000_1000_0011_0000_1010_0000 228: jmp cc_eq, TTc3 012D : 0000_0100_0000_0000_0001_0001 229: add r6, c1, r6 012E : 1000_0010_0110_0110_0010_0110 230: 231: TTc3: add r0, r11, r4 ; r4: event buffer a 012F : 1000_0010_0000_0001_0110_0100 232: lpio r4, r5 0130 : 1110_0010_0000_0000_1000_0101 233: lpio r4, r5 ; r5: filter result 0131 : 1110_0010_0000_0000_1000_0101 234: 235: cmp r3, r5 0132 : 1000_1000_0011_0000_1010_0000 236: jmp cc_eq, TTc4 0133 : 0000_0100_0000_0000_0001_0001 237: add r6, c1, r6 0134 : 1000_0010_0110_0110_0010_0110 238: 239: TTc4: add r0, r12, r4 ; r4: event buffer a 0135 : 1000_0010_0000_0001_1000_0100 240: lpio r4, r5 0136 : 1110_0010_0000_0000_1000_0101 241: lpio r4, r5 ; r5: filter result 0137 : 1110_0010_0000_0000_1000_0101 242: 243: cmp r3, r5 0138 : 1000_1000_0011_0000_1010_0000 244: jmp cc_eq, TTc5 0139 : 0000_0100_0000_0000_0001_0001 245: add r6, c1, r6 013A : 1000_0010_0110_0110_0010_0110 246: 247: #ifdef cpu3 248: TTc5: add r0, r13, r4 ; r4: event buffer a 249: lpio r4, r5 250: lpio r4, r5 ; r5: filter result 251: 252: cmp r3, r5 253: jmp cc_eq, TTend 254: add r6, c1, r6 255: #else 256: nop 013B : 0000_0000_0000_0000_0000_0000 257: nop 013C : 0000_0000_0000_0000_0000_0000 258: nop 013D : 0000_0000_0000_0000_0000_0000 259: 260: nop 013E : 0000_0000_0000_0000_0000_0000 261: nop 013F : 0000_0000_0000_0000_0000_0000 262: TTc5: nop 0140 : 0000_0000_0000_0000_0000_0000 263: #endif 264: 265: TTend: add r6, ERROR_CTR, r6 0141 : 1000_0010_0110_0111_0000_0110 266: jmpr cc_busy, 0 0142 : 0000_0100_0010_1000_0101_0111 267: sgio r6, ERROR_ADR 0143 : 0010_1000_0110_1100_0001_0000 268: 269: add r0, c1, r0 0144 : 1000_0010_0000_0110_0010_0000 270: cmp r0, 31 0145 : 1100_1000_0000_0000_0001_1111 271: jmp cc_ltu, loopTT 0146 : 0000_0100_0000_0000_0001_0000 272: nop 0147 : 0000_0000_0000_0000_0000_0000 273: 274: 275: 276: 277: ;########################################### 278: ;# 279: ;# increase counters 280: ;# 281: ;########################################### 282: 283: 284: #ifdef cpu3 285: 286: mov 1, r1 287: add r1, ADD_CTR, r0 288: jmpr cc_busy, 0 289: sgio r0, ADD_ADR 290: 291: #else 292: 293: nop 0148 : 0000_0000_0000_0000_0000_0000 294: nop 0149 : 0000_0000_0000_0000_0000_0000 295: nop 014A : 0000_0000_0000_0000_0000_0000 296: nop 014B : 0000_0000_0000_0000_0000_0000 297: 298: #endif 299: 300: jmpr cc_busy, 0 014C : 0000_0100_0010_1001_1001_0111 301: 302: 303: 304: 305: ;########################################### 306: ;# 307: ;# copy lower indicator words 308: ;# 309: ;########################################### 310: 311: 312: #ifdef cpu0 313: mov 0x7B8, r15 314: #endif 315: 316: #ifdef cpu1 317: mov 0x7CC, r15 318: #endif 319: 320: #ifdef cpu2 321: mov 0x7E0, r15 014D : 1100_0110_1111_1100_0000_1111 322: #endif 323: 324: #ifdef cpu3 325: mov 0x7F4, r15 326: #endif 327: 328: lpio EBI0, r0 014E : 1110_0111_0011_0000_0000_0000 329: lpio EBI0, r0 014F : 1110_0111_0011_0000_0000_0000 330: sra+ r0 0150 : 0011_1000_0000_0000_0000_0000 331: 332: lpio EBI2, r0 0151 : 1110_0111_0011_0000_0100_0000 333: lpio EBI2, r0 0152 : 1110_0111_0011_0000_0100_0000 334: sra+ r0 0153 : 0011_1000_0000_0000_0000_0000 335: 336: lpio EBI4, r0 0154 : 1110_0111_0011_0000_1000_0000 337: lpio EBI4, r0 0155 : 1110_0111_0011_0000_1000_0000 338: sra+ r0 0156 : 0011_1000_0000_0000_0000_0000 339: 340: lpio EBI6, r0 0157 : 1110_0111_0011_0000_1100_0000 341: lpio EBI6, r0 0158 : 1110_0111_0011_0000_1100_0000 342: sra+ r0 0159 : 0011_1000_0000_0000_0000_0000 343: 344: lpio EBI8, r0 015A : 1110_0111_0011_0001_0000_0000 345: lpio EBI8, r0 015B : 1110_0111_0011_0001_0000_0000 346: sra+ r0 015C : 0011_1000_0000_0000_0000_0000 347: 348: #ifdef cpu3 349: lpio EBIA, r0 350: lpio EBIA, r0 351: sra+ r0 352: #else 353: nop 015D : 0000_0000_0000_0000_0000_0000 354: nop 015E : 0000_0000_0000_0000_0000_0000 355: nop 015F : 0000_0000_0000_0000_0000_0000 356: #endif 357: 358: 359: ;########################################### 360: ;# 361: ;# DMEM address to copy event buffer da 362: ;# beware: byte address = 4 * word addr 363: ;# 364: ;########################################### 365: 366: #ifdef cpu0 367: mov 0x080, r15 368: #endif 369: 370: #ifdef cpu1 371: mov 0x238, r15 372: #endif 373: 374: #ifdef cpu2 375: mov 0x3F0, r15 0160 : 1100_0110_0111_1110_0000_1111 376: #endif 377: 378: #ifdef cpu3 379: mov 0x5A8, r15 380: #endif 381: 382: ;########################################### 383: ;# 384: ;# channel check bits, absolute channel 385: ;# 386: ;########################################### 387: 388: #ifdef cpu0 389: mov 3, r3 390: #endif 391: 392: #ifdef cpu1 393: mov 2, r3 394: #endif 395: 396: #ifdef cpu2 397: mov 3, r3 0161 : 1100_0110_0000_0000_0110_0011 398: #endif 399: 400: #ifdef cpu3 401: mov 2, r3 402: #endif 403: 404: ;########################################### 405: ;# 406: ;# copy event buffer data of CPU's chan 407: ;# 408: ;########################################### 409: 410: mov EBR0, r14 0162 : 1100_0111_0000_0000_0000_1110 411: mov 66, r5 0163 : 1100_0110_0000_1000_0100_0101 412: 413: loop0: lpio+ r0 0164 : 1110_1110_0000_0000_0000_0000 414: lpio+ r0 0165 : 1110_1110_0000_0000_0000_0000 415: lpio+ r1 0166 : 1110_1110_0000_0000_0000_0001 416: lpio r14, r2 0167 : 1110_0010_0000_0001_1100_0010 417: 418: shl 10, r2, r2 0168 : 1011_0010_1010_0000_0100_0010 419: or r1, r2, r2 0169 : 1010_1010_0001_0000_0100_0010 420: shl 10, r2, r2 016A : 1011_0010_1010_0000_0100_0010 421: or r0, r2, r2 016B : 1010_1010_0000_0000_0100_0010 422: shl 2, r2, r2 016C : 1011_0010_0010_0000_0100_0010 423: or r3, r2, r2 016D : 1010_1010_0011_0000_0100_0010 424: 425: sra+ r2 016E : 0011_1000_0010_0000_0000_0000 426: 427: sub r5, c3, r5 016F : 1000_1010_0101_0110_0110_0101 428: jmp cc_gtu, loop0 0170 : 0000_0100_0000_0000_0000_1000 429: 430: ;########################################### 431: ;# 432: ;# copy event buffer data of CPU's chan 433: ;# 434: ;########################################### 435: 436: mov EBR1, r14 0171 : 1100_0111_0000_1000_0000_1110 437: mov 66, r5 0172 : 1100_0110_0000_1000_0100_0101 438: xor r3, c1, r3 0173 : 1010_0010_0011_0110_0010_0011 439: 440: loop1: lpio+ r0 0174 : 1110_1110_0000_0000_0000_0000 441: lpio+ r0 0175 : 1110_1110_0000_0000_0000_0000 442: lpio+ r1 0176 : 1110_1110_0000_0000_0000_0001 443: lpio r14, r2 0177 : 1110_0010_0000_0001_1100_0010 444: 445: shl 10, r2, r2 0178 : 1011_0010_1010_0000_0100_0010 446: or r1, r2, r2 0179 : 1010_1010_0001_0000_0100_0010 447: shl 10, r2, r2 017A : 1011_0010_1010_0000_0100_0010 448: or r0, r2, r2 017B : 1010_1010_0000_0000_0100_0010 449: shl 2, r2, r2 017C : 1011_0010_0010_0000_0100_0010 450: or r3, r2, r2 017D : 1010_1010_0011_0000_0100_0010 451: 452: sra+ r2 017E : 0011_1000_0010_0000_0000_0000 453: 454: sub r5, c3, r5 017F : 1000_1010_0101_0110_0110_0101 455: jmp cc_gtu, loop1 0180 : 0000_0100_0000_0000_0000_1000 456: 457: ;########################################### 458: ;# 459: ;# copy event buffer data of CPU's chan 460: ;# 461: ;########################################### 462: 463: mov EBR2, r14 0181 : 1100_0111_0001_0000_0000_1110 464: mov 66, r5 0182 : 1100_0110_0000_1000_0100_0101 465: xor r3, c1, r3 0183 : 1010_0010_0011_0110_0010_0011 466: 467: loop2: lpio+ r0 0184 : 1110_1110_0000_0000_0000_0000 468: lpio+ r0 0185 : 1110_1110_0000_0000_0000_0000 469: lpio+ r1 0186 : 1110_1110_0000_0000_0000_0001 470: lpio r14, r2 0187 : 1110_0010_0000_0001_1100_0010 471: 472: shl 10, r2, r2 0188 : 1011_0010_1010_0000_0100_0010 473: or r1, r2, r2 0189 : 1010_1010_0001_0000_0100_0010 474: shl 10, r2, r2 018A : 1011_0010_1010_0000_0100_0010 475: or r0, r2, r2 018B : 1010_1010_0000_0000_0100_0010 476: shl 2, r2, r2 018C : 1011_0010_0010_0000_0100_0010 477: or r3, r2, r2 018D : 1010_1010_0011_0000_0100_0010 478: 479: sra+ r2 018E : 0011_1000_0010_0000_0000_0000 480: 481: sub r5, c3, r5 018F : 1000_1010_0101_0110_0110_0101 482: jmp cc_gtu, loop2 0190 : 0000_0100_0000_0000_0000_1000 483: 484: ;########################################### 485: ;# 486: ;# copy event buffer data of CPU's chan 487: ;# 488: ;########################################### 489: 490: mov EBR3, r14 0191 : 1100_0111_0001_1000_0000_1110 491: mov 66, r5 0192 : 1100_0110_0000_1000_0100_0101 492: xor r3, c1, r3 0193 : 1010_0010_0011_0110_0010_0011 493: 494: loop3: lpio+ r0 0194 : 1110_1110_0000_0000_0000_0000 495: lpio+ r0 0195 : 1110_1110_0000_0000_0000_0000 496: lpio+ r1 0196 : 1110_1110_0000_0000_0000_0001 497: lpio r14, r2 0197 : 1110_0010_0000_0001_1100_0010 498: 499: shl 10, r2, r2 0198 : 1011_0010_1010_0000_0100_0010 500: or r1, r2, r2 0199 : 1010_1010_0001_0000_0100_0010 501: shl 10, r2, r2 019A : 1011_0010_1010_0000_0100_0010 502: or r0, r2, r2 019B : 1010_1010_0000_0000_0100_0010 503: shl 2, r2, r2 019C : 1011_0010_0010_0000_0100_0010 504: or r3, r2, r2 019D : 1010_1010_0011_0000_0100_0010 505: 506: sra+ r2 019E : 0011_1000_0010_0000_0000_0000 507: 508: sub r5, c3, r5 019F : 1000_1010_0101_0110_0110_0101 509: jmp cc_gtu, loop3 01A0 : 0000_0100_0000_0000_0000_1000 510: 511: ;########################################### 512: ;# 513: ;# copy event buffer data of CPU's chan 514: ;# 515: ;########################################### 516: 517: mov EBR4, r14 01A1 : 1100_0111_0010_0000_0000_1110 518: mov 66, r5 01A2 : 1100_0110_0000_1000_0100_0101 519: xor r3, c1, r3 01A3 : 1010_0010_0011_0110_0010_0011 520: 521: loop4: lpio+ r0 01A4 : 1110_1110_0000_0000_0000_0000 522: lpio+ r0 01A5 : 1110_1110_0000_0000_0000_0000 523: lpio+ r1 01A6 : 1110_1110_0000_0000_0000_0001 524: lpio r14, r2 01A7 : 1110_0010_0000_0001_1100_0010 525: 526: shl 10, r2, r2 01A8 : 1011_0010_1010_0000_0100_0010 527: or r1, r2, r2 01A9 : 1010_1010_0001_0000_0100_0010 528: shl 10, r2, r2 01AA : 1011_0010_1010_0000_0100_0010 529: or r0, r2, r2 01AB : 1010_1010_0000_0000_0100_0010 530: shl 2, r2, r2 01AC : 1011_0010_0010_0000_0100_0010 531: or r3, r2, r2 01AD : 1010_1010_0011_0000_0100_0010 532: 533: sra+ r2 01AE : 0011_1000_0010_0000_0000_0000 534: 535: sub r5, c3, r5 01AF : 1000_1010_0101_0110_0110_0101 536: jmp cc_gtu, loop4 01B0 : 0000_0100_0000_0000_0000_1000 537: 538: ;########################################### 539: ;# 540: ;# copy event buffer data of CPU's chan 541: ;# 542: ;########################################### 543: 544: #ifdef cpu3 545: mov EBR5, r14 546: mov 66, r5 547: xor r3, c1, r3 548: 549: loop5: lpio+ r0 550: lpio+ r0 551: lpio+ r1 552: lpio r14, r2 553: 554: shl 10, r2, r2 555: or r1, r2, r2 556: shl 10, r2, r2 557: or r0, r2, r2 558: shl 2, r2, r2 559: or r3, r2, r2 560: 561: sra+ r2 562: 563: sub r5, c3, r5 564: jmp cc_gtu, loop5 565: #else 566: nop 01B1 : 0000_0000_0000_0000_0000_0000 567: nop 01B2 : 0000_0000_0000_0000_0000_0000 568: nop 01B3 : 0000_0000_0000_0000_0000_0000 569: nop 01B4 : 0000_0000_0000_0000_0000_0000 570: nop 01B5 : 0000_0000_0000_0000_0000_0000 571: nop 01B6 : 0000_0000_0000_0000_0000_0000 572: nop 01B7 : 0000_0000_0000_0000_0000_0000 573: nop 01B8 : 0000_0000_0000_0000_0000_0000 574: nop 01B9 : 0000_0000_0000_0000_0000_0000 575: nop 01BA : 0000_0000_0000_0000_0000_0000 576: nop 01BB : 0000_0000_0000_0000_0000_0000 577: nop 01BC : 0000_0000_0000_0000_0000_0000 578: nop 01BD : 0000_0000_0000_0000_0000_0000 579: nop 01BE : 0000_0000_0000_0000_0000_0000 580: nop 01BF : 0000_0000_0000_0000_0000_0000 581: nop 01C0 : 0000_0000_0000_0000_0000_0000 582: #endif 583: 584: 585: ;########################################### 586: ;# 587: ;# end current state, goto clear state 588: ;# 589: ;########################################### 590: 591: 592: #ifdef cpu3 593: 594: mov 0, r0 595: jmpr cc_busy, 0 596: sgio r0, EBSIM_FAST 597: 598: #ifdef MCM 599: mov 0, r0 600: jmpr cc_busy, 0 601: iext SEBDOU 602: sgio r0, SEBDOU 603: mov 5, r0 604: jmpr cc_busy, 0 605: iext SEBDEN 606: sgio r0, SEBDEN 607: #endif 608: 609: jmpr cc_busy, 0 610: mov CMD_LP, r0 611: sgio r0, SMCMD 612: 613: #else 614: 615: nop 01C1 : 0000_0000_0000_0000_0000_0000 616: nop 01C2 : 0000_0000_0000_0000_0000_0000 617: nop 01C3 : 0000_0000_0000_0000_0000_0000 618: 619: nop 01C4 : 0000_0000_0000_0000_0000_0000 620: nop 01C5 : 0000_0000_0000_0000_0000_0000 621: 622: #endif 623: 624: 625: 626: ;########################################### 627: ;# 628: ;# switch off own clock after transfer 629: ;# 630: ;########################################### 631: 632: 633: clkoff: mov 0, r0 01C6 : 1100_0110_0000_0000_0000_0000 634: jmpr cc_busy, 0 01C7 : 0000_0100_0011_1000_1111_0111 635: 636: #ifdef cpu0 637: sgio r0, CPU0SS 638: #endif 639: 640: #ifdef cpu1 641: sgio r0, CPU1SS 642: #endif 643: 644: #ifdef cpu2 645: sgio r0, CPU2SS 01C8 : 0010_1000_0000_1010_0010_0101 646: #endif 647: 648: #ifdef cpu3 649: sgio r0, CPU3SS 650: #endif 651: 652: jmp cc_uncond, clkoff 01C9 : 0000_0100_0000_0000_0000_1111 653: nop 01CA : 0000_0000_0000_0000_0000_0000 654: 655: 656: 657: ;################################################### 658: ;# 659: ;# 0x0300: Interrrupt Raw Data Readout Jump Add 660: ;# 661: ;# Nothing to be done here. 662: ;# 663: ;################################################### 664: 665: 666: org 0x300 667: 668: jmp cc_uncond, clkoff 0300 : 0000_0100_0000_0000_0000_1111 669: nop 0301 : 0000_0000_0000_0000_0000_0000 670: 671: 672: 673: 674: 675: 676: 677: 678: 679: 680: 681: 682: 683: 684: 685: 686: 687: 688: Source file read, 0 error(s), 0 warning(s).