Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.6, Dec 2007 SVN Revision 0, SVN Date 2007-12-27 Please send any comments to: angelov@kip.uni-heidelberg.de 18:34:51 / 21 Apr 2008 Source code file: SignalProcessing.asm Memory initialisation file: Log file: ../work/cpu2.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU2 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 107 ASM_SVN_REV = 0 1: ;################################################# 2: ;# 3: ;# Test Program for nonlinearity filter. 4: ;# 5: ;# Input data is taken from event buffer and 6: ;# another memory region. 7: ;# 8: ;# Marcus Gutfleisch 9: ;# Ruprecht-Karls-Universität Heidelberg, Kir 10: ;# 11: ;# Heidelberg, 18.03.2005 12: ;# 13: ;################################################# 14: 15: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: 31: #def CTGDINI=0x0B80; dddd dddd dddd dddd dddd dddd 32: #def CTGCTRL=0x0B81; ---- ---- ---- ---- ---S idce 33: #def CTGDOUT=0x0B82; DDDD DDDD DDDD DDDD DDDD DDDD 34: #def CTPDINI=0x0200; dddd dddd dddd dddd dddd dddd 35: #def CTPCTRL=0x0201; ---- ---- ---- ---- ---S idce 36: #def CTPDOUT=0x0202; DDDD DDDD DDDD DDDD DDDD DDDD 37: 38: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 39: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 40: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 41: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 42: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 43: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 44: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 45: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 46: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 47: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 48: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 49: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 50: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 51: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 52: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 53: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 54: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 55: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 56: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 57: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 58: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 59: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 60: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 61: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 62: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 63: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 64: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 65: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 66: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 67: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 68: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 69: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 70: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 71: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 72: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 73: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 74: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 75: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 76: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 77: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 78: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 79: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 80: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 81: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 82: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 83: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 84: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 85: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 86: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 87: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 88: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 89: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 90: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 91: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 92: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 93: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 94: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 95: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 96: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 97: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 98: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 99: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 100: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 101: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 102: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 103: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 104: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 105: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 106: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 107: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 108: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 109: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 110: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 111: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 112: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 113: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 114: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 115: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 116: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 117: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 118: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 119: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 120: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 121: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 122: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 123: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 124: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 125: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 126: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 127: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 128: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 129: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 130: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 131: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 132: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 133: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 134: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 135: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 136: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 137: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 138: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 139: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 140: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 141: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 142: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 143: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 144: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 145: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 146: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 147: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 148: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 149: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 150: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 151: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 152: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 153: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 154: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 155: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 156: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 157: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 158: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 159: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 160: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 161: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 162: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 163: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 164: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 165: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 166: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 167: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 168: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 169: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 170: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 171: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 172: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 173: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 174: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 175: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 176: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 177: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 178: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 179: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 180: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 181: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 182: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 183: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 184: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 185: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 186: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 187: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 188: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 189: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 190: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 191: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 192: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 193: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 194: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 195: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 196: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 197: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 198: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 199: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 200: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 201: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 202: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 203: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 204: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 205: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 206: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 207: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 208: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 209: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 210: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 211: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 212: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 213: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 214: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 215: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 216: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 217: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 218: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- 219: #def GBUSR0=0x0300; -- readonly 220: #def GBUSR1=0x0301; -- readonly *** End of include file /cad/tools/bin//conf_va.inc *** Include file ../../assembler.inc 1: ;#define MCM=1; 2: ;#define WAFER=1; 3: #define ROB=1; *** End of include file ../../assembler.inc 18: 19: 20: 21: ;######################################### 22: ;# 23: ;# defines 24: ;# 25: ;######################################### 26: 27: 28: #def CPU_SYNC = g0 29: 30: 31: #def CC_ERROR_CTR = c8 32: #def LV_ERROR_CTR = c9 33: #def OFFSET_CTR = c12 34: #def LS_CTR = c13 35: 36: #def OFFSET_ADR = 0xC04 37: #def AL_ADR = 0xC05 38: 39: #ifdef cpu0 40: #def CC_ERROR_ADR = 0xC00 41: #def LV_ERROR_ADR = 0xC01 42: #endif 43: #ifdef cpu1 44: #def CC_ERROR_ADR = 0xC08 45: #def LV_ERROR_ADR = 0xC09 46: #endif 47: #ifdef cpu2 48: #def CC_ERROR_ADR = 0xC10 49: #def LV_ERROR_ADR = 0xC11 50: #endif 51: #ifdef cpu3 52: #def CC_ERROR_ADR = 0xC18 53: #def LV_ERROR_ADR = 0xC19 54: #endif 55: 56: 57: 58: ;######################################### 59: ;# 60: ;# 0x0000: Infinite Loop at Instructi 61: ;# 62: ;######################################### 63: 64: 65: org 0x0000 66: 67: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 68: nop 0001 : 0000_0000_0000_0000_0000_0000 69: 70: 71: 72: ;######################################### 73: ;# 74: ;# 0x0010: Interrrupt Clear Jump Addr 75: ;# 76: ;# CPU0: switch off all NI 77: ;# switch off NI cloc 78: ;# switch off preproc 79: ;# switch on filter 80: ;# 81: ;# CPU1: end clear state, a 82: ;# 83: ;# CPU2: get tracklet end s 84: ;# 85: ;# CPU3: get data end signa 86: ;# 87: ;######################################### 88: 89: 90: org 0x0010 91: 92: mov 0, r12 0010 : 1100_0110_0000_0000_0000_1100 93: mov 4, r13 0011 : 1100_0110_0000_0000_1000_1101 94: 95: #ifdef cpu0 96: 97: mov CMD_EXT_CLR, r0 98: mov 1024, r2 99: jmpr cc_busy, 0 100: cmp r2, OFFSET_CTR 101: jmp cc_leu, end_lp 102: sgio r0, SMCMD 103: 104: #else 105: 106: #ifdef MCM 107: #ifdef cpu1 108: mov 0, r0 109: iext SEBDOU 110: sgio r0, SEBDOU 111: #else 112: nop 113: nop 114: nop 115: #endif 116: #endif 117: 118: nop 0012 : 0000_0000_0000_0000_0000_0000 119: nop 0013 : 0000_0000_0000_0000_0000_0000 120: nop 0014 : 0000_0000_0000_0000_0000_0000 121: 122: #endif 123: 124: end_cl: jmpr cc_uncond, 0 0015 : 0000_0100_0000_0010_1010_1111 125: nop 0016 : 0000_0000_0000_0000_0000_0000 126: 127: end_lp: 128: #ifdef MCM 129: mov 5, r0 130: iext SEBDEN 131: sgio r0, SEBDEN 132: jmpr cc_busy, 0 133: #endif 134: 135: mov CMD_LP, r0 0017 : 1100_0110_0000_0010_0100_0000 136: sgio r0, SMCMD 0018 : 0010_1000_0000_1010_0000_0100 137: 138: jmpr cc_uncond, 0 0019 : 0000_0100_0000_0011_0010_1111 139: nop 001A : 0000_0000_0000_0000_0000_0000 140: 141: 142: 143: ;######################################### 144: ;# 145: ;# 0x0100: Interrrupt Tracklet Proces 146: ;# 147: ;# send delayed tracklet end 148: ;# 149: ;######################################### 150: 151: 152: org 0x0100 153: 154: #ifdef cpu0 155: mov 6, r0 156: iext EBD 157: mov EBD, r1 158: jmpr cc_busy, 0 159: sgio r0, r1 160: #endif 161: 162: #ifdef cpu1 163: nop 164: nop 165: nop 166: nop 167: nop 168: #endif 169: 170: #ifdef cpu2 171: nop 0100 : 0000_0000_0000_0000_0000_0000 172: nop 0101 : 0000_0000_0000_0000_0000_0000 173: nop 0102 : 0000_0000_0000_0000_0000_0000 174: nop 0103 : 0000_0000_0000_0000_0000_0000 175: nop 0104 : 0000_0000_0000_0000_0000_0000 176: #endif 177: 178: #ifdef cpu3 179: mov 1, r0 180: iext EBSIM 181: mov EBSIM, r1 182: jmpr cc_busy, 0 183: sgio r0, r1 184: #endif 185: 186: 187: 188: ;################################# 189: ;# 190: ;# increase counters (1/3) 191: ;# 192: ;################################# 193: 194: 195: #ifdef cpu3 196: 197: mov 1, r1 198: add r1, LS_CTR, r0 199: jmpr cc_busy, 0 200: sgio r0, AL_ADR 201: 202: #else 203: 204: nop 0105 : 0000_0000_0000_0000_0000_0000 205: nop 0106 : 0000_0000_0000_0000_0000_0000 206: nop 0107 : 0000_0000_0000_0000_0000_0000 207: nop 0108 : 0000_0000_0000_0000_0000_0000 208: 209: #endif 210: 211: jmpr cc_busy, 0 0109 : 0000_0100_0010_0001_0011_0111 212: 213: 214: 215: ;################################# 216: ;# 217: ;# copy lower indicator words 218: ;# 219: ;################################# 220: 221: 222: #ifdef cpu0 223: mov 0x7B8, r15 224: #endif 225: 226: #ifdef cpu1 227: mov 0x7CC, r15 228: #endif 229: 230: #ifdef cpu2 231: mov 0x7E0, r15 010A : 1100_0110_1111_1100_0000_1111 232: #endif 233: 234: #ifdef cpu3 235: mov 0x7F4, r15 236: #endif 237: 238: lpio EBI0, r0 010B : 1110_0111_0011_0000_0000_0000 239: lpio EBI0, r0 010C : 1110_0111_0011_0000_0000_0000 240: sra+ r0 010D : 0011_1000_0000_0000_0000_0000 241: 242: lpio EBI2, r0 010E : 1110_0111_0011_0000_0100_0000 243: lpio EBI2, r0 010F : 1110_0111_0011_0000_0100_0000 244: sra+ r0 0110 : 0011_1000_0000_0000_0000_0000 245: 246: lpio EBI4, r0 0111 : 1110_0111_0011_0000_1000_0000 247: lpio EBI4, r0 0112 : 1110_0111_0011_0000_1000_0000 248: sra+ r0 0113 : 0011_1000_0000_0000_0000_0000 249: 250: lpio EBI6, r0 0114 : 1110_0111_0011_0000_1100_0000 251: lpio EBI6, r0 0115 : 1110_0111_0011_0000_1100_0000 252: sra+ r0 0116 : 0011_1000_0000_0000_0000_0000 253: 254: lpio EBI8, r0 0117 : 1110_0111_0011_0001_0000_0000 255: lpio EBI8, r0 0118 : 1110_0111_0011_0001_0000_0000 256: sra+ r0 0119 : 0011_1000_0000_0000_0000_0000 257: 258: #ifdef cpu3 259: lpio EBIA, r0 260: lpio EBIA, r0 261: sra+ r0 262: #else 263: nop 011A : 0000_0000_0000_0000_0000_0000 264: nop 011B : 0000_0000_0000_0000_0000_0000 265: nop 011C : 0000_0000_0000_0000_0000_0000 266: #endif 267: 268: 269: ;################################# 270: ;# 271: ;# DMEM address to copy event 272: ;# beware: byte address = 4 * 273: ;# 274: ;################################# 275: 276: #ifdef cpu0 277: mov 0x080, r15 278: #endif 279: 280: #ifdef cpu1 281: mov 0x238, r15 282: #endif 283: 284: #ifdef cpu2 285: mov 0x3F0, r15 011D : 1100_0110_0111_1110_0000_1111 286: #endif 287: 288: #ifdef cpu3 289: mov 0x5A8, r15 290: #endif 291: 292: ;################################# 293: ;# 294: ;# channel check bits, absolu 295: ;# 296: ;################################# 297: 298: #ifdef cpu0 299: mov 3, r3 300: #endif 301: 302: #ifdef cpu1 303: mov 2, r3 304: #endif 305: 306: #ifdef cpu2 307: mov 3, r3 011E : 1100_0110_0000_0000_0110_0011 308: #endif 309: 310: #ifdef cpu3 311: mov 2, r3 312: #endif 313: 314: ;################################# 315: ;# 316: ;# copy event buffer data of 317: ;# 318: ;################################# 319: 320: mov EBR0, r14 011F : 1100_0111_0000_0000_0000_1110 321: mov 66, r5 0120 : 1100_0110_0000_1000_0100_0101 322: 323: loop0: lpio+ r0 0121 : 1110_1110_0000_0000_0000_0000 324: lpio+ r0 0122 : 1110_1110_0000_0000_0000_0000 325: lpio+ r1 0123 : 1110_1110_0000_0000_0000_0001 326: lpio r14, r2 0124 : 1110_0010_0000_0001_1100_0010 327: 328: shl 10, r2, r2 0125 : 1011_0010_1010_0000_0100_0010 329: or r1, r2, r2 0126 : 1010_1010_0001_0000_0100_0010 330: shl 10, r2, r2 0127 : 1011_0010_1010_0000_0100_0010 331: or r0, r2, r2 0128 : 1010_1010_0000_0000_0100_0010 332: shl 2, r2, r2 0129 : 1011_0010_0010_0000_0100_0010 333: or r3, r2, r2 012A : 1010_1010_0011_0000_0100_0010 334: 335: sra+ r2 012B : 0011_1000_0010_0000_0000_0000 336: 337: sub r5, c3, r5 012C : 1000_1010_0101_0110_0110_0101 338: jmp cc_gtu, loop0 012D : 0000_0100_0000_0000_0000_1000 339: 340: ;################################# 341: ;# 342: ;# copy event buffer data of 343: ;# 344: ;################################# 345: 346: mov EBR1, r14 012E : 1100_0111_0000_1000_0000_1110 347: mov 66, r5 012F : 1100_0110_0000_1000_0100_0101 348: xor r3, c1, r3 0130 : 1010_0010_0011_0110_0010_0011 349: 350: loop1: lpio+ r0 0131 : 1110_1110_0000_0000_0000_0000 351: lpio+ r0 0132 : 1110_1110_0000_0000_0000_0000 352: lpio+ r1 0133 : 1110_1110_0000_0000_0000_0001 353: lpio r14, r2 0134 : 1110_0010_0000_0001_1100_0010 354: 355: shl 10, r2, r2 0135 : 1011_0010_1010_0000_0100_0010 356: or r1, r2, r2 0136 : 1010_1010_0001_0000_0100_0010 357: shl 10, r2, r2 0137 : 1011_0010_1010_0000_0100_0010 358: or r0, r2, r2 0138 : 1010_1010_0000_0000_0100_0010 359: shl 2, r2, r2 0139 : 1011_0010_0010_0000_0100_0010 360: or r3, r2, r2 013A : 1010_1010_0011_0000_0100_0010 361: 362: sra+ r2 013B : 0011_1000_0010_0000_0000_0000 363: 364: sub r5, c3, r5 013C : 1000_1010_0101_0110_0110_0101 365: jmp cc_gtu, loop1 013D : 0000_0100_0000_0000_0000_1000 366: 367: ;################################# 368: ;# 369: ;# copy event buffer data of 370: ;# 371: ;################################# 372: 373: mov EBR2, r14 013E : 1100_0111_0001_0000_0000_1110 374: mov 66, r5 013F : 1100_0110_0000_1000_0100_0101 375: xor r3, c1, r3 0140 : 1010_0010_0011_0110_0010_0011 376: 377: loop2: lpio+ r0 0141 : 1110_1110_0000_0000_0000_0000 378: lpio+ r0 0142 : 1110_1110_0000_0000_0000_0000 379: lpio+ r1 0143 : 1110_1110_0000_0000_0000_0001 380: lpio r14, r2 0144 : 1110_0010_0000_0001_1100_0010 381: 382: shl 10, r2, r2 0145 : 1011_0010_1010_0000_0100_0010 383: or r1, r2, r2 0146 : 1010_1010_0001_0000_0100_0010 384: shl 10, r2, r2 0147 : 1011_0010_1010_0000_0100_0010 385: or r0, r2, r2 0148 : 1010_1010_0000_0000_0100_0010 386: shl 2, r2, r2 0149 : 1011_0010_0010_0000_0100_0010 387: or r3, r2, r2 014A : 1010_1010_0011_0000_0100_0010 388: 389: sra+ r2 014B : 0011_1000_0010_0000_0000_0000 390: 391: sub r5, c3, r5 014C : 1000_1010_0101_0110_0110_0101 392: jmp cc_gtu, loop2 014D : 0000_0100_0000_0000_0000_1000 393: 394: ;################################# 395: ;# 396: ;# copy event buffer data of 397: ;# 398: ;################################# 399: 400: mov EBR3, r14 014E : 1100_0111_0001_1000_0000_1110 401: mov 66, r5 014F : 1100_0110_0000_1000_0100_0101 402: xor r3, c1, r3 0150 : 1010_0010_0011_0110_0010_0011 403: 404: loop3: lpio+ r0 0151 : 1110_1110_0000_0000_0000_0000 405: lpio+ r0 0152 : 1110_1110_0000_0000_0000_0000 406: lpio+ r1 0153 : 1110_1110_0000_0000_0000_0001 407: lpio r14, r2 0154 : 1110_0010_0000_0001_1100_0010 408: 409: shl 10, r2, r2 0155 : 1011_0010_1010_0000_0100_0010 410: or r1, r2, r2 0156 : 1010_1010_0001_0000_0100_0010 411: shl 10, r2, r2 0157 : 1011_0010_1010_0000_0100_0010 412: or r0, r2, r2 0158 : 1010_1010_0000_0000_0100_0010 413: shl 2, r2, r2 0159 : 1011_0010_0010_0000_0100_0010 414: or r3, r2, r2 015A : 1010_1010_0011_0000_0100_0010 415: 416: sra+ r2 015B : 0011_1000_0010_0000_0000_0000 417: 418: sub r5, c3, r5 015C : 1000_1010_0101_0110_0110_0101 419: jmp cc_gtu, loop3 015D : 0000_0100_0000_0000_0000_1000 420: 421: ;################################# 422: ;# 423: ;# copy event buffer data of 424: ;# 425: ;################################# 426: 427: mov EBR4, r14 015E : 1100_0111_0010_0000_0000_1110 428: mov 66, r5 015F : 1100_0110_0000_1000_0100_0101 429: xor r3, c1, r3 0160 : 1010_0010_0011_0110_0010_0011 430: 431: loop4: lpio+ r0 0161 : 1110_1110_0000_0000_0000_0000 432: lpio+ r0 0162 : 1110_1110_0000_0000_0000_0000 433: lpio+ r1 0163 : 1110_1110_0000_0000_0000_0001 434: lpio r14, r2 0164 : 1110_0010_0000_0001_1100_0010 435: 436: shl 10, r2, r2 0165 : 1011_0010_1010_0000_0100_0010 437: or r1, r2, r2 0166 : 1010_1010_0001_0000_0100_0010 438: shl 10, r2, r2 0167 : 1011_0010_1010_0000_0100_0010 439: or r0, r2, r2 0168 : 1010_1010_0000_0000_0100_0010 440: shl 2, r2, r2 0169 : 1011_0010_0010_0000_0100_0010 441: or r3, r2, r2 016A : 1010_1010_0011_0000_0100_0010 442: 443: sra+ r2 016B : 0011_1000_0010_0000_0000_0000 444: 445: sub r5, c3, r5 016C : 1000_1010_0101_0110_0110_0101 446: jmp cc_gtu, loop4 016D : 0000_0100_0000_0000_0000_1000 447: 448: ;################################# 449: ;# 450: ;# copy event buffer data of 451: ;# 452: ;################################# 453: 454: #ifdef cpu3 455: mov EBR5, r14 456: mov 66, r5 457: xor r3, c1, r3 458: 459: loop5: lpio+ r0 460: lpio+ r0 461: lpio+ r1 462: lpio r14, r2 463: 464: shl 10, r2, r2 465: or r1, r2, r2 466: shl 10, r2, r2 467: or r0, r2, r2 468: shl 2, r2, r2 469: or r3, r2, r2 470: 471: sra+ r2 472: 473: sub r5, c3, r5 474: jmp cc_gtu, loop5 475: #else 476: nop 016E : 0000_0000_0000_0000_0000_0000 477: nop 016F : 0000_0000_0000_0000_0000_0000 478: nop 0170 : 0000_0000_0000_0000_0000_0000 479: nop 0171 : 0000_0000_0000_0000_0000_0000 480: nop 0172 : 0000_0000_0000_0000_0000_0000 481: nop 0173 : 0000_0000_0000_0000_0000_0000 482: nop 0174 : 0000_0000_0000_0000_0000_0000 483: nop 0175 : 0000_0000_0000_0000_0000_0000 484: nop 0176 : 0000_0000_0000_0000_0000_0000 485: nop 0177 : 0000_0000_0000_0000_0000_0000 486: nop 0178 : 0000_0000_0000_0000_0000_0000 487: nop 0179 : 0000_0000_0000_0000_0000_0000 488: nop 017A : 0000_0000_0000_0000_0000_0000 489: nop 017B : 0000_0000_0000_0000_0000_0000 490: nop 017C : 0000_0000_0000_0000_0000_0000 491: nop 017D : 0000_0000_0000_0000_0000_0000 492: #endif 493: 494: 495: 496: ;################################# 497: ;# 498: ;# send all but cpu 3 to infi 499: ;# 500: ;################################# 501: 502: 503: 504: #ifdef cpu3 505: nop 506: #else 507: jmpr cc_uncond, 0 017E : 0000_0100_0010_1111_1100_1111 508: #endif 509: 510: nop 017F : 0000_0000_0000_0000_0000_0000 511: 512: 513: ;################################# 514: ;# 515: ;# increase counters (2/3) 516: ;# 517: ;################################# 518: 519: 520: mov 1, r1 0180 : 1100_0110_0000_0000_0010_0001 521: add r1, OFFSET_CTR, r0 0181 : 1000_0010_0001_0111_1000_0000 522: jmpr cc_busy, 0 0182 : 0000_0100_0011_0000_0101_0111 523: sgio r0, OFFSET_ADR 0183 : 0010_1000_0000_1100_0000_0100 524: 525: 526: 527: ;################################# 528: ;# 529: ;# Prepare Pedestal Follower 530: ;# 531: ;################################# 532: 533: 534: mov 0, r0 0184 : 1100_0110_0000_0000_0000_0000 535: iext EBSIM 0185 : 0101_0000_0000_0000_0000_0011 536: mov EBSIM, r1 0186 : 1100_0110_0000_0001_1010_0001 537: jmpr cc_busy, 0 0187 : 0000_0100_0011_0000_1111_0111 538: sgio r0, r1 0188 : 0010_0100_0000_0000_0010_0000 539: 540: mov 0, r0 0189 : 1100_0110_0000_0000_0000_0000 541: iext EBD 018A : 0101_0000_0000_0000_0000_0011 542: mov EBD, r1 018B : 1100_0110_0000_0001_0010_0001 543: jmpr cc_busy, 0 018C : 0000_0100_0011_0001_1001_0111 544: sgio r0, r1 018D : 0010_0100_0000_0000_0010_0000 545: 546: 547: mov 0, r6 ; r6: cha 018E : 1100_0110_0000_0000_0000_0110 548: mov 0, r7 ; r7: lim 018F : 1100_0110_0000_0000_0000_0111 549: iext FILCLK 0190 : 0101_0000_0000_0000_0000_0000 550: mov FILCLK, r8 ; r8: FIL 0191 : 1100_0111_0100_0101_0100_1000 551: mov 0, r9 ; r9: :=0 0192 : 1100_0110_0000_0000_0000_1001 552: mov 1, r10 ; r10: :=1 0193 : 1100_0110_0000_0000_0010_1010 553: iext 0x40000 0194 : 0101_0000_0000_0000_0100_0000 554: mov 0x40000, r11 ; r11: tim 0195 : 1100_0110_0000_0000_0000_1011 555: mov 0x010, r12 ; r12: tim 0196 : 1100_0110_0000_0010_0000_1100 556: mov 0, r13 ; r13: DBA 0197 : 1100_0110_0000_0000_0000_1101 557: iext FPA 0198 : 0101_0000_0000_0000_0000_0011 558: mov FPA, r14 ; r14: FPA 0199 : 1100_0110_0000_1100_0000_1110 559: iext 0xF000 019A : 0101_0000_0000_0000_0000_1111 560: mov 0xF000, r15 ; r15: DBA 019B : 1100_0110_0000_0000_0000_1111 561: 562: mov 1, r0 019C : 1100_0110_0000_0000_0010_0000 563: iext FPCL 019D : 0101_0000_0000_0000_0000_0011 564: mov FPCL, r1 019E : 1100_0110_0000_0100_0100_0001 565: jmpr cc_busy, 0 019F : 0000_0100_0011_0011_1111_0111 566: sgio r0, r1 ; activate 01A0 : 0010_0100_0000_0000_0010_0000 567: 568: 569: ;################################# 570: ;# 571: ;# Do Pedestal Follower Testi 572: ;# 573: ;# r0: time loop counter 574: ;# r1: value of channel 0 575: ;# r2: value of channel i 576: ;# r3: channel check loop 577: ;# r4: 578: ;# r5: DBANK write addres 579: ;# 580: ;################################# 581: 582: 583: dbkl: jmpr cc_busy, 0 01A1 : 0000_0100_0011_0100_0011_0111 584: sgio r10, r8 ; switch F 01A2 : 0010_0100_1010_0001_0000_0000 585: 586: mov r11, r0 ;################# 01A3 : 1100_0010_0000_0001_0110_0000 587: tmlp0: sub r0, c1, r0 ;# timing loop 01A4 : 1000_1010_0000_0110_0010_0000 588: jmp cc_geu, tmlp0 ;################# 01A5 : 0000_0100_0000_0000_0000_0000 589: nop 01A6 : 0000_0000_0000_0000_0000_0000 590: 591: jmpr cc_busy, 0 01A7 : 0000_0100_0011_0100_1111_0111 592: sgio r9, r8 ; switch F 01A8 : 0010_0100_1001_0001_0000_0000 593: 594: mov r12, r0 ;################# 01A9 : 1100_0010_0000_0001_1000_0000 595: tmlp1: sub r0, c1, r0 ;# Wait till FILCL 01AA : 1000_1010_0000_0110_0010_0000 596: jmp cc_geu, tmlp1 ;################# 01AB : 0000_0100_0000_0000_0000_0000 597: nop 01AC : 0000_0000_0000_0000_0000_0000 598: 599: iext FPA ;################# 01AD : 0101_0000_0000_0000_0000_0011 600: mov FPA, r14 ;# 01AE : 1100_0110_0000_1100_0000_1110 601: jmpr cc_busy, 0 ;# load FPA of cha 01AF : 0000_0100_0011_0101_1111_0111 602: lgio+ 0 ;# 01B0 : 1111_0100_0000_0000_0000_0000 603: jmpr cc_busy, 0 ;################# 01B1 : 0000_0100_0011_0110_0011_0111 604: lpio 0x300, r1 01B2 : 1110_0110_0110_0000_0000_0001 605: 606: mov 20, r3 ;################# 01B3 : 1100_0110_0000_0010_1000_0011 607: cclp: lgio+ 0 ;# 01B4 : 1111_0100_0000_0000_0000_0000 608: jmpr cc_busy, 0 ;# channel to chan 01B5 : 0000_0100_0011_0110_1011_0111 609: lpio 0x300, r2 ;# 01B6 : 1110_0110_0110_0000_0000_0010 610: ;# 611: cmp r2, r1 ;# do the com 01B7 : 1000_1000_0010_0000_0010_0000 612: jmp cc_eq, ccok ;# 01B8 : 0000_0100_0000_0000_0001_0001 613: add r6, c1, r6 ;# increase e 01B9 : 1000_0010_0110_0110_0010_0110 614: ;# 615: ccok: sub r3, c1, r3 ;# 01BA : 1000_1010_0011_0110_0010_0011 616: jmp cc_gtu, cclp ;################# 01BB : 0000_0100_0000_0000_0000_1000 617: 618: 619: add r13, r15, r5 ;################# 01BC : 1000_0010_1101_0001_1110_0101 620: jmpr cc_busy, 0 ;# store to DBANK 01BD : 0000_0100_0011_0111_1011_0111 621: sgio r1, r5 ;################# 01BE : 0010_0100_0001_0000_1010_0000 622: 623: add r13, c1, r13 ;################# 01BF : 1000_0010_1101_0110_0010_1101 624: cmp r13, 0x100 ;# loop ends after 01C0 : 1100_1000_1101_0001_0000_0000 625: jmp cc_ltu, dbkl ;################# 01C1 : 0000_0100_0000_0000_0001_0000 626: 627: nop 01C2 : 0000_0000_0000_0000_0000_0000 628: 629: 630: 631: ;################################# 632: ;# 633: ;# check limit value 634: ;# 635: ;# r1: received l 636: ;# r2: expected l 637: ;# 638: ;################################# 639: 640: 641: mov 255, r2 01C3 : 1100_0110_0001_1111_1110_0010 642: shl 13, r2, r2 01C4 : 1011_0010_1101_0000_0100_0010 643: shl 10, r2, r2 01C5 : 1011_0010_1010_0000_0100_0010 644: cmp r1, r2 01C6 : 1000_1000_0001_0000_0100_0000 645: jmp cc_eq, lvok 01C7 : 0000_0100_0000_0000_0001_0001 646: add r7, c1, r7 01C8 : 1000_0010_0111_0110_0010_0111 647: lvok: nop 01C9 : 0000_0000_0000_0000_0000_0000 648: 649: 650: 651: ;################################# 652: ;# 653: ;# cleanup after pedestal fil 654: ;# 655: ;################################# 656: 657: 658: clup: jmpr cc_busy, 0 01CA : 0000_0100_0011_1001_0101_0111 659: sgio r10, r8 ; switch F 01CB : 0010_0100_1010_0001_0000_0000 660: 661: jmpr cc_busy, 0 ; store ch 01CC : 0000_0100_0011_1001_1001_0111 662: sgio r6, CC_ERROR_ADR 01CD : 0010_1000_0110_1100_0001_0000 663: 664: jmpr cc_busy, 0 ; store li 01CE : 0000_0100_0011_1001_1101_0111 665: sgio r7, LV_ERROR_ADR 01CF : 0010_1000_0111_1100_0001_0001 666: 667: 668: 669: ;################################# 670: ;# 671: ;# increase counters (3/3) 672: ;# 673: ;################################# 674: 675: 676: mov 1024, r1 01D0 : 1100_0110_1000_0000_0000_0001 677: add r1, OFFSET_CTR, r0 01D1 : 1000_0010_0001_0111_1000_0000 678: jmpr cc_busy, 0 01D2 : 0000_0100_0011_1010_0101_0111 679: sgio r0, OFFSET_ADR 01D3 : 0010_1000_0000_1100_0000_0100 680: 681: 682: 683: ;################################# 684: ;# 685: ;# end current state, goto cl 686: ;# 687: ;################################# 688: 689: 690: 691: mov CMD_CLEAR, r0 01D4 : 1100_0110_1000_0010_0100_0000 692: jmpr cc_busy, 0 01D5 : 0000_0100_0011_1010_1011_0111 693: sgio r0, SMCMD 01D6 : 0010_1000_0000_1010_0000_0100 694: 695: 696: 697: ;################################# 698: ;# 699: ;# switch off own clock after 700: ;# 701: ;################################# 702: 703: 704: clkoff: mov 0, r0 01D7 : 1100_0110_0000_0000_0000_0000 705: jmpr cc_busy, 0 01D8 : 0000_0100_0011_1011_0001_0111 706: 707: #ifdef cpu0 708: sgio r0, CPU0SS 709: #endif 710: 711: #ifdef cpu1 712: sgio r0, CPU1SS 713: #endif 714: 715: #ifdef cpu2 716: sgio r0, CPU2SS 01D9 : 0010_1000_0000_1010_0010_0101 717: #endif 718: 719: #ifdef cpu3 720: sgio r0, CPU3SS 721: #endif 722: 723: jmp cc_uncond, clkoff 01DA : 0000_0100_0000_0000_0000_1111 724: nop 01DB : 0000_0000_0000_0000_0000_0000 725: 726: 727: 728: ;######################################### 729: ;# 730: ;# 0x0300: Interrrupt Raw Data Readou 731: ;# 732: ;# Nothing to be done here. 733: ;# 734: ;######################################### 735: 736: 737: org 0x300 738: 739: jmp cc_uncond, clkoff 0300 : 0000_0100_0000_0000_0000_1111 740: nop 0301 : 0000_0000_0000_0000_0000_0000 741: 742: 743: 744: 745: 746: 747: 748: 749: 750: 751: 752: 753: 754: 755: 756: 757: 758: 759: Source file read, 0 error(s), 0 warning(s).