Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.6, Dec 2007 SVN Revision 0, SVN Date 2007-12-27 Please send any comments to: angelov@kip.uni-heidelberg.de 18:34:35 / 21 Apr 2008 Source code file: SignalProcessing.asm Memory initialisation file: Log file: ../work/cpu3.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU3 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 107 ASM_SVN_REV = 0 1: ;################################################# 2: ;# 3: ;# Test Program for nonlinearity filter. 4: ;# 5: ;# Input data is taken from event buffer and 6: ;# another memory region. 7: ;# 8: ;# Marcus Gutfleisch 9: ;# Ruprecht-Karls-Universität Heidelberg, Kir 10: ;# 11: ;# Heidelberg, 18.03.2005 12: ;# 13: ;################################################# 14: 15: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: 31: #def CTGDINI=0x0B80; dddd dddd dddd dddd dddd dddd 32: #def CTGCTRL=0x0B81; ---- ---- ---- ---- ---S idce 33: #def CTGDOUT=0x0B82; DDDD DDDD DDDD DDDD DDDD DDDD 34: #def CTPDINI=0x0200; dddd dddd dddd dddd dddd dddd 35: #def CTPCTRL=0x0201; ---- ---- ---- ---- ---S idce 36: #def CTPDOUT=0x0202; DDDD DDDD DDDD DDDD DDDD DDDD 37: 38: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 39: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 40: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 41: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 42: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 43: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 44: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 45: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 46: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 47: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 48: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 49: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 50: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 51: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 52: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 53: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 54: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 55: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 56: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 57: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 58: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 59: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 60: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 61: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 62: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 63: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 64: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 65: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 66: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 67: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 68: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 69: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 70: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 71: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 72: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 73: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 74: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 75: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 76: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 77: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 78: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 79: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 80: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 81: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 82: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 83: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 84: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 85: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 86: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 87: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 88: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 89: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 90: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 91: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 92: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 93: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 94: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 95: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 96: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 97: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 98: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 99: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 100: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 101: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 102: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 103: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 104: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 105: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 106: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 107: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 108: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 109: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 110: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 111: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 112: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 113: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 114: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 115: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 116: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 117: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 118: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 119: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 120: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 121: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 122: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 123: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 124: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 125: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 126: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 127: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 128: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 129: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 130: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 131: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 132: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 133: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 134: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 135: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 136: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 137: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 138: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 139: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 140: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 141: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 142: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 143: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 144: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 145: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 146: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 147: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 148: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 149: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 150: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 151: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 152: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 153: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 154: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 155: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 156: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 157: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 158: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 159: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 160: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 161: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 162: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 163: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 164: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 165: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 166: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 167: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 168: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 169: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 170: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 171: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 172: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 173: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 174: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 175: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 176: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 177: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 178: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 179: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 180: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 181: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 182: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 183: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 184: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 185: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 186: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 187: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 188: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 189: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 190: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 191: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 192: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 193: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 194: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 195: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 196: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 197: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 198: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 199: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 200: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 201: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 202: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 203: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 204: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 205: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 206: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 207: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 208: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 209: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 210: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 211: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 212: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 213: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 214: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 215: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 216: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 217: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 218: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- 219: #def GBUSR0=0x0300; -- readonly 220: #def GBUSR1=0x0301; -- readonly *** End of include file /cad/tools/bin//conf_va.inc *** Include file ../../assembler.inc 1: ;#define MCM=1; 2: ;#define WAFER=1; 3: #define ROB=1; *** End of include file ../../assembler.inc 18: 19: 20: 21: ;######################################### 22: ;# 23: ;# defines 24: ;# 25: ;######################################### 26: 27: 28: #def EBSIM_FAST = g0 29: #def CPU_SYNC = g1 30: 31: 32: #def ERROR_CTR = c8 33: #def OFFSET_CTR = c12 34: #def LUT_CTR = c13 35: 36: #def OFFSET_ADR = 0xC04 37: #def LUT_ADR = 0xC05 38: 39: #ifdef cpu0 40: #def ERROR_ADR = 0xC00 41: #endif 42: #ifdef cpu1 43: #def ERROR_ADR = 0xC08 44: #endif 45: #ifdef cpu2 46: #def ERROR_ADR = 0xC10 47: #endif 48: #ifdef cpu3 49: #def ERROR_ADR = 0xC18 50: #endif 51: 52: 53: 54: ;######################################### 55: ;# 56: ;# 0x0000: Infinite Loop at Instructi 57: ;# 58: ;######################################### 59: 60: 61: org 0x0000 62: 63: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 64: nop 0001 : 0000_0000_0000_0000_0000_0000 65: 66: 67: 68: ;######################################### 69: ;# 70: ;# 0x0010: Interrrupt Clear Jump Addr 71: ;# 72: ;# CPU0: switch off all NI 73: ;# switch off NI cloc 74: ;# switch off preproc 75: ;# switch on filter 76: ;# 77: ;# CPU1: end clear state, a 78: ;# 79: ;# CPU2: get tracklet end s 80: ;# 81: ;# CPU3: get data end signa 82: ;# 83: ;######################################### 84: 85: 86: org 0x0010 87: 88: mov 0, r12 0010 : 1100_0110_0000_0000_0000_1100 89: mov 4, r13 0011 : 1100_0110_0000_0000_1000_1101 90: 91: #ifdef cpu0 92: 93: iext EBSIM 94: mov EBSIM, EBSIM_FAST 95: mov 0, CPU_SYNC 96: 97: iext b1111_0101_0000_0000_0010_0000 98: mov b1111_0101_0000_0000_0010_0000, r0 99: jmpr cc_busy, 0 100: sgio r0, SMOFFON 101: 102: mov CMD_EXT_CLR, r0 103: mov CMD_PRETRIGG, r1 104: mov 1054, r2 105: jmpr cc_busy, 0 106: cmp r2, OFFSET_CTR 107: jmp cc_leu, end_lp 108: sgio r0, SMCMD 109: 110: nop 111: nop 112: sgio r1, SMCMD 113: 114: #else 115: 116: #ifdef MCM 117: #ifdef cpu1 118: mov 0, r0 119: iext SEBDOU 120: sgio r0, SEBDOU 121: #else 122: nop 123: nop 124: nop 125: #endif 126: #endif 127: 128: nop 0012 : 0000_0000_0000_0000_0000_0000 129: nop 0013 : 0000_0000_0000_0000_0000_0000 130: nop 0014 : 0000_0000_0000_0000_0000_0000 131: nop 0015 : 0000_0000_0000_0000_0000_0000 132: 133: nop 0016 : 0000_0000_0000_0000_0000_0000 134: nop 0017 : 0000_0000_0000_0000_0000_0000 135: nop 0018 : 0000_0000_0000_0000_0000_0000 136: nop 0019 : 0000_0000_0000_0000_0000_0000 137: nop 001A : 0000_0000_0000_0000_0000_0000 138: 139: nop 001B : 0000_0000_0000_0000_0000_0000 140: nop 001C : 0000_0000_0000_0000_0000_0000 141: nop 001D : 0000_0000_0000_0000_0000_0000 142: 143: #endif 144: 145: end_cl: jmpr cc_uncond, 0 001E : 0000_0100_0000_0011_1100_1111 146: nop 001F : 0000_0000_0000_0000_0000_0000 147: 148: end_lp: 149: #ifdef MCM 150: mov 5, r0 151: iext SEBDEN 152: sgio r0, SEBDEN 153: jmpr cc_uncond, 0 154: #endif 155: 156: mov CMD_LP, r0 0020 : 1100_0110_0000_0010_0100_0000 157: sgio r0, SMCMD 0021 : 0010_1000_0000_1010_0000_0100 158: 159: jmpr cc_uncond, 0 0022 : 0000_0100_0000_0100_0100_1111 160: nop 0023 : 0000_0000_0000_0000_0000_0000 161: 162: 163: 164: ;######################################### 165: ;# 166: ;# 0x0100: Interrrupt Tracklet Proces 167: ;# 168: ;# send delayed tracklet end 169: ;# 170: ;######################################### 171: 172: 173: org 0x0100 174: 175: #ifdef cpu0 176: nop 177: nop 178: nop 179: nop 180: #endif 181: 182: #ifdef cpu1 183: nop 184: nop 185: nop 186: nop 187: #endif 188: 189: #ifdef cpu2 190: nop 191: nop 192: nop 193: nop 194: #endif 195: 196: #ifdef cpu3 197: mov 1, r0 0100 : 1100_0110_0000_0000_0010_0000 198: jmpr cc_busy, 0 0101 : 0000_0100_0010_0000_0011_0111 199: sgio r0, EBSIM_FAST 0102 : 0010_0100_0000_0010_0000_0000 200: nop 0103 : 0000_0000_0000_0000_0000_0000 201: #endif 202: 203: 204: 205: ;################################# 206: ;# 207: ;# check result 208: ;# 209: ;################################# 210: 211: 212: mov EBR0, r8 ; load cha 0104 : 1100_0111_0000_0000_0000_1000 213: add r8, c1, r8 ; add +1 d 0105 : 1000_0010_1000_0110_0010_1000 214: mov EBR1, r9 0106 : 1100_0111_0000_1000_0000_1001 215: add r9, c1, r9 0107 : 1000_0010_1001_0110_0010_1001 216: mov EBR2, r10 0108 : 1100_0111_0001_0000_0000_1010 217: add r10, c1, r10 0109 : 1000_0010_1010_0110_0010_1010 218: mov EBR3, r11 010A : 1100_0111_0001_1000_0000_1011 219: add r11, c1, r11 010B : 1000_0010_1011_0110_0010_1011 220: mov EBR4, r12 010C : 1100_0111_0010_0000_0000_1100 221: add r12, c1, r12 010D : 1000_0010_1100_0110_0010_1100 222: mov EBR5, r13 010E : 1100_0111_0010_1000_0000_1101 223: add r13, c1, r13 010F : 1000_0010_1101_0110_0010_1101 224: 225: mov 0, r0 ; r0: time 0110 : 1100_0110_0000_0000_0000_0000 226: 227: shl -2, LUT_CTR, r1 ; r1: curr 0111 : 1011_0011_1110_0111_1010_0001 228: mov 3, r2 0112 : 1100_0110_0000_0000_0110_0010 229: and r2, LUT_CTR, r2 ; r2: curr 0113 : 1010_0110_0010_0111_1010_0010 230: 231: loopTT: mov 0, r6 ; r6: erro 0114 : 1100_0110_0000_0000_0000_0110 232: 233: add r0, OFFSET_CTR, r3 0115 : 1000_0010_0000_0111_1000_0011 234: cmp r3, 1023 0116 : 1100_1000_0011_0011_1111_1111 235: jmp cc_leu, TTval 0117 : 0000_0100_0000_0000_0001_1000 236: mov 1024, r4 0118 : 1100_0110_1000_0000_0000_0100 237: sub r3, r4, r3 0119 : 1000_1010_0011_0000_1000_0011 238: 239: TTval: shl 2, r3, r3 011A : 1011_0010_0010_0000_0110_0011 240: add r3, r1, r3 011B : 1000_0010_0011_0000_0010_0011 241: add r3, r2, r3 011C : 1000_0010_0011_0000_0100_0011 242: shl -2, r3, r3 011D : 1011_0011_1110_0000_0110_0011 243: cmp r3, 1023 011E : 1100_1000_0011_0011_1111_1111 244: jmp cc_leu, TTc0 011F : 0000_0100_0000_0000_0001_1000 245: mov 1023, r3 ; r3: expe 0120 : 1100_0110_0111_1111_1110_0011 246: 247: TTc0: add r0, r8, r4 ; r4: even 0121 : 1000_0010_0000_0001_0000_0100 248: lpio r4, r5 0122 : 1110_0010_0000_0000_1000_0101 249: lpio r4, r5 ; r5: filt 0123 : 1110_0010_0000_0000_1000_0101 250: 251: cmp r3, r5 0124 : 1000_1000_0011_0000_1010_0000 252: jmp cc_eq, TTc1 0125 : 0000_0100_0000_0000_0001_0001 253: add r6, c1, r6 0126 : 1000_0010_0110_0110_0010_0110 254: 255: TTc1: add r0, r9, r4 ; r4: even 0127 : 1000_0010_0000_0001_0010_0100 256: lpio r4, r5 0128 : 1110_0010_0000_0000_1000_0101 257: lpio r4, r5 ; r5: filt 0129 : 1110_0010_0000_0000_1000_0101 258: 259: cmp r3, r5 012A : 1000_1000_0011_0000_1010_0000 260: jmp cc_eq, TTc2 012B : 0000_0100_0000_0000_0001_0001 261: add r6, c1, r6 012C : 1000_0010_0110_0110_0010_0110 262: 263: TTc2: add r0, r10, r4 ; r4: even 012D : 1000_0010_0000_0001_0100_0100 264: lpio r4, r5 012E : 1110_0010_0000_0000_1000_0101 265: lpio r4, r5 ; r5: filt 012F : 1110_0010_0000_0000_1000_0101 266: 267: cmp r3, r5 0130 : 1000_1000_0011_0000_1010_0000 268: jmp cc_eq, TTc3 0131 : 0000_0100_0000_0000_0001_0001 269: add r6, c1, r6 0132 : 1000_0010_0110_0110_0010_0110 270: 271: TTc3: add r0, r11, r4 ; r4: even 0133 : 1000_0010_0000_0001_0110_0100 272: lpio r4, r5 0134 : 1110_0010_0000_0000_1000_0101 273: lpio r4, r5 ; r5: filt 0135 : 1110_0010_0000_0000_1000_0101 274: 275: cmp r3, r5 0136 : 1000_1000_0011_0000_1010_0000 276: jmp cc_eq, TTc4 0137 : 0000_0100_0000_0000_0001_0001 277: add r6, c1, r6 0138 : 1000_0010_0110_0110_0010_0110 278: 279: TTc4: add r0, r12, r4 ; r4: even 0139 : 1000_0010_0000_0001_1000_0100 280: lpio r4, r5 013A : 1110_0010_0000_0000_1000_0101 281: lpio r4, r5 ; r5: filt 013B : 1110_0010_0000_0000_1000_0101 282: 283: cmp r3, r5 013C : 1000_1000_0011_0000_1010_0000 284: jmp cc_eq, TTc5 013D : 0000_0100_0000_0000_0001_0001 285: add r6, c1, r6 013E : 1000_0010_0110_0110_0010_0110 286: 287: #ifdef cpu3 288: TTc5: add r0, r13, r4 ; r4: even 013F : 1000_0010_0000_0001_1010_0100 289: lpio r4, r5 0140 : 1110_0010_0000_0000_1000_0101 290: lpio r4, r5 ; r5: filt 0141 : 1110_0010_0000_0000_1000_0101 291: 292: cmp r3, r5 0142 : 1000_1000_0011_0000_1010_0000 293: jmp cc_eq, TTend 0143 : 0000_0100_0000_0000_0001_0001 294: add r6, c1, r6 0144 : 1000_0010_0110_0110_0010_0110 295: #else 296: nop 297: nop 298: nop 299: 300: nop 301: nop 302: TTc5: nop 303: #endif 304: 305: TTend: add r6, ERROR_CTR, r6 0145 : 1000_0010_0110_0111_0000_0110 306: jmpr cc_busy, 0 0146 : 0000_0100_0010_1000_1101_0111 307: sgio r6, ERROR_ADR 0147 : 0010_1000_0110_1100_0001_1000 308: 309: add r0, c1, r0 0148 : 1000_0010_0000_0110_0010_0000 310: cmp r0, 31 0149 : 1100_1000_0000_0000_0001_1111 311: jmp cc_ltu, loopTT 014A : 0000_0100_0000_0000_0001_0000 312: nop 014B : 0000_0000_0000_0000_0000_0000 313: 314: 315: 316: 317: ;################################# 318: ;# 319: ;# increase counters 320: ;# 321: ;################################# 322: 323: 324: #ifdef cpu3 325: 326: mov 1, r1 014C : 1100_0110_0000_0000_0010_0001 327: add r1, LUT_CTR, r0 014D : 1000_0010_0001_0111_1010_0000 328: cmp r0, 256 014E : 1100_1000_0000_0001_0000_0000 329: jmp cc_ltu, ct_LUT 014F : 0000_0100_0000_0000_0001_0000 330: 331: mov 0, r0 0150 : 1100_0110_0000_0000_0000_0000 332: mov 31, r1 0151 : 1100_0110_0000_0011_1110_0001 333: add r1, OFFSET_CTR, r1 0152 : 1000_0010_0001_0111_1000_0001 334: 335: jmpr cc_busy, 0 0153 : 0000_0100_0010_1010_0111_0111 336: sgio r1, OFFSET_ADR 0154 : 0010_1000_0001_1100_0000_0100 337: 338: ct_LUT: jmpr cc_busy, 0 0155 : 0000_0100_0010_1010_1011_0111 339: sgio r0, LUT_ADR 0156 : 0010_1000_0000_1100_0000_0101 340: 341: #else 342: 343: nop 344: nop 345: nop 346: nop 347: 348: nop 349: nop 350: nop 351: 352: nop 353: nop 354: 355: nop 356: nop 357: 358: #endif 359: 360: jmpr cc_busy, 0 0157 : 0000_0100_0010_1010_1111_0111 361: 362: 363: 364: ;################################# 365: ;# 366: ;# write next LUT test entrie 367: ;# 368: ;################################# 369: 370: 371: iext FLL 0158 : 0101_0000_0000_0000_0000_0011 372: mov FLL, r0 0159 : 1100_0110_0010_0000_0000_0000 373: mov 0, r1 015A : 1100_0110_0000_0000_0000_0001 374: shl -2, LUT_CTR, r12 ; r12: nex 015B : 1011_0011_1110_0111_1010_1100 375: mov 3, r13 015C : 1100_0110_0000_0000_0110_1101 376: and r13, LUT_CTR, r13 ; r13: nex 015D : 1010_0110_1101_0111_1010_1101 377: 378: loopLT: add r0, r1, r2 015E : 1000_0010_0000_0000_0010_0010 379: jmpr cc_busy, 0 015F : 0000_0100_0010_1011_1111_0111 380: sgio r12, r2 0160 : 0010_0100_1100_0000_0100_0000 381: 382: add r1, c1, r1 0161 : 1000_0010_0001_0110_0010_0001 383: cmp r1, 64 0162 : 1100_1000_0001_0000_0100_0000 384: jmp cc_ltu, loopLT 0163 : 0000_0100_0000_0000_0001_0000 385: 386: iext FPNP 0164 : 0101_0000_0000_0000_0000_0011 387: mov FPNP, r0 0165 : 1100_0110_0000_0100_0010_0000 388: 389: jmpr cc_busy, 0 0166 : 0000_0100_0010_1100_1101_0111 390: sgio r13, r0 0167 : 0010_0100_1101_0000_0000_0000 391: 392: 393: 394: ;################################# 395: ;# 396: ;# write next test pattern in 397: ;# 398: ;################################# 399: 400: 401: #ifdef cpu3 402: 403: mov 0, r0 0168 : 1100_0110_0000_0000_0000_0000 404: cmp r0, LUT_CTR 0169 : 1000_1000_0000_0111_1010_0000 405: jmp cc_neq, endEB 016A : 0000_0100_0000_0000_0000_0001 406: 407: iext EBW 016B : 0101_0000_0000_0000_0000_0010 408: mov EBW, r0 016C : 1100_0110_0000_0000_0000_0000 409: mov 32, r1 016D : 1100_0110_0000_0100_0000_0001 410: add r0, r1, r0 ; r0: even 016E : 1000_0010_0000_0000_0010_0000 411: 412: mov 0, r1 ; r1: chan 016F : 1100_0110_0000_0000_0000_0001 413: mov 0, r2 ; r2: time 0170 : 1100_0110_0000_0000_0000_0010 414: 415: loopEB: 416: add r2, OFFSET_CTR, r4 0171 : 1000_0010_0010_0111_1000_0100 417: shl 7, r1, r3 0172 : 1011_0010_0111_0000_0010_0011 418: add r0, r3, r3 0173 : 1000_0010_0000_0000_0110_0011 419: add r2, r3, r3 0174 : 1000_0010_0010_0000_0110_0011 420: 421: jmpr cc_busy, 0 ; r3: sing 0175 : 0000_0100_0010_1110_1011_0111 422: sgio r4, r3 ; r4: data 0176 : 0010_0100_0100_0000_0110_0000 423: 424: mov 10, r5 0177 : 1100_0110_0000_0001_0100_0101 425: 426: waitD: sub r5, c1, r5 0178 : 1000_1010_0101_0110_0010_0101 427: jmp cc_gts, waitD 0179 : 0000_0100_0000_0000_0000_1001 428: 429: add r1, c1, r1 017A : 1000_0010_0001_0110_0010_0001 430: cmp r1, 21 017B : 1100_1000_0001_0000_0001_0101 431: jmp cc_ltu, loopEB 017C : 0000_0100_0000_0000_0001_0000 432: 433: mov 0, r1 017D : 1100_0110_0000_0000_0000_0001 434: add r2, c1, r2 017E : 1000_0010_0010_0110_0010_0010 435: cmp r2, 32 017F : 1100_1000_0010_0000_0010_0000 436: jmp cc_ltu, loopEB 0180 : 0000_0100_0000_0000_0001_0000 437: nop 0181 : 0000_0000_0000_0000_0000_0000 438: endEB: mov 1, CPU_SYNC 0182 : 1100_0110_0000_0000_0011_0001 439: 440: #else 441: 442: nop 443: 444: #endif 445: 446: 447: 448: ;################################# 449: ;# 450: ;# wait for data writing comp 451: ;# 452: ;################################# 453: 454: 455: wsy: mov CPU_SYNC, r0 0183 : 1100_0010_0000_0010_0010_0000 456: cmp r0, 1 0184 : 1100_1000_0000_0000_0000_0001 457: jmp cc_neq, wsy 0185 : 0000_0100_0000_0000_0000_0001 458: 459: 460: ;################################# 461: ;# 462: ;# copy lower indicator words 463: ;# 464: ;################################# 465: 466: 467: #ifdef cpu0 468: mov 0x7B8, r15 469: #endif 470: 471: #ifdef cpu1 472: mov 0x7CC, r15 473: #endif 474: 475: #ifdef cpu2 476: mov 0x7E0, r15 477: #endif 478: 479: #ifdef cpu3 480: mov 0x7F4, r15 0186 : 1100_0110_1111_1110_1000_1111 481: #endif 482: 483: lpio EBI0, r0 0187 : 1110_0111_0011_0000_0000_0000 484: lpio EBI0, r0 0188 : 1110_0111_0011_0000_0000_0000 485: sra+ r0 0189 : 0011_1000_0000_0000_0000_0000 486: 487: lpio EBI2, r0 018A : 1110_0111_0011_0000_0100_0000 488: lpio EBI2, r0 018B : 1110_0111_0011_0000_0100_0000 489: sra+ r0 018C : 0011_1000_0000_0000_0000_0000 490: 491: lpio EBI4, r0 018D : 1110_0111_0011_0000_1000_0000 492: lpio EBI4, r0 018E : 1110_0111_0011_0000_1000_0000 493: sra+ r0 018F : 0011_1000_0000_0000_0000_0000 494: 495: lpio EBI6, r0 0190 : 1110_0111_0011_0000_1100_0000 496: lpio EBI6, r0 0191 : 1110_0111_0011_0000_1100_0000 497: sra+ r0 0192 : 0011_1000_0000_0000_0000_0000 498: 499: lpio EBI8, r0 0193 : 1110_0111_0011_0001_0000_0000 500: lpio EBI8, r0 0194 : 1110_0111_0011_0001_0000_0000 501: sra+ r0 0195 : 0011_1000_0000_0000_0000_0000 502: 503: #ifdef cpu3 504: lpio EBIA, r0 0196 : 1110_0111_0011_0001_0100_0000 505: lpio EBIA, r0 0197 : 1110_0111_0011_0001_0100_0000 506: sra+ r0 0198 : 0011_1000_0000_0000_0000_0000 507: #else 508: nop 509: nop 510: nop 511: #endif 512: 513: 514: ;################################# 515: ;# 516: ;# DMEM address to copy event 517: ;# beware: byte address = 4 * 518: ;# 519: ;################################# 520: 521: #ifdef cpu0 522: mov 0x080, r15 523: #endif 524: 525: #ifdef cpu1 526: mov 0x238, r15 527: #endif 528: 529: #ifdef cpu2 530: mov 0x3F0, r15 531: #endif 532: 533: #ifdef cpu3 534: mov 0x5A8, r15 0199 : 1100_0110_1011_0101_0000_1111 535: #endif 536: 537: ;################################# 538: ;# 539: ;# channel check bits, absolu 540: ;# 541: ;################################# 542: 543: #ifdef cpu0 544: mov 3, r3 545: #endif 546: 547: #ifdef cpu1 548: mov 2, r3 549: #endif 550: 551: #ifdef cpu2 552: mov 3, r3 553: #endif 554: 555: #ifdef cpu3 556: mov 2, r3 019A : 1100_0110_0000_0000_0100_0011 557: #endif 558: 559: ;################################# 560: ;# 561: ;# copy event buffer data of 562: ;# 563: ;################################# 564: 565: mov EBR0, r14 019B : 1100_0111_0000_0000_0000_1110 566: mov 66, r5 019C : 1100_0110_0000_1000_0100_0101 567: 568: loop0: lpio+ r0 019D : 1110_1110_0000_0000_0000_0000 569: lpio+ r0 019E : 1110_1110_0000_0000_0000_0000 570: lpio+ r1 019F : 1110_1110_0000_0000_0000_0001 571: lpio r14, r2 01A0 : 1110_0010_0000_0001_1100_0010 572: 573: shl 10, r2, r2 01A1 : 1011_0010_1010_0000_0100_0010 574: or r1, r2, r2 01A2 : 1010_1010_0001_0000_0100_0010 575: shl 10, r2, r2 01A3 : 1011_0010_1010_0000_0100_0010 576: or r0, r2, r2 01A4 : 1010_1010_0000_0000_0100_0010 577: shl 2, r2, r2 01A5 : 1011_0010_0010_0000_0100_0010 578: or r3, r2, r2 01A6 : 1010_1010_0011_0000_0100_0010 579: 580: sra+ r2 01A7 : 0011_1000_0010_0000_0000_0000 581: 582: sub r5, c3, r5 01A8 : 1000_1010_0101_0110_0110_0101 583: jmp cc_gtu, loop0 01A9 : 0000_0100_0000_0000_0000_1000 584: 585: ;################################# 586: ;# 587: ;# copy event buffer data of 588: ;# 589: ;################################# 590: 591: mov EBR1, r14 01AA : 1100_0111_0000_1000_0000_1110 592: mov 66, r5 01AB : 1100_0110_0000_1000_0100_0101 593: xor r3, c1, r3 01AC : 1010_0010_0011_0110_0010_0011 594: 595: loop1: lpio+ r0 01AD : 1110_1110_0000_0000_0000_0000 596: lpio+ r0 01AE : 1110_1110_0000_0000_0000_0000 597: lpio+ r1 01AF : 1110_1110_0000_0000_0000_0001 598: lpio r14, r2 01B0 : 1110_0010_0000_0001_1100_0010 599: 600: shl 10, r2, r2 01B1 : 1011_0010_1010_0000_0100_0010 601: or r1, r2, r2 01B2 : 1010_1010_0001_0000_0100_0010 602: shl 10, r2, r2 01B3 : 1011_0010_1010_0000_0100_0010 603: or r0, r2, r2 01B4 : 1010_1010_0000_0000_0100_0010 604: shl 2, r2, r2 01B5 : 1011_0010_0010_0000_0100_0010 605: or r3, r2, r2 01B6 : 1010_1010_0011_0000_0100_0010 606: 607: sra+ r2 01B7 : 0011_1000_0010_0000_0000_0000 608: 609: sub r5, c3, r5 01B8 : 1000_1010_0101_0110_0110_0101 610: jmp cc_gtu, loop1 01B9 : 0000_0100_0000_0000_0000_1000 611: 612: ;################################# 613: ;# 614: ;# copy event buffer data of 615: ;# 616: ;################################# 617: 618: mov EBR2, r14 01BA : 1100_0111_0001_0000_0000_1110 619: mov 66, r5 01BB : 1100_0110_0000_1000_0100_0101 620: xor r3, c1, r3 01BC : 1010_0010_0011_0110_0010_0011 621: 622: loop2: lpio+ r0 01BD : 1110_1110_0000_0000_0000_0000 623: lpio+ r0 01BE : 1110_1110_0000_0000_0000_0000 624: lpio+ r1 01BF : 1110_1110_0000_0000_0000_0001 625: lpio r14, r2 01C0 : 1110_0010_0000_0001_1100_0010 626: 627: shl 10, r2, r2 01C1 : 1011_0010_1010_0000_0100_0010 628: or r1, r2, r2 01C2 : 1010_1010_0001_0000_0100_0010 629: shl 10, r2, r2 01C3 : 1011_0010_1010_0000_0100_0010 630: or r0, r2, r2 01C4 : 1010_1010_0000_0000_0100_0010 631: shl 2, r2, r2 01C5 : 1011_0010_0010_0000_0100_0010 632: or r3, r2, r2 01C6 : 1010_1010_0011_0000_0100_0010 633: 634: sra+ r2 01C7 : 0011_1000_0010_0000_0000_0000 635: 636: sub r5, c3, r5 01C8 : 1000_1010_0101_0110_0110_0101 637: jmp cc_gtu, loop2 01C9 : 0000_0100_0000_0000_0000_1000 638: 639: ;################################# 640: ;# 641: ;# copy event buffer data of 642: ;# 643: ;################################# 644: 645: mov EBR3, r14 01CA : 1100_0111_0001_1000_0000_1110 646: mov 66, r5 01CB : 1100_0110_0000_1000_0100_0101 647: xor r3, c1, r3 01CC : 1010_0010_0011_0110_0010_0011 648: 649: loop3: lpio+ r0 01CD : 1110_1110_0000_0000_0000_0000 650: lpio+ r0 01CE : 1110_1110_0000_0000_0000_0000 651: lpio+ r1 01CF : 1110_1110_0000_0000_0000_0001 652: lpio r14, r2 01D0 : 1110_0010_0000_0001_1100_0010 653: 654: shl 10, r2, r2 01D1 : 1011_0010_1010_0000_0100_0010 655: or r1, r2, r2 01D2 : 1010_1010_0001_0000_0100_0010 656: shl 10, r2, r2 01D3 : 1011_0010_1010_0000_0100_0010 657: or r0, r2, r2 01D4 : 1010_1010_0000_0000_0100_0010 658: shl 2, r2, r2 01D5 : 1011_0010_0010_0000_0100_0010 659: or r3, r2, r2 01D6 : 1010_1010_0011_0000_0100_0010 660: 661: sra+ r2 01D7 : 0011_1000_0010_0000_0000_0000 662: 663: sub r5, c3, r5 01D8 : 1000_1010_0101_0110_0110_0101 664: jmp cc_gtu, loop3 01D9 : 0000_0100_0000_0000_0000_1000 665: 666: ;################################# 667: ;# 668: ;# copy event buffer data of 669: ;# 670: ;################################# 671: 672: mov EBR4, r14 01DA : 1100_0111_0010_0000_0000_1110 673: mov 66, r5 01DB : 1100_0110_0000_1000_0100_0101 674: xor r3, c1, r3 01DC : 1010_0010_0011_0110_0010_0011 675: 676: loop4: lpio+ r0 01DD : 1110_1110_0000_0000_0000_0000 677: lpio+ r0 01DE : 1110_1110_0000_0000_0000_0000 678: lpio+ r1 01DF : 1110_1110_0000_0000_0000_0001 679: lpio r14, r2 01E0 : 1110_0010_0000_0001_1100_0010 680: 681: shl 10, r2, r2 01E1 : 1011_0010_1010_0000_0100_0010 682: or r1, r2, r2 01E2 : 1010_1010_0001_0000_0100_0010 683: shl 10, r2, r2 01E3 : 1011_0010_1010_0000_0100_0010 684: or r0, r2, r2 01E4 : 1010_1010_0000_0000_0100_0010 685: shl 2, r2, r2 01E5 : 1011_0010_0010_0000_0100_0010 686: or r3, r2, r2 01E6 : 1010_1010_0011_0000_0100_0010 687: 688: sra+ r2 01E7 : 0011_1000_0010_0000_0000_0000 689: 690: sub r5, c3, r5 01E8 : 1000_1010_0101_0110_0110_0101 691: jmp cc_gtu, loop4 01E9 : 0000_0100_0000_0000_0000_1000 692: 693: ;################################# 694: ;# 695: ;# copy event buffer data of 696: ;# 697: ;################################# 698: 699: #ifdef cpu3 700: mov EBR5, r14 01EA : 1100_0111_0010_1000_0000_1110 701: mov 66, r5 01EB : 1100_0110_0000_1000_0100_0101 702: xor r3, c1, r3 01EC : 1010_0010_0011_0110_0010_0011 703: 704: loop5: lpio+ r0 01ED : 1110_1110_0000_0000_0000_0000 705: lpio+ r0 01EE : 1110_1110_0000_0000_0000_0000 706: lpio+ r1 01EF : 1110_1110_0000_0000_0000_0001 707: lpio r14, r2 01F0 : 1110_0010_0000_0001_1100_0010 708: 709: shl 10, r2, r2 01F1 : 1011_0010_1010_0000_0100_0010 710: or r1, r2, r2 01F2 : 1010_1010_0001_0000_0100_0010 711: shl 10, r2, r2 01F3 : 1011_0010_1010_0000_0100_0010 712: or r0, r2, r2 01F4 : 1010_1010_0000_0000_0100_0010 713: shl 2, r2, r2 01F5 : 1011_0010_0010_0000_0100_0010 714: or r3, r2, r2 01F6 : 1010_1010_0011_0000_0100_0010 715: 716: sra+ r2 01F7 : 0011_1000_0010_0000_0000_0000 717: 718: sub r5, c3, r5 01F8 : 1000_1010_0101_0110_0110_0101 719: jmp cc_gtu, loop5 01F9 : 0000_0100_0000_0000_0000_1000 720: #else 721: nop 722: nop 723: nop 724: nop 725: nop 726: nop 727: nop 728: nop 729: nop 730: nop 731: nop 732: nop 733: nop 734: nop 735: nop 736: nop 737: #endif 738: 739: 740: ;################################# 741: ;# 742: ;# end current state, goto cl 743: ;# 744: ;################################# 745: 746: 747: #ifdef cpu3 748: 749: mov 0, r0 01FA : 1100_0110_0000_0000_0000_0000 750: jmpr cc_busy, 0 01FB : 0000_0100_0011_1111_0111_0111 751: sgio r0, EBSIM_FAST 01FC : 0010_0100_0000_0010_0000_0000 752: 753: mov CMD_CLEAR, r0 01FD : 1100_0110_1000_0010_0100_0000 754: jmpr cc_busy, 0 01FE : 0000_0100_0011_1111_1101_0111 755: sgio r0, SMCMD 01FF : 0010_1000_0000_1010_0000_0100 756: 757: #else 758: 759: nop 760: nop 761: nop 762: 763: nop 764: nop 765: nop 766: 767: #endif 768: 769: 770: 771: ;################################# 772: ;# 773: ;# switch off own clock after 774: ;# 775: ;################################# 776: 777: 778: clkoff: mov 0, r0 0200 : 1100_0110_0000_0000_0000_0000 779: jmpr cc_busy, 0 0201 : 0000_0100_0100_0000_0011_0111 780: 781: #ifdef cpu0 782: sgio r0, CPU0SS 783: #endif 784: 785: #ifdef cpu1 786: sgio r0, CPU1SS 787: #endif 788: 789: #ifdef cpu2 790: sgio r0, CPU2SS 791: #endif 792: 793: #ifdef cpu3 794: sgio r0, CPU3SS 0202 : 0010_1000_0000_1010_0010_0111 795: #endif 796: 797: jmp cc_uncond, clkoff 0203 : 0000_0100_0000_0000_0000_1111 798: nop 0204 : 0000_0000_0000_0000_0000_0000 799: 800: 801: 802: ;######################################### 803: ;# 804: ;# 0x0300: Interrrupt Raw Data Readou 805: ;# 806: ;# Nothing to be done here. 807: ;# 808: ;######################################### 809: 810: 811: org 0x300 812: 813: jmp cc_uncond, clkoff 0300 : 0000_0100_0000_0000_0000_1111 814: nop 0301 : 0000_0000_0000_0000_0000_0000 815: 816: 817: 818: 819: 820: 821: 822: 823: 824: 825: 826: 827: 828: 829: 830: 831: 832: 833: Source file read, 0 error(s), 0 warning(s).