Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.6, Dec 2007 SVN Revision 0, SVN Date 2007-12-27 Please send any comments to: angelov@kip.uni-heidelberg.de 18:34:34 / 21 Apr 2008 Source code file: SignalProcessing.asm Memory initialisation file: Log file: ../work/cpu0.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU0 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 107 ASM_SVN_REV = 0 1: ;################################################# 2: ;# 3: ;# Test Program for nonlinearity filter. 4: ;# 5: ;# Input data is taken from event buffer and 6: ;# another memory region. 7: ;# 8: ;# Marcus Gutfleisch 9: ;# Ruprecht-Karls-Universität Heidelberg, Kir 10: ;# 11: ;# Heidelberg, 18.03.2005 12: ;# 13: ;################################################# 14: 15: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: 31: #def CTGDINI=0x0B80; dddd dddd dddd dddd dddd dddd 32: #def CTGCTRL=0x0B81; ---- ---- ---- ---- ---S idce 33: #def CTGDOUT=0x0B82; DDDD DDDD DDDD DDDD DDDD DDDD 34: #def CTPDINI=0x0200; dddd dddd dddd dddd dddd dddd 35: #def CTPCTRL=0x0201; ---- ---- ---- ---- ---S idce 36: #def CTPDOUT=0x0202; DDDD DDDD DDDD DDDD DDDD DDDD 37: 38: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 39: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 40: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 41: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 42: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 43: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 44: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 45: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 46: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 47: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 48: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 49: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 50: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 51: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 52: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 53: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 54: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 55: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 56: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 57: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 58: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 59: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 60: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 61: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 62: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 63: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 64: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 65: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 66: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 67: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 68: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 69: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 70: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 71: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 72: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 73: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 74: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 75: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 76: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 77: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 78: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 79: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 80: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 81: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 82: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 83: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 84: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 85: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 86: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 87: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 88: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 89: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 90: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 91: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 92: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 93: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 94: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 95: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 96: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 97: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 98: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 99: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 100: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 101: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 102: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 103: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 104: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 105: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 106: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 107: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 108: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 109: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 110: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 111: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 112: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 113: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 114: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 115: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 116: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 117: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 118: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 119: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 120: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 121: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 122: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 123: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 124: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 125: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 126: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 127: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 128: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 129: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 130: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 131: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 132: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 133: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 134: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 135: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 136: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 137: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 138: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 139: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 140: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 141: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 142: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 143: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 144: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 145: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 146: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 147: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 148: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 149: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 150: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 151: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 152: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 153: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 154: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 155: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 156: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 157: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 158: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 159: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 160: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 161: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 162: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 163: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 164: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 165: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 166: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 167: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 168: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 169: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 170: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 171: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 172: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 173: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 174: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 175: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 176: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 177: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 178: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 179: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 180: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 181: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 182: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 183: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 184: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 185: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 186: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 187: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 188: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 189: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 190: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 191: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 192: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 193: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 194: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 195: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 196: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 197: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 198: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 199: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 200: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 201: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 202: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 203: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 204: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 205: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 206: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 207: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 208: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 209: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 210: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 211: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 212: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 213: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 214: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 215: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 216: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 217: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 218: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- 219: #def GBUSR0=0x0300; -- readonly 220: #def GBUSR1=0x0301; -- readonly *** End of include file /cad/tools/bin//conf_va.inc *** Include file ../../assembler.inc 1: ;#define MCM=1; 2: ;#define WAFER=1; 3: #define ROB=1; *** End of include file ../../assembler.inc 18: 19: 20: 21: ;######################################### 22: ;# 23: ;# defines 24: ;# 25: ;######################################### 26: 27: 28: #def EBSIM_FAST = g0 29: #def CPU_SYNC = g1 30: 31: 32: #def ERROR_CTR = c8 33: #def OFFSET_CTR = c12 34: #def LUT_CTR = c13 35: 36: #def OFFSET_ADR = 0xC04 37: #def LUT_ADR = 0xC05 38: 39: #ifdef cpu0 40: #def ERROR_ADR = 0xC00 41: #endif 42: #ifdef cpu1 43: #def ERROR_ADR = 0xC08 44: #endif 45: #ifdef cpu2 46: #def ERROR_ADR = 0xC10 47: #endif 48: #ifdef cpu3 49: #def ERROR_ADR = 0xC18 50: #endif 51: 52: 53: 54: ;######################################### 55: ;# 56: ;# 0x0000: Infinite Loop at Instructi 57: ;# 58: ;######################################### 59: 60: 61: org 0x0000 62: 63: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 64: nop 0001 : 0000_0000_0000_0000_0000_0000 65: 66: 67: 68: ;######################################### 69: ;# 70: ;# 0x0010: Interrrupt Clear Jump Addr 71: ;# 72: ;# CPU0: switch off all NI 73: ;# switch off NI cloc 74: ;# switch off preproc 75: ;# switch on filter 76: ;# 77: ;# CPU1: end clear state, a 78: ;# 79: ;# CPU2: get tracklet end s 80: ;# 81: ;# CPU3: get data end signa 82: ;# 83: ;######################################### 84: 85: 86: org 0x0010 87: 88: mov 0, r12 0010 : 1100_0110_0000_0000_0000_1100 89: mov 4, r13 0011 : 1100_0110_0000_0000_1000_1101 90: 91: #ifdef cpu0 92: 93: iext EBSIM 0012 : 0101_0000_0000_0000_0000_0011 94: mov EBSIM, EBSIM_FAST 0013 : 1100_0110_0000_0001_1011_0000 95: mov 0, CPU_SYNC 0014 : 1100_0110_0000_0000_0001_0001 96: 97: iext b1111_0101_0000_0000_0010_0000 0015 : 0101_0000_0000_1111_0101_0000 98: mov b1111_0101_0000_0000_0010_0000, r0 0016 : 1100_0110_0000_0100_0000_0000 99: jmpr cc_busy, 0 0017 : 0000_0100_0000_0010_1111_0111 100: sgio r0, SMOFFON 0018 : 0010_1000_0000_1010_0000_0101 101: 102: mov CMD_EXT_CLR, r0 0019 : 1100_0110_0110_0010_0100_0000 103: mov CMD_PRETRIGG, r1 001A : 1100_0110_1010_0010_0100_0001 104: mov 1023, r2 001B : 1100_0110_0111_1111_1110_0010 105: jmpr cc_busy, 0 001C : 0000_0100_0000_0011_1001_0111 106: cmp r2, OFFSET_CTR 001D : 1000_1000_0010_0111_1000_0000 107: jmp cc_leu, end_lp 001E : 0000_0100_0000_0000_0001_1000 108: sgio r0, SMCMD 001F : 0010_1000_0000_1010_0000_0100 109: 110: nop 0020 : 0000_0000_0000_0000_0000_0000 111: nop 0021 : 0000_0000_0000_0000_0000_0000 112: sgio r1, SMCMD 0022 : 0010_1000_0001_1010_0000_0100 113: 114: #else 115: 116: #ifdef MCM 117: #ifdef cpu1 118: mov 0, r0 119: iext SEBDOU 120: sgio r0, SEBDOU 121: #else 122: nop 123: nop 124: nop 125: #endif 126: #endif 127: 128: nop 129: nop 130: nop 131: nop 132: 133: nop 134: nop 135: nop 136: nop 137: nop 138: 139: nop 140: nop 141: nop 142: 143: #endif 144: 145: end_cl: jmpr cc_uncond, 0 0023 : 0000_0100_0000_0100_0110_1111 146: nop 0024 : 0000_0000_0000_0000_0000_0000 147: 148: end_lp: 149: #ifdef MCM 150: mov 5, r0 151: iext SEBDEN 152: sgio r0, SEBDEN 153: jmpr cc_uncond, 0 154: #endif 155: 156: mov CMD_LP, r0 0025 : 1100_0110_0000_0010_0100_0000 157: sgio r0, SMCMD 0026 : 0010_1000_0000_1010_0000_0100 158: 159: jmpr cc_uncond, 0 0027 : 0000_0100_0000_0100_1110_1111 160: nop 0028 : 0000_0000_0000_0000_0000_0000 161: 162: 163: 164: ;######################################### 165: ;# 166: ;# 0x0100: Interrrupt Tracklet Proces 167: ;# 168: ;# send delayed tracklet end 169: ;# 170: ;######################################### 171: 172: 173: org 0x0100 174: 175: #ifdef cpu0 176: nop 0100 : 0000_0000_0000_0000_0000_0000 177: nop 0101 : 0000_0000_0000_0000_0000_0000 178: nop 0102 : 0000_0000_0000_0000_0000_0000 179: nop 0103 : 0000_0000_0000_0000_0000_0000 180: #endif 181: 182: #ifdef cpu1 183: nop 184: nop 185: nop 186: nop 187: #endif 188: 189: #ifdef cpu2 190: nop 191: nop 192: nop 193: nop 194: #endif 195: 196: #ifdef cpu3 197: mov 1, r0 198: jmpr cc_busy, 0 199: sgio r0, EBSIM_FAST 200: nop 201: #endif 202: 203: 204: 205: ;################################# 206: ;# 207: ;# check result 208: ;# 209: ;################################# 210: 211: 212: mov EBR0, r8 ; load cha 0104 : 1100_0111_0000_0000_0000_1000 213: add r8, c1, r8 ; add +1 d 0105 : 1000_0010_1000_0110_0010_1000 214: mov EBR1, r9 0106 : 1100_0111_0000_1000_0000_1001 215: add r9, c1, r9 0107 : 1000_0010_1001_0110_0010_1001 216: mov EBR2, r10 0108 : 1100_0111_0001_0000_0000_1010 217: add r10, c1, r10 0109 : 1000_0010_1010_0110_0010_1010 218: mov EBR3, r11 010A : 1100_0111_0001_1000_0000_1011 219: add r11, c1, r11 010B : 1000_0010_1011_0110_0010_1011 220: mov EBR4, r12 010C : 1100_0111_0010_0000_0000_1100 221: add r12, c1, r12 010D : 1000_0010_1100_0110_0010_1100 222: mov EBR5, r13 010E : 1100_0111_0010_1000_0000_1101 223: add r13, c1, r13 010F : 1000_0010_1101_0110_0010_1101 224: 225: mov 0, r0 ; r0: time 0110 : 1100_0110_0000_0000_0000_0000 226: 227: mov 3, r2 0111 : 1100_0110_0000_0000_0110_0010 228: and r2, LUT_CTR, r2 ; r2: curr 0112 : 1010_0110_0010_0111_1010_0010 229: 230: loopTT: mov 0, r6 ; r6: erro 0113 : 1100_0110_0000_0000_0000_0110 231: 232: mov 11, r3 0114 : 1100_0110_0000_0001_0110_0011 233: mul32 r0, r3, r3 0115 : 1001_0000_0000_0000_0110_1011 234: nop 0116 : 0000_0000_0000_0000_0000_0000 235: add r3, OFFSET_CTR, r3 0117 : 1000_0010_0011_0111_1000_0011 236: cmp r3, 1023 0118 : 1100_1000_0011_0011_1111_1111 237: jmp cc_leu, TTval 0119 : 0000_0100_0000_0000_0001_1000 238: mov 1024, r4 011A : 1100_0110_1000_0000_0000_0100 239: sub r3, r4, r3 ; expected 011B : 1000_1010_0011_0000_1000_0011 240: 241: TTval: shl -4, r3, r1 ; expected 011C : 1011_0011_1100_0000_0110_0001 242: mov 63, r7 011D : 1100_0110_0000_0111_1110_0111 243: sub r7, r1, r1 ; r1: expe 011E : 1000_1010_0111_0000_0010_0001 244: shl 2, r3, r3 011F : 1011_0010_0010_0000_0110_0011 245: add r3, r1, r3 0120 : 1000_0010_0011_0000_0010_0011 246: add r3, r2, r3 0121 : 1000_0010_0011_0000_0100_0011 247: shl -2, r3, r3 0122 : 1011_0011_1110_0000_0110_0011 248: cmp r3, 1023 0123 : 1100_1000_0011_0011_1111_1111 249: jmp cc_leu, TTc0 0124 : 0000_0100_0000_0000_0001_1000 250: mov 1023, r3 ; r3: expe 0125 : 1100_0110_0111_1111_1110_0011 251: 252: TTc0: add r0, r8, r4 ; r4: even 0126 : 1000_0010_0000_0001_0000_0100 253: lpio r4, r5 0127 : 1110_0010_0000_0000_1000_0101 254: lpio r4, r5 ; r5: filt 0128 : 1110_0010_0000_0000_1000_0101 255: 256: cmp r3, r5 0129 : 1000_1000_0011_0000_1010_0000 257: jmp cc_eq, TTc1 012A : 0000_0100_0000_0000_0001_0001 258: add r6, c1, r6 012B : 1000_0010_0110_0110_0010_0110 259: 260: TTc1: add r0, r9, r4 ; r4: even 012C : 1000_0010_0000_0001_0010_0100 261: lpio r4, r5 012D : 1110_0010_0000_0000_1000_0101 262: lpio r4, r5 ; r5: filt 012E : 1110_0010_0000_0000_1000_0101 263: 264: cmp r3, r5 012F : 1000_1000_0011_0000_1010_0000 265: jmp cc_eq, TTc2 0130 : 0000_0100_0000_0000_0001_0001 266: add r6, c1, r6 0131 : 1000_0010_0110_0110_0010_0110 267: 268: TTc2: add r0, r10, r4 ; r4: even 0132 : 1000_0010_0000_0001_0100_0100 269: lpio r4, r5 0133 : 1110_0010_0000_0000_1000_0101 270: lpio r4, r5 ; r5: filt 0134 : 1110_0010_0000_0000_1000_0101 271: 272: cmp r3, r5 0135 : 1000_1000_0011_0000_1010_0000 273: jmp cc_eq, TTc3 0136 : 0000_0100_0000_0000_0001_0001 274: add r6, c1, r6 0137 : 1000_0010_0110_0110_0010_0110 275: 276: TTc3: add r0, r11, r4 ; r4: even 0138 : 1000_0010_0000_0001_0110_0100 277: lpio r4, r5 0139 : 1110_0010_0000_0000_1000_0101 278: lpio r4, r5 ; r5: filt 013A : 1110_0010_0000_0000_1000_0101 279: 280: cmp r3, r5 013B : 1000_1000_0011_0000_1010_0000 281: jmp cc_eq, TTc4 013C : 0000_0100_0000_0000_0001_0001 282: add r6, c1, r6 013D : 1000_0010_0110_0110_0010_0110 283: 284: TTc4: add r0, r12, r4 ; r4: even 013E : 1000_0010_0000_0001_1000_0100 285: lpio r4, r5 013F : 1110_0010_0000_0000_1000_0101 286: lpio r4, r5 ; r5: filt 0140 : 1110_0010_0000_0000_1000_0101 287: 288: cmp r3, r5 0141 : 1000_1000_0011_0000_1010_0000 289: jmp cc_eq, TTc5 0142 : 0000_0100_0000_0000_0001_0001 290: add r6, c1, r6 0143 : 1000_0010_0110_0110_0010_0110 291: 292: #ifdef cpu3 293: TTc5: add r0, r13, r4 ; r4: even 294: lpio r4, r5 295: lpio r4, r5 ; r5: filt 296: 297: cmp r3, r5 298: jmp cc_eq, TTend 299: add r6, c1, r6 300: #else 301: nop 0144 : 0000_0000_0000_0000_0000_0000 302: nop 0145 : 0000_0000_0000_0000_0000_0000 303: nop 0146 : 0000_0000_0000_0000_0000_0000 304: 305: nop 0147 : 0000_0000_0000_0000_0000_0000 306: nop 0148 : 0000_0000_0000_0000_0000_0000 307: TTc5: nop 0149 : 0000_0000_0000_0000_0000_0000 308: #endif 309: 310: TTend: add r6, ERROR_CTR, r6 014A : 1000_0010_0110_0111_0000_0110 311: jmpr cc_busy, 0 014B : 0000_0100_0010_1001_0111_0111 312: sgio r6, ERROR_ADR 014C : 0010_1000_0110_1100_0000_0000 313: 314: add r0, c1, r0 014D : 1000_0010_0000_0110_0010_0000 315: cmp r0, 31 014E : 1100_1000_0000_0000_0001_1111 316: jmp cc_ltu, loopTT 014F : 0000_0100_0000_0000_0001_0000 317: nop 0150 : 0000_0000_0000_0000_0000_0000 318: 319: 320: 321: 322: ;################################# 323: ;# 324: ;# increase counters 325: ;# 326: ;################################# 327: 328: 329: #ifdef cpu3 330: 331: mov 1, r1 332: add r1, LUT_CTR, r0 333: cmp r0, 4 334: jmp cc_ltu, ct_LUT 335: 336: mov 0, r0 337: mov 341, r1 338: add r1, OFFSET_CTR, r1 339: 340: jmpr cc_busy, 0 341: sgio r1, OFFSET_ADR 342: 343: ct_LUT: jmpr cc_busy, 0 344: sgio r0, LUT_ADR 345: 346: #else 347: 348: nop 0151 : 0000_0000_0000_0000_0000_0000 349: nop 0152 : 0000_0000_0000_0000_0000_0000 350: nop 0153 : 0000_0000_0000_0000_0000_0000 351: nop 0154 : 0000_0000_0000_0000_0000_0000 352: 353: nop 0155 : 0000_0000_0000_0000_0000_0000 354: nop 0156 : 0000_0000_0000_0000_0000_0000 355: nop 0157 : 0000_0000_0000_0000_0000_0000 356: 357: nop 0158 : 0000_0000_0000_0000_0000_0000 358: nop 0159 : 0000_0000_0000_0000_0000_0000 359: 360: nop 015A : 0000_0000_0000_0000_0000_0000 361: nop 015B : 0000_0000_0000_0000_0000_0000 362: 363: #endif 364: 365: jmpr cc_busy, 0 015C : 0000_0100_0010_1011_1001_0111 366: 367: 368: 369: ;################################# 370: ;# 371: ;# write next LUT test entrie 372: ;# 373: ;################################# 374: 375: 376: mov 3, r13 015D : 1100_0110_0000_0000_0110_1101 377: and r13, LUT_CTR, r13 ; r13: nex 015E : 1010_0110_1101_0111_1010_1101 378: 379: iext FPNP 015F : 0101_0000_0000_0000_0000_0011 380: mov FPNP, r0 0160 : 1100_0110_0000_0100_0010_0000 381: 382: jmpr cc_busy, 0 0161 : 0000_0100_0010_1100_0011_0111 383: sgio r13, r0 0162 : 0010_0100_1101_0000_0000_0000 384: 385: 386: 387: ;################################# 388: ;# 389: ;# write next test pattern in 390: ;# 391: ;################################# 392: 393: 394: #ifdef cpu3 395: 396: mov 0, r0 397: cmp r0, LUT_CTR 398: jmp cc_neq, endEB 399: 400: iext EBW 401: mov EBW, r0 402: mov 32, r1 403: add r0, r1, r0 ; r0: even 404: 405: mov 0, r1 ; r1: chan 406: mov 0, r2 ; r2: time 407: 408: loopEB: mov 11, r4 409: mul32 r2, r4, r4 410: nop 411: add r4, OFFSET_CTR, r4 412: shl 7, r1, r3 413: add r0, r3, r3 414: add r2, r3, r3 415: 416: jmpr cc_busy, 0 ; r3: sing 417: sgio r4, r3 ; r4: data 418: 419: mov 10, r5 420: 421: waitD: sub r5, c1, r5 422: jmp cc_gts, waitD 423: 424: add r1, c1, r1 425: cmp r1, 21 426: jmp cc_ltu, loopEB 427: 428: mov 0, r1 429: add r2, c1, r2 430: cmp r2, 32 431: jmp cc_ltu, loopEB 432: nop 433: endEB: mov 1, CPU_SYNC 434: 435: #else 436: 437: nop 0163 : 0000_0000_0000_0000_0000_0000 438: 439: #endif 440: 441: 442: 443: ;################################# 444: ;# 445: ;# wait for data writing comp 446: ;# 447: ;################################# 448: 449: 450: wsy: mov CPU_SYNC, r0 0164 : 1100_0010_0000_0010_0010_0000 451: cmp r0, 1 0165 : 1100_1000_0000_0000_0000_0001 452: jmp cc_neq, wsy 0166 : 0000_0100_0000_0000_0000_0001 453: 454: 455: ;################################# 456: ;# 457: ;# copy lower indicator words 458: ;# 459: ;################################# 460: 461: 462: #ifdef cpu0 463: mov 0x7B8, r15 0167 : 1100_0110_1111_0111_0000_1111 464: #endif 465: 466: #ifdef cpu1 467: mov 0x7CC, r15 468: #endif 469: 470: #ifdef cpu2 471: mov 0x7E0, r15 472: #endif 473: 474: #ifdef cpu3 475: mov 0x7F4, r15 476: #endif 477: 478: lpio EBI0, r0 0168 : 1110_0111_0011_0000_0000_0000 479: lpio EBI0, r0 0169 : 1110_0111_0011_0000_0000_0000 480: sra+ r0 016A : 0011_1000_0000_0000_0000_0000 481: 482: lpio EBI2, r0 016B : 1110_0111_0011_0000_0100_0000 483: lpio EBI2, r0 016C : 1110_0111_0011_0000_0100_0000 484: sra+ r0 016D : 0011_1000_0000_0000_0000_0000 485: 486: lpio EBI4, r0 016E : 1110_0111_0011_0000_1000_0000 487: lpio EBI4, r0 016F : 1110_0111_0011_0000_1000_0000 488: sra+ r0 0170 : 0011_1000_0000_0000_0000_0000 489: 490: lpio EBI6, r0 0171 : 1110_0111_0011_0000_1100_0000 491: lpio EBI6, r0 0172 : 1110_0111_0011_0000_1100_0000 492: sra+ r0 0173 : 0011_1000_0000_0000_0000_0000 493: 494: lpio EBI8, r0 0174 : 1110_0111_0011_0001_0000_0000 495: lpio EBI8, r0 0175 : 1110_0111_0011_0001_0000_0000 496: sra+ r0 0176 : 0011_1000_0000_0000_0000_0000 497: 498: #ifdef cpu3 499: lpio EBIA, r0 500: lpio EBIA, r0 501: sra+ r0 502: #else 503: nop 0177 : 0000_0000_0000_0000_0000_0000 504: nop 0178 : 0000_0000_0000_0000_0000_0000 505: nop 0179 : 0000_0000_0000_0000_0000_0000 506: #endif 507: 508: 509: ;################################# 510: ;# 511: ;# DMEM address to copy event 512: ;# beware: byte address = 4 * 513: ;# 514: ;################################# 515: 516: #ifdef cpu0 517: mov 0x080, r15 017A : 1100_0110_0001_0000_0000_1111 518: #endif 519: 520: #ifdef cpu1 521: mov 0x238, r15 522: #endif 523: 524: #ifdef cpu2 525: mov 0x3F0, r15 526: #endif 527: 528: #ifdef cpu3 529: mov 0x5A8, r15 530: #endif 531: 532: ;################################# 533: ;# 534: ;# channel check bits, absolu 535: ;# 536: ;################################# 537: 538: #ifdef cpu0 539: mov 3, r3 017B : 1100_0110_0000_0000_0110_0011 540: #endif 541: 542: #ifdef cpu1 543: mov 2, r3 544: #endif 545: 546: #ifdef cpu2 547: mov 3, r3 548: #endif 549: 550: #ifdef cpu3 551: mov 2, r3 552: #endif 553: 554: ;################################# 555: ;# 556: ;# copy event buffer data of 557: ;# 558: ;################################# 559: 560: mov EBR0, r14 017C : 1100_0111_0000_0000_0000_1110 561: mov 66, r5 017D : 1100_0110_0000_1000_0100_0101 562: 563: loop0: lpio+ r0 017E : 1110_1110_0000_0000_0000_0000 564: lpio+ r0 017F : 1110_1110_0000_0000_0000_0000 565: lpio+ r1 0180 : 1110_1110_0000_0000_0000_0001 566: lpio r14, r2 0181 : 1110_0010_0000_0001_1100_0010 567: 568: shl 10, r2, r2 0182 : 1011_0010_1010_0000_0100_0010 569: or r1, r2, r2 0183 : 1010_1010_0001_0000_0100_0010 570: shl 10, r2, r2 0184 : 1011_0010_1010_0000_0100_0010 571: or r0, r2, r2 0185 : 1010_1010_0000_0000_0100_0010 572: shl 2, r2, r2 0186 : 1011_0010_0010_0000_0100_0010 573: or r3, r2, r2 0187 : 1010_1010_0011_0000_0100_0010 574: 575: sra+ r2 0188 : 0011_1000_0010_0000_0000_0000 576: 577: sub r5, c3, r5 0189 : 1000_1010_0101_0110_0110_0101 578: jmp cc_gtu, loop0 018A : 0000_0100_0000_0000_0000_1000 579: 580: ;################################# 581: ;# 582: ;# copy event buffer data of 583: ;# 584: ;################################# 585: 586: mov EBR1, r14 018B : 1100_0111_0000_1000_0000_1110 587: mov 66, r5 018C : 1100_0110_0000_1000_0100_0101 588: xor r3, c1, r3 018D : 1010_0010_0011_0110_0010_0011 589: 590: loop1: lpio+ r0 018E : 1110_1110_0000_0000_0000_0000 591: lpio+ r0 018F : 1110_1110_0000_0000_0000_0000 592: lpio+ r1 0190 : 1110_1110_0000_0000_0000_0001 593: lpio r14, r2 0191 : 1110_0010_0000_0001_1100_0010 594: 595: shl 10, r2, r2 0192 : 1011_0010_1010_0000_0100_0010 596: or r1, r2, r2 0193 : 1010_1010_0001_0000_0100_0010 597: shl 10, r2, r2 0194 : 1011_0010_1010_0000_0100_0010 598: or r0, r2, r2 0195 : 1010_1010_0000_0000_0100_0010 599: shl 2, r2, r2 0196 : 1011_0010_0010_0000_0100_0010 600: or r3, r2, r2 0197 : 1010_1010_0011_0000_0100_0010 601: 602: sra+ r2 0198 : 0011_1000_0010_0000_0000_0000 603: 604: sub r5, c3, r5 0199 : 1000_1010_0101_0110_0110_0101 605: jmp cc_gtu, loop1 019A : 0000_0100_0000_0000_0000_1000 606: 607: ;################################# 608: ;# 609: ;# copy event buffer data of 610: ;# 611: ;################################# 612: 613: mov EBR2, r14 019B : 1100_0111_0001_0000_0000_1110 614: mov 66, r5 019C : 1100_0110_0000_1000_0100_0101 615: xor r3, c1, r3 019D : 1010_0010_0011_0110_0010_0011 616: 617: loop2: lpio+ r0 019E : 1110_1110_0000_0000_0000_0000 618: lpio+ r0 019F : 1110_1110_0000_0000_0000_0000 619: lpio+ r1 01A0 : 1110_1110_0000_0000_0000_0001 620: lpio r14, r2 01A1 : 1110_0010_0000_0001_1100_0010 621: 622: shl 10, r2, r2 01A2 : 1011_0010_1010_0000_0100_0010 623: or r1, r2, r2 01A3 : 1010_1010_0001_0000_0100_0010 624: shl 10, r2, r2 01A4 : 1011_0010_1010_0000_0100_0010 625: or r0, r2, r2 01A5 : 1010_1010_0000_0000_0100_0010 626: shl 2, r2, r2 01A6 : 1011_0010_0010_0000_0100_0010 627: or r3, r2, r2 01A7 : 1010_1010_0011_0000_0100_0010 628: 629: sra+ r2 01A8 : 0011_1000_0010_0000_0000_0000 630: 631: sub r5, c3, r5 01A9 : 1000_1010_0101_0110_0110_0101 632: jmp cc_gtu, loop2 01AA : 0000_0100_0000_0000_0000_1000 633: 634: ;################################# 635: ;# 636: ;# copy event buffer data of 637: ;# 638: ;################################# 639: 640: mov EBR3, r14 01AB : 1100_0111_0001_1000_0000_1110 641: mov 66, r5 01AC : 1100_0110_0000_1000_0100_0101 642: xor r3, c1, r3 01AD : 1010_0010_0011_0110_0010_0011 643: 644: loop3: lpio+ r0 01AE : 1110_1110_0000_0000_0000_0000 645: lpio+ r0 01AF : 1110_1110_0000_0000_0000_0000 646: lpio+ r1 01B0 : 1110_1110_0000_0000_0000_0001 647: lpio r14, r2 01B1 : 1110_0010_0000_0001_1100_0010 648: 649: shl 10, r2, r2 01B2 : 1011_0010_1010_0000_0100_0010 650: or r1, r2, r2 01B3 : 1010_1010_0001_0000_0100_0010 651: shl 10, r2, r2 01B4 : 1011_0010_1010_0000_0100_0010 652: or r0, r2, r2 01B5 : 1010_1010_0000_0000_0100_0010 653: shl 2, r2, r2 01B6 : 1011_0010_0010_0000_0100_0010 654: or r3, r2, r2 01B7 : 1010_1010_0011_0000_0100_0010 655: 656: sra+ r2 01B8 : 0011_1000_0010_0000_0000_0000 657: 658: sub r5, c3, r5 01B9 : 1000_1010_0101_0110_0110_0101 659: jmp cc_gtu, loop3 01BA : 0000_0100_0000_0000_0000_1000 660: 661: ;################################# 662: ;# 663: ;# copy event buffer data of 664: ;# 665: ;################################# 666: 667: mov EBR4, r14 01BB : 1100_0111_0010_0000_0000_1110 668: mov 66, r5 01BC : 1100_0110_0000_1000_0100_0101 669: xor r3, c1, r3 01BD : 1010_0010_0011_0110_0010_0011 670: 671: loop4: lpio+ r0 01BE : 1110_1110_0000_0000_0000_0000 672: lpio+ r0 01BF : 1110_1110_0000_0000_0000_0000 673: lpio+ r1 01C0 : 1110_1110_0000_0000_0000_0001 674: lpio r14, r2 01C1 : 1110_0010_0000_0001_1100_0010 675: 676: shl 10, r2, r2 01C2 : 1011_0010_1010_0000_0100_0010 677: or r1, r2, r2 01C3 : 1010_1010_0001_0000_0100_0010 678: shl 10, r2, r2 01C4 : 1011_0010_1010_0000_0100_0010 679: or r0, r2, r2 01C5 : 1010_1010_0000_0000_0100_0010 680: shl 2, r2, r2 01C6 : 1011_0010_0010_0000_0100_0010 681: or r3, r2, r2 01C7 : 1010_1010_0011_0000_0100_0010 682: 683: sra+ r2 01C8 : 0011_1000_0010_0000_0000_0000 684: 685: sub r5, c3, r5 01C9 : 1000_1010_0101_0110_0110_0101 686: jmp cc_gtu, loop4 01CA : 0000_0100_0000_0000_0000_1000 687: 688: ;################################# 689: ;# 690: ;# copy event buffer data of 691: ;# 692: ;################################# 693: 694: #ifdef cpu3 695: mov EBR5, r14 696: mov 66, r5 697: xor r3, c1, r3 698: 699: loop5: lpio+ r0 700: lpio+ r0 701: lpio+ r1 702: lpio r14, r2 703: 704: shl 10, r2, r2 705: or r1, r2, r2 706: shl 10, r2, r2 707: or r0, r2, r2 708: shl 2, r2, r2 709: or r3, r2, r2 710: 711: sra+ r2 712: 713: sub r5, c3, r5 714: jmp cc_gtu, loop5 715: #else 716: nop 01CB : 0000_0000_0000_0000_0000_0000 717: nop 01CC : 0000_0000_0000_0000_0000_0000 718: nop 01CD : 0000_0000_0000_0000_0000_0000 719: nop 01CE : 0000_0000_0000_0000_0000_0000 720: nop 01CF : 0000_0000_0000_0000_0000_0000 721: nop 01D0 : 0000_0000_0000_0000_0000_0000 722: nop 01D1 : 0000_0000_0000_0000_0000_0000 723: nop 01D2 : 0000_0000_0000_0000_0000_0000 724: nop 01D3 : 0000_0000_0000_0000_0000_0000 725: nop 01D4 : 0000_0000_0000_0000_0000_0000 726: nop 01D5 : 0000_0000_0000_0000_0000_0000 727: nop 01D6 : 0000_0000_0000_0000_0000_0000 728: nop 01D7 : 0000_0000_0000_0000_0000_0000 729: nop 01D8 : 0000_0000_0000_0000_0000_0000 730: nop 01D9 : 0000_0000_0000_0000_0000_0000 731: nop 01DA : 0000_0000_0000_0000_0000_0000 732: #endif 733: 734: 735: ;################################# 736: ;# 737: ;# end current state, goto cl 738: ;# 739: ;################################# 740: 741: 742: #ifdef cpu3 743: 744: mov 0, r0 745: jmpr cc_busy, 0 746: sgio r0, EBSIM_FAST 747: 748: mov CMD_CLEAR, r0 749: jmpr cc_busy, 0 750: sgio r0, SMCMD 751: 752: #else 753: 754: nop 01DB : 0000_0000_0000_0000_0000_0000 755: nop 01DC : 0000_0000_0000_0000_0000_0000 756: nop 01DD : 0000_0000_0000_0000_0000_0000 757: 758: nop 01DE : 0000_0000_0000_0000_0000_0000 759: nop 01DF : 0000_0000_0000_0000_0000_0000 760: nop 01E0 : 0000_0000_0000_0000_0000_0000 761: 762: #endif 763: 764: 765: 766: ;################################# 767: ;# 768: ;# switch off own clock after 769: ;# 770: ;################################# 771: 772: 773: clkoff: mov 0, r0 01E1 : 1100_0110_0000_0000_0000_0000 774: jmpr cc_busy, 0 01E2 : 0000_0100_0011_1100_0101_0111 775: 776: #ifdef cpu0 777: sgio r0, CPU0SS 01E3 : 0010_1000_0000_1010_0010_0001 778: #endif 779: 780: #ifdef cpu1 781: sgio r0, CPU1SS 782: #endif 783: 784: #ifdef cpu2 785: sgio r0, CPU2SS 786: #endif 787: 788: #ifdef cpu3 789: sgio r0, CPU3SS 790: #endif 791: 792: jmp cc_uncond, clkoff 01E4 : 0000_0100_0000_0000_0000_1111 793: nop 01E5 : 0000_0000_0000_0000_0000_0000 794: 795: 796: 797: ;######################################### 798: ;# 799: ;# 0x0300: Interrrupt Raw Data Readou 800: ;# 801: ;# Nothing to be done here. 802: ;# 803: ;######################################### 804: 805: 806: org 0x300 807: 808: jmp cc_uncond, clkoff 0300 : 0000_0100_0000_0000_0000_1111 809: nop 0301 : 0000_0000_0000_0000_0000_0000 810: 811: 812: 813: 814: 815: 816: 817: 818: 819: 820: 821: 822: 823: 824: 825: 826: 827: 828: Source file read, 0 error(s), 0 warning(s).