Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.7, Jul 2008 SVN Revision 2158, SVN Date 2008-07-17 Please send any comments to: angelov@kip.uni-heidelberg.de 11:44:03 / 24 Nov 2008 Source code file: SignalProcessing.asm Memory initialisation file: Log file: ../work/cpu0.log Program memory size in words: 4096 Default constants, read from /usr/share/trap/asm_mimd.inc 1 CPU0 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 107 ASM_SVN_REV = 2158 1: ;########################################################### 2: ;# 3: ;# Test Program for nonlinearity filter. 4: ;# 5: ;# Input data is taken from event buffer and stored bac 6: ;# another memory region. 7: ;# 8: ;# Marcus Gutfleisch 9: ;# Ruprecht-Karls-Universität Heidelberg, Kirchhoff-Ins 10: ;# 11: ;# Heidelberg, 18.03.2005 12: ;# 13: ;########################################################### 14: 15: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt tttt tttt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt tttt tttt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt tttt tttt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snme eeee ddd 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc cccc cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- ---- --St oam 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- ---- --St oam 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- ---- --St oam 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- ---- --St oam 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- ---- --St oam 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- ---- --St oam 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- ---- --St oam 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- ---- --St oam 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- ---- --St oam 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- ---- --St oam 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- ---- --St oam 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- ---- --St oam 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- ---- ---- --- 30: 31: #def CTGDINI=0x0B80; dddd dddd dddd dddd dddd dddd dddd dddd 32: #def CTGCTRL=0x0B81; ---- ---- ---- ---- ---S idce essb bbbb 33: #def CTGDOUT=0x0B82; DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 34: #def CTPDINI=0x0200; dddd dddd dddd dddd dddd dddd dddd dddd 35: #def CTPCTRL=0x0201; ---- ---- ---- ---- ---S idce essb bbbb 36: #def CTPDOUT=0x0202; DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 37: 38: #def PASADEL=0x3158; ---- ---- ---- ---- ---- ---- aaaa aaa 39: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- ---- --aa aaa 40: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- ---- --aa aaa 41: #def PASADAC=0x315B; ---- ---- ---- ---- ---- ---- aaaa aaa 42: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaaa aaaa aaa 43: #def PASASTL=0x315D; ---- ---- ---- ---- ---- ---- aaaa aaa 44: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- ---- ---- --- 45: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- ---- ---- --- 46: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaaa aaaa aaa 47: #def ADCINB=0x3051; ---- ---- ---- ---- ---- ---- ---- --m 48: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- ---- ---d ddd 49: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssbz hhhe app 50: #def ADCTST=0x3054; ---- ---- ---- ---- ---- ---- ---- --t 51: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- ---- ---- --- 52: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- ---- ---- --- 53: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- ---- ---- --- 54: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- ---- ---- -aa 55: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- ---- -ret aii 56: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaaa aaaa aaa 57: #def SADCEC=0x3166; ---- ---- ---- ---- ---- ---- -daa ate 58: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --AA AAAA AAA 59: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --AA AAAA AAA 60: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --AA AAAA AAA 61: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --AA AAAA AAA 62: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --AA AAAA AAA 63: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --AA AAAA AAA 64: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --AA AAAA AAA 65: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --AA AAAA AAA 66: #def SADCMC=0x3170; ---- ---- ---- ---- ---- ---- aaaa aaa 67: #def SADCOC=0x3171; ---- ---- ---- ---- ---- ---- aaaa aaa 68: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd cccc bbbb aaa 69: #def SADCTC=0x3173; ---- ---- ---- ---- ---- ---- ---- -aa 70: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -eaa aaaa aaa 71: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- ---- ---- -ee 72: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- ---- ---- -oo 73: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- ---- ---- -ii 74: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAAA AAAA AAA 75: #def TPPT0=0x3000; ---- ---- ---- ---- ---- ---- -ddd ddd 76: #def TPPAE=0x3004; ---- ---- ---- ---- ---- ---- -ddd ddd 77: #def TPPGR=0x3003; ---- ---- ---- ---- ---- ---- -ddd ddd 78: #def FLBY=0x3018; ---- ---- ---- ---- ---- ---- ---- --- 79: #def FLL=0x3100; ---- ---- ---- ---- ---- ---- --dd ddd 80: #def FPBY=0x3019; ---- ---- ---- ---- ---- ---- ---- --- 81: #def FPTC=0x3020; ---- ---- ---- ---- ---- ---- ---- --d 82: #def FPNP=0x3021; ---- ---- ---- ---- ---- ---d dddd ddd 83: #def FPCL=0x3022; ---- ---- ---- ---- ---- ---- ---- --- 84: #def FPA=0x3060; --dd dddd dddd dddd dddd dddd dddd ddd 85: #def FGBY=0x301A; ---- ---- ---- ---- ---- ---- ---- --- 86: #def FGFn=0x3080; ---- ---- ---- ---- ---- ---d dddd ddd 87: #def FGAn=0x30A0; ---- ---- ---- ---- ---- ---- --dd ddd 88: #def FGTA=0x3028; ---- ---- ---- ---- ---- dddd dddd ddd 89: #def FGTB=0x3029; ---- ---- ---- ---- ---- dddd dddd ddd 90: #def FGCL=0x302A; ---- ---- ---- ---- ---- ---- ---- --- 91: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd dddd dddd ddd 92: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd dddd dddd ddd 93: #def FTBY=0x301B; ---- ---- ---- ---- ---- ---- ---- --- 94: #def FTAL=0x3030; ---- ---- ---- ---- ---- --dd dddd ddd 95: #def FTLL=0x3031; ---- ---- ---- ---- ---- --dd dddd ddd 96: #def FTLS=0x3032; ---- ---- ---- ---- ---- --dd dddd ddd 97: #def FCBY=0x301C; ---- ---- ---- ---- ---- ---- ---- --- 98: #def FCWn=0x3038; ---- ---- ---- ---- ---- ---- dddd ddd 99: #def TPFS=0x3001; ---- ---- ---- ---- ---- ---- -ddd ddd 100: #def TPFE=0x3002; ---- ---- ---- ---- ---- ---- -ddd ddd 101: #def TPQS0=0x3005; ---- ---- ---- ---- ---- ---- -ddd ddd 102: #def TPQE0=0x3006; ---- ---- ---- ---- ---- ---- -ddd ddd 103: #def TPQS1=0x3007; ---- ---- ---- ---- ---- ---- -ddd ddd 104: #def TPQE1=0x3008; ---- ---- ---- ---- ---- ---- -ddd ddd 105: #def TPHT=0x3041; ---- ---- ---- ---- --dd dddd dddd ddd 106: #def TPVBY=0x3043; ---- ---- ---- ---- ---- ---- ---- --- 107: #def TPVT=0x3042; ---- ---- ---- ---- ---- ---- --dd ddd 108: #def TPFP=0x3040; ---- ---- ---- ---- ---- ---- --dd ddd 109: #def TPL=0x3180; ---- ---- ---- ---- ---- ---- ---d ddd 110: #def TPCL=0x3045; ---- ---- ---- ---- ---- ---- ---d ddd 111: #def TPCT=0x3044; ---- ---- ---- ---- ---- ---- ---d ddd 112: #def TPD=0x3047; ---- ---- ---- ---- ---- ---- ---- ddd 113: #def TPH=0x3140; ---- ---- ---- ---- ---- ---- ---d ddd 114: #def TPCBY=0x3046; ---- ---- ---- ---- ---- ---- ---- --- 115: #def TPCI0=0x3048; ---- ---- ---- ---- ---- ---- ---d ddd 116: #def TPCI1=0x3049; ---- ---- ---- ---- ---- ---- ---d ddd 117: #def TPCI2=0x304A; ---- ---- ---- ---- ---- ---- ---d ddd 118: #def TPCI3=0x304B; ---- ---- ---- ---- ---- ---- ---d ddd 119: #def EBD=0x3009; ---- ---- ---- ---- ---- ---- ---- -dd 120: #def EBSF=0x300C; ---- ---- ---- ---- ---- ---- ---- --- 121: #def EBAQA=0x300A; ---- ---- ---- ---- ---- ---- -ddd ddd 122: #def EBSIM=0x300D; ---- ---- ---- ---- ---- ---- ---- --- 123: #def EBSIA=0x300B; ---- ---- ---- ---- ---- ---- -ddd ddd 124: #def EBR=0x0800; ---- ---- ---- ---- ---- -pdd dddd ddd 125: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pdd dddd ddd 126: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pdd dddd ddd 127: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pdd dddd ddd 128: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pdd dddd ddd 129: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pdd dddd ddd 130: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pdd dddd ddd 131: #def EBW=0x2000; ---- ---- ---- ---- ---- --dd dddd ddd 132: #def EBPP=0x300E; ---- ---- ---- ---- ---- ---- ---- --- 133: #def EBPC=0x300F; ---- ---- ---- ---- ---- ---- ---- --- 134: #def EBP0=0x3010; ---- ---- ---- ---- ---- ---d dddd ddd 135: #def EBP1=0x3011; ---- ---- ---- ---- ---- ---d dddd ddd 136: #def EBP2=0x3012; ---- ---- ---- ---- ---- ---d dddd ddd 137: #def EBP3=0x3013; ---- ---- ---- ---- ---- ---d dddd ddd 138: #def EBIS=0x3014; ---- ---- ---- ---- ---- --dd dddd ddd 139: #def EBIT=0x3015; ---- ---- ---- ---- ---- dddd dddd ddd 140: #def EBIL=0x3016; ---- ---- ---- ---- ---- ---- dddd ddd 141: #def EBIN=0x3017; ---- ---- ---- ---- ---- ---- ---- --- 142: #def EBI=0x0980; dddd dddd dddd dddd dddd dddd dddd ddd 143: #def EBI0=0x0980; dddd dddd dddd dddd dddd dddd dddd dd 144: #def EBI1=0x0981; dddd dddd dddd dddd dddd dddd dddd dd 145: #def EBI2=0x0982; dddd dddd dddd dddd dddd dddd dddd dd 146: #def EBI3=0x0983; dddd dddd dddd dddd dddd dddd dddd dd 147: #def EBI4=0x0984; dddd dddd dddd dddd dddd dddd dddd dd 148: #def EBI5=0x0985; dddd dddd dddd dddd dddd dddd dddd dd 149: #def EBI6=0x0986; dddd dddd dddd dddd dddd dddd dddd dd 150: #def EBI7=0x0987; dddd dddd dddd dddd dddd dddd dddd dd 151: #def EBI8=0x0988; dddd dddd dddd dddd dddd dddd dddd dd 152: #def EBI9=0x0989; dddd dddd dddd dddd dddd dddd dddd dd 153: #def EBIA=0x098A; dddd dddd dddd dddd dddd dddd dddd dd 154: #def EBIB=0x098B; dddd dddd dddd dddd dddd dddd dddd dd 155: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- ---- ---- wwr 156: #def MEMRW=0xD000; ---- ---- ---- ---- ---- ---- -www wrr 157: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- ---b dddd iii 158: #def DMDELA=0xD002; ---- ---- ---- ---- ---- ---- ---- aaa 159: #def DMDELS=0xD003; ---- ---- ---- ---- ---- ---- ---- sss 160: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 161: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 162: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 163: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 164: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 165: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 166: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 167: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 168: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaaa aaaa aaa 169: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaaa aaaa aaa 170: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaaa aaaa aaa 171: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaaa aaaa aaa 172: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmmm mmmm mmm 173: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmmm mmmm mmm 174: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmmm mmmm mmm 175: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmmm mmmm mmm 176: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmmm mmmm mmm 177: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmmm mmmm mmm 178: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmmm mmmm mmm 179: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmmm mmmm mmm 180: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmmm mmmm mmm 181: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmmm mmmm mmm 182: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmmm mmmm mmm 183: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmmm mmmm mmm 184: #def NMOD=0x0D40; ---- ---- ---- ---- ---- ---- ---i cmm 185: #def NTRO=0x0D43; ---- ---- ---- --ii iddd cccb bbaa aff 186: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt tttt tttt ttt 187: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbbb aaaa aaa 188: #def NRRO=0x0D44; ---- ---- ---- --ii iddd cccb bbaa aff 189: #def NTP=0x0D46; pppp pppp pppp pppp pppp pppp pppp ppp 190: #def NP0=0x0D48; ---- ---- ---- ---- ---- -ppp pfff fec 191: #def NP1=0x0D49; ---- ---- ---- ---- ---- -ppp pfff fec 192: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -ppp pfff fec 193: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -ppp pfff fec 194: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLLL CCCC CCC 195: #def NED=0x0D42; ---- ---- ---- ---- orpp ppff ffcc css 196: #def NDLY=0x0D41; --jj jiii hhhg ggff feee dddc ccbb baa 197: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhhh llll lll 198: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DSS EHLZ YXW 199: #def NLE=0x00C2; ---- ---- ---- ---- ---- ---- EEEE EEE 200: #def NFE=0x0DC1; ---- ---- ---- ---- ---- ---- ---- DCB 201: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- ---- ---- --- 202: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- ---- ---S SSS 203: #def NITM0=0x0A08; ---- ---- ---- ---- --tt tttt tttt ttt 204: #def NITM1=0x0A09; ---- ---- ---- ---- --tt tttt tttt ttt 205: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt tttt tttt ttt 206: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt tttt tttt ttt 207: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd dddd dddd ddd 208: #def SMON=0x0A06; ---- ---- ---- ---- ---- dddd dddd ddd 209: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- dddd dddd ddd 210: #def NODP=0x0000; dddd dddd dddd dddd dddd dddd dddd ddd 211: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- ---- ---- 212: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- ---- ---- 213: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- ---- ---- 214: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- ---- ---- 215: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- ---- ---- 216: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- ---- ---- 217: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- ---- ---- 218: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- ---- ---- 219: #def GBUSR0=0x0300; -- readonly 220: #def GBUSR1=0x0301; -- readonly *** End of include file /usr/share/trap//conf_va.inc *** Include file ../../assembler.inc 1: ;#define MCM=1; 2: ;#define WAFER=1; 3: #define ROB=1; *** End of include file ../../assembler.inc 18: 19: 20: 21: ;################################################### 22: ;# 23: ;# defines 24: ;# 25: ;################################################### 26: 27: 28: #def EBSIM_FAST = g0 29: #def CPU_SYNC = g1 30: 31: 32: #def TA_ERROR_CTR = c8 33: #def TB_ERROR_CTR = c9 34: #def OFFSET_CTR = c12 35: 36: #def OFFSET_ADR = 0xC04 37: 38: #ifdef cpu0 39: #def TA_ERROR_ADR = 0xC00 40: #def TB_ERROR_ADR = 0xC01 41: #endif 42: #ifdef cpu1 43: #def TA_ERROR_ADR = 0xC08 44: #def TB_ERROR_ADR = 0xC09 45: #endif 46: #ifdef cpu2 47: #def TA_ERROR_ADR = 0xC10 48: #def TB_ERROR_ADR = 0xC11 49: #endif 50: #ifdef cpu3 51: #def TA_ERROR_ADR = 0xC18 52: #def TB_ERROR_ADR = 0xC19 53: #endif 54: 55: 56: 57: ;################################################### 58: ;# 59: ;# 0x0000: Infinite Loop at Instruction Memory 60: ;# 61: ;################################################### 62: 63: 64: org 0x0000 65: 66: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 67: nop 0001 : 0000_0000_0000_0000_0000_0000 68: 69: 70: 71: ;################################################### 72: ;# 73: ;# 0x0010: Interrrupt Clear Jump Address 74: ;# 75: ;# CPU0: switch off all NI LVDS cells 76: ;# switch off NI clock 77: ;# switch off preprocessor cloc 78: ;# switch on filter clock 79: ;# 80: ;# CPU1: end clear state, arm state m 81: ;# 82: ;# CPU2: get tracklet end signature ( 83: ;# 84: ;# CPU3: get data end signature (???) 85: ;# 86: ;################################################### 87: 88: 89: org 0x0010 90: 91: mov 0, r12 0010 : 1100_0110_0000_0000_0000_1100 92: mov 4, r13 0011 : 1100_0110_0000_0000_1000_1101 93: 94: #ifdef cpu0 95: 96: iext EBSIM 0012 : 0101_0000_0000_0000_0000_0011 97: mov EBSIM, EBSIM_FAST 0013 : 1100_0110_0000_0001_1011_0000 98: mov 0, CPU_SYNC 0014 : 1100_0110_0000_0000_0001_0001 99: 100: iext b1111_0101_0000_0000_0010_0000 0015 : 0101_0000_0000_1111_0101_0000 101: mov b1111_0101_0000_0000_0010_0000, r0 0016 : 1100_0110_0000_0100_0000_0000 102: jmpr cc_busy, 0 0017 : 0000_0100_0000_0010_1111_0111 103: sgio r0, SMOFFON 0018 : 0010_1000_0000_1010_0000_0101 104: 105: mov CMD_EXT_CLR, r0 0019 : 1100_0110_0110_0010_0100_0000 106: mov CMD_PRETRIGG, r1 001A : 1100_0110_1010_0010_0100_0001 107: mov 1020, r2 001B : 1100_0110_0111_1111_1000_0010 108: jmpr cc_busy, 0 001C : 0000_0100_0000_0011_1001_0111 109: cmp r2, OFFSET_CTR 001D : 1000_1000_0010_0111_1000_0000 110: jmp cc_leu, end_lp 001E : 0000_0100_0000_0000_0001_1000 111: sgio r0, SMCMD 001F : 0010_1000_0000_1010_0000_0100 112: 113: nop 0020 : 0000_0000_0000_0000_0000_0000 114: nop 0021 : 0000_0000_0000_0000_0000_0000 115: sgio r1, SMCMD 0022 : 0010_1000_0001_1010_0000_0100 116: 117: #else 118: 119: #ifdef MCM 120: #ifdef cpu1 121: mov 0, r0 122: iext SEBDOU 123: sgio r0, SEBDOU 124: #else 125: nop 126: nop 127: nop 128: #endif 129: #endif 130: 131: nop 132: nop 133: nop 134: nop 135: 136: nop 137: nop 138: nop 139: nop 140: nop 141: 142: nop 143: nop 144: nop 145: 146: #endif 147: 148: end_cl: jmpr cc_uncond, 0 0023 : 0000_0100_0000_0100_0110_1111 149: nop 0024 : 0000_0000_0000_0000_0000_0000 150: 151: end_lp: 152: #ifdef MCM 153: mov 5, r0 154: iext SEBDEN 155: sgio r0, SEBDEN 156: jmpr cc_busy, 0 157: #endif 158: 159: mov CMD_LP, r0 0025 : 1100_0110_0000_0010_0100_0000 160: sgio r0, SMCMD 0026 : 0010_1000_0000_1010_0000_0100 161: 162: jmpr cc_uncond, 0 0027 : 0000_0100_0000_0100_1110_1111 163: nop 0028 : 0000_0000_0000_0000_0000_0000 164: 165: 166: 167: ;################################################### 168: ;# 169: ;# 0x0100: Interrrupt Tracklet Processing Jump 170: ;# 171: ;# send delayed tracklet end marker 172: ;# 173: ;################################################### 174: 175: 176: org 0x0100 177: 178: #ifdef cpu0 179: nop 0100 : 0000_0000_0000_0000_0000_0000 180: nop 0101 : 0000_0000_0000_0000_0000_0000 181: nop 0102 : 0000_0000_0000_0000_0000_0000 182: nop 0103 : 0000_0000_0000_0000_0000_0000 183: #endif 184: 185: #ifdef cpu1 186: nop 187: nop 188: nop 189: nop 190: #endif 191: 192: #ifdef cpu2 193: nop 194: nop 195: nop 196: nop 197: #endif 198: 199: #ifdef cpu3 200: mov 1, r0 201: jmpr cc_busy, 0 202: sgio r0, EBSIM_FAST 203: nop 204: #endif 205: 206: 207: 208: ;########################################### 209: ;# 210: ;# check result 211: ;# 212: ;########################################### 213: 214: 215: #ifdef cpu3 216: nop 217: #else 218: jmp cc_uncond, wsy 0104 : 0000_0100_0000_0000_0000_1111 219: #endif 220: 221: mov 127, r1 ; r1: FGTA entry 0105 : 1100_0110_0000_1111_1110_0001 222: mov 511, r2 ; r2: FGTB entry 0106 : 1100_0110_0011_1111_1110_0010 223: 224: mov 0, r4 ; TA CTR expected en 0107 : 1100_0110_0000_0000_0000_0100 225: mov 0, r5 ; TB CTR expected en 0108 : 1100_0110_0000_0000_0000_0101 226: 227: mov 29, r3 0109 : 1100_0110_0000_0011_1010_0011 228: add r3, OFFSET_CTR, r3 010A : 1000_0010_0011_0111_1000_0011 229: shl 2, r3, r3 ; r3: current upper 010B : 1011_0010_0010_0000_0110_0011 230: 231: shl -2, r1, r8 010C : 1011_0011_1110_0000_0010_1000 232: shl -2, r2, r9 010D : 1011_0011_1110_0000_0100_1001 233: shl -2, r3, r10 010E : 1011_0011_1110_0000_0110_1010 234: 235: cmp r1, r3 010F : 1000_1000_0001_0000_0110_0000 236: jmp cc_gtu, ctrg ; . < TA 0110 : 0000_0100_0000_0000_0000_1000 237: 238: sub r10, r8, r4 0111 : 1000_1010_1010_0001_0000_0100 239: 240: cmp r2, r3 0112 : 1000_1000_0010_0000_0110_0000 241: jmp cc_gtu, ctrg ; TA <= . < TB 0113 : 0000_0100_0000_0000_0000_1000 242: 243: sub r9, r8, r4 ; TB <= . 0114 : 1000_1010_1001_0001_0000_0100 244: sub r10, r9, r5 0115 : 1000_1010_1010_0001_0010_0101 245: 246: ctrg: mov 0, r0 ; r0: channel loop c 0116 : 1100_0110_0000_0000_0000_0000 247: mov 0, r6 ; r6: TA error incre 0117 : 1100_0110_0000_0000_0000_0110 248: mov 0, r7 ; r7: TB error incre 0118 : 1100_0110_0000_0000_0000_0111 249: 250: iext FGCAn 0119 : 0101_0000_0000_0000_0000_0011 251: mov FGCAn, r1 ; r1: TA Counters of 011A : 1100_0110_0001_1000_0000_0001 252: 253: mov 0x20, r2 011B : 1100_0110_0000_0100_0000_0010 254: add r2, r1, r2 ; r2: TB Counters of 011C : 1000_0010_0010_0000_0010_0010 255: 256: cclp: add r1, r0, r8 ; r8: current TA cou 011D : 1000_0010_0001_0000_0000_1000 257: add r2, r0, r9 ; r9: current TB cou 011E : 1000_0010_0010_0000_0000_1001 258: 259: jmpr cc_busy, 0 011F : 0000_0100_0010_0011_1111_0111 260: lgio 0, r8 0120 : 1110_1000_0000_0001_0000_0000 261: jmpr cc_busy, 0 0121 : 0000_0100_0010_0100_0011_0111 262: lpio 0x300, r10 ; r10: current TA co 0122 : 1110_0110_0110_0000_0000_1010 263: 264: jmpr cc_busy, 0 0123 : 0000_0100_0010_0100_0111_0111 265: lgio 0, r9 0124 : 1110_1000_0000_0001_0010_0000 266: jmpr cc_busy, 0 0125 : 0000_0100_0010_0100_1011_0111 267: lpio 0x300, r11 ; r11: current TB co 0126 : 1110_0110_0110_0000_0000_1011 268: 269: cmp r4, r10 ; check TA entry 0127 : 1000_1000_0100_0001_0100_0000 270: jmp cc_eq, caok 0128 : 0000_0100_0000_0000_0001_0001 271: add r6, c1, r6 0129 : 1000_0010_0110_0110_0010_0110 272: 273: caok: cmp r5, r11 ; check TB entry 012A : 1000_1000_0101_0001_0110_0000 274: jmp cc_eq, cbok 012B : 0000_0100_0000_0000_0001_0001 275: add r7, c1, r7 012C : 1000_0010_0111_0110_0010_0111 276: 277: cbok: add r0, c1, r0 012D : 1000_0010_0000_0110_0010_0000 278: cmp r0, 21 012E : 1100_1000_0000_0000_0001_0101 279: jmp cc_ltu, cclp ; complete loop 012F : 0000_0100_0000_0000_0001_0000 280: nop 0130 : 0000_0000_0000_0000_0000_0000 281: 282: add r6, TA_ERROR_CTR, r6 ; update error count 0131 : 1000_0010_0110_0111_0000_0110 283: add r7, TB_ERROR_CTR, r7 0132 : 1000_0010_0111_0111_0010_0111 284: 285: jmpr cc_busy, 0 0133 : 0000_0100_0010_0110_0111_0111 286: sgio r6, TA_ERROR_ADR 0134 : 0010_1000_0110_1100_0000_0000 287: 288: jmpr cc_busy, 0 0135 : 0000_0100_0010_0110_1011_0111 289: sgio r7, TB_ERROR_ADR 0136 : 0010_1000_0111_1100_0000_0001 290: 291: 292: 293: ;########################################### 294: ;# 295: ;# increase counters 296: ;# 297: ;########################################### 298: 299: 300: #ifdef cpu3 301: 302: mov 30, r1 303: add r1, OFFSET_CTR, r1 304: 305: jmpr cc_busy, 0 306: sgio r1, OFFSET_ADR 307: 308: #else 309: 310: nop 0137 : 0000_0000_0000_0000_0000_0000 311: nop 0138 : 0000_0000_0000_0000_0000_0000 312: 313: nop 0139 : 0000_0000_0000_0000_0000_0000 314: nop 013A : 0000_0000_0000_0000_0000_0000 315: 316: #endif 317: 318: jmpr cc_busy, 0 013B : 0000_0100_0010_0111_0111_0111 319: 320: 321: 322: ;########################################### 323: ;# 324: ;# write next test pattern into event b 325: ;# 326: ;########################################### 327: 328: 329: #ifdef cpu3 330: 331: iext EBW 332: mov EBW, r0 333: mov 33, r1 334: add r0, r1, r0 ; r0: event buffer o 335: 336: mov 0, r1 ; r1: channel number 337: mov 0, r2 ; r2: time bin numbe 338: 339: loopEB: 340: add r2, OFFSET_CTR, r4 341: shl 7, r1, r3 342: add r0, r3, r3 343: add r2, r3, r3 344: 345: jmpr cc_busy, 0 ; r3: single event b 346: sgio r4, r3 ; r4: data to write 347: 348: mov 10, r5 349: 350: waitD: sub r5, c1, r5 351: jmp cc_gts, waitD 352: 353: add r1, c1, r1 354: cmp r1, 21 355: jmp cc_ltu, loopEB 356: 357: mov 0, r1 358: add r2, c1, r2 359: cmp r2, 30 360: jmp cc_ltu, loopEB 361: nop 362: endEB: mov 1, CPU_SYNC 363: 364: #else 365: 366: nop 013C : 0000_0000_0000_0000_0000_0000 367: 368: #endif 369: 370: 371: 372: ;########################################### 373: ;# 374: ;# wait for data writing completion 375: ;# 376: ;########################################### 377: 378: 379: wsy: mov CPU_SYNC, r0 013D : 1100_0010_0000_0010_0010_0000 380: cmp r0, 1 013E : 1100_1000_0000_0000_0000_0001 381: jmp cc_neq, wsy 013F : 0000_0100_0000_0000_0000_0001 382: 383: 384: ;########################################### 385: ;# 386: ;# copy lower indicator words 387: ;# 388: ;########################################### 389: 390: 391: #ifdef cpu0 392: mov 0x7B8, r15 0140 : 1100_0110_1111_0111_0000_1111 393: #endif 394: 395: #ifdef cpu1 396: mov 0x7CC, r15 397: #endif 398: 399: #ifdef cpu2 400: mov 0x7E0, r15 401: #endif 402: 403: #ifdef cpu3 404: mov 0x7F4, r15 405: #endif 406: 407: lpio EBI0, r0 0141 : 1110_0111_0011_0000_0000_0000 408: lpio EBI0, r0 0142 : 1110_0111_0011_0000_0000_0000 409: sra+ r0 0143 : 0011_1000_0000_0000_0000_0000 410: 411: lpio EBI2, r0 0144 : 1110_0111_0011_0000_0100_0000 412: lpio EBI2, r0 0145 : 1110_0111_0011_0000_0100_0000 413: sra+ r0 0146 : 0011_1000_0000_0000_0000_0000 414: 415: lpio EBI4, r0 0147 : 1110_0111_0011_0000_1000_0000 416: lpio EBI4, r0 0148 : 1110_0111_0011_0000_1000_0000 417: sra+ r0 0149 : 0011_1000_0000_0000_0000_0000 418: 419: lpio EBI6, r0 014A : 1110_0111_0011_0000_1100_0000 420: lpio EBI6, r0 014B : 1110_0111_0011_0000_1100_0000 421: sra+ r0 014C : 0011_1000_0000_0000_0000_0000 422: 423: lpio EBI8, r0 014D : 1110_0111_0011_0001_0000_0000 424: lpio EBI8, r0 014E : 1110_0111_0011_0001_0000_0000 425: sra+ r0 014F : 0011_1000_0000_0000_0000_0000 426: 427: #ifdef cpu3 428: lpio EBIA, r0 429: lpio EBIA, r0 430: sra+ r0 431: #else 432: nop 0150 : 0000_0000_0000_0000_0000_0000 433: nop 0151 : 0000_0000_0000_0000_0000_0000 434: nop 0152 : 0000_0000_0000_0000_0000_0000 435: #endif 436: 437: 438: ;########################################### 439: ;# 440: ;# DMEM address to copy event buffer da 441: ;# beware: byte address = 4 * word addr 442: ;# 443: ;########################################### 444: 445: #ifdef cpu0 446: mov 0x080, r15 0153 : 1100_0110_0001_0000_0000_1111 447: #endif 448: 449: #ifdef cpu1 450: mov 0x238, r15 451: #endif 452: 453: #ifdef cpu2 454: mov 0x3F0, r15 455: #endif 456: 457: #ifdef cpu3 458: mov 0x5A8, r15 459: #endif 460: 461: ;########################################### 462: ;# 463: ;# channel check bits, absolute channel 464: ;# 465: ;########################################### 466: 467: #ifdef cpu0 468: mov 3, r3 0154 : 1100_0110_0000_0000_0110_0011 469: #endif 470: 471: #ifdef cpu1 472: mov 2, r3 473: #endif 474: 475: #ifdef cpu2 476: mov 3, r3 477: #endif 478: 479: #ifdef cpu3 480: mov 2, r3 481: #endif 482: 483: ;########################################### 484: ;# 485: ;# copy event buffer data of CPU's chan 486: ;# 487: ;########################################### 488: 489: mov EBR0, r14 0155 : 1100_0111_0000_0000_0000_1110 490: mov 66, r5 0156 : 1100_0110_0000_1000_0100_0101 491: 492: loop0: lpio+ r0 0157 : 1110_1110_0000_0000_0000_0000 493: lpio+ r0 0158 : 1110_1110_0000_0000_0000_0000 494: lpio+ r1 0159 : 1110_1110_0000_0000_0000_0001 495: lpio r14, r2 015A : 1110_0010_0000_0001_1100_0010 496: 497: shl 10, r2, r2 015B : 1011_0010_1010_0000_0100_0010 498: or r1, r2, r2 015C : 1010_1010_0001_0000_0100_0010 499: shl 10, r2, r2 015D : 1011_0010_1010_0000_0100_0010 500: or r0, r2, r2 015E : 1010_1010_0000_0000_0100_0010 501: shl 2, r2, r2 015F : 1011_0010_0010_0000_0100_0010 502: or r3, r2, r2 0160 : 1010_1010_0011_0000_0100_0010 503: 504: sra+ r2 0161 : 0011_1000_0010_0000_0000_0000 505: 506: sub r5, c3, r5 0162 : 1000_1010_0101_0110_0110_0101 507: jmp cc_gtu, loop0 0163 : 0000_0100_0000_0000_0000_1000 508: 509: ;########################################### 510: ;# 511: ;# copy event buffer data of CPU's chan 512: ;# 513: ;########################################### 514: 515: mov EBR1, r14 0164 : 1100_0111_0000_1000_0000_1110 516: mov 66, r5 0165 : 1100_0110_0000_1000_0100_0101 517: xor r3, c1, r3 0166 : 1010_0010_0011_0110_0010_0011 518: 519: loop1: lpio+ r0 0167 : 1110_1110_0000_0000_0000_0000 520: lpio+ r0 0168 : 1110_1110_0000_0000_0000_0000 521: lpio+ r1 0169 : 1110_1110_0000_0000_0000_0001 522: lpio r14, r2 016A : 1110_0010_0000_0001_1100_0010 523: 524: shl 10, r2, r2 016B : 1011_0010_1010_0000_0100_0010 525: or r1, r2, r2 016C : 1010_1010_0001_0000_0100_0010 526: shl 10, r2, r2 016D : 1011_0010_1010_0000_0100_0010 527: or r0, r2, r2 016E : 1010_1010_0000_0000_0100_0010 528: shl 2, r2, r2 016F : 1011_0010_0010_0000_0100_0010 529: or r3, r2, r2 0170 : 1010_1010_0011_0000_0100_0010 530: 531: sra+ r2 0171 : 0011_1000_0010_0000_0000_0000 532: 533: sub r5, c3, r5 0172 : 1000_1010_0101_0110_0110_0101 534: jmp cc_gtu, loop1 0173 : 0000_0100_0000_0000_0000_1000 535: 536: ;########################################### 537: ;# 538: ;# copy event buffer data of CPU's chan 539: ;# 540: ;########################################### 541: 542: mov EBR2, r14 0174 : 1100_0111_0001_0000_0000_1110 543: mov 66, r5 0175 : 1100_0110_0000_1000_0100_0101 544: xor r3, c1, r3 0176 : 1010_0010_0011_0110_0010_0011 545: 546: loop2: lpio+ r0 0177 : 1110_1110_0000_0000_0000_0000 547: lpio+ r0 0178 : 1110_1110_0000_0000_0000_0000 548: lpio+ r1 0179 : 1110_1110_0000_0000_0000_0001 549: lpio r14, r2 017A : 1110_0010_0000_0001_1100_0010 550: 551: shl 10, r2, r2 017B : 1011_0010_1010_0000_0100_0010 552: or r1, r2, r2 017C : 1010_1010_0001_0000_0100_0010 553: shl 10, r2, r2 017D : 1011_0010_1010_0000_0100_0010 554: or r0, r2, r2 017E : 1010_1010_0000_0000_0100_0010 555: shl 2, r2, r2 017F : 1011_0010_0010_0000_0100_0010 556: or r3, r2, r2 0180 : 1010_1010_0011_0000_0100_0010 557: 558: sra+ r2 0181 : 0011_1000_0010_0000_0000_0000 559: 560: sub r5, c3, r5 0182 : 1000_1010_0101_0110_0110_0101 561: jmp cc_gtu, loop2 0183 : 0000_0100_0000_0000_0000_1000 562: 563: ;########################################### 564: ;# 565: ;# copy event buffer data of CPU's chan 566: ;# 567: ;########################################### 568: 569: mov EBR3, r14 0184 : 1100_0111_0001_1000_0000_1110 570: mov 66, r5 0185 : 1100_0110_0000_1000_0100_0101 571: xor r3, c1, r3 0186 : 1010_0010_0011_0110_0010_0011 572: 573: loop3: lpio+ r0 0187 : 1110_1110_0000_0000_0000_0000 574: lpio+ r0 0188 : 1110_1110_0000_0000_0000_0000 575: lpio+ r1 0189 : 1110_1110_0000_0000_0000_0001 576: lpio r14, r2 018A : 1110_0010_0000_0001_1100_0010 577: 578: shl 10, r2, r2 018B : 1011_0010_1010_0000_0100_0010 579: or r1, r2, r2 018C : 1010_1010_0001_0000_0100_0010 580: shl 10, r2, r2 018D : 1011_0010_1010_0000_0100_0010 581: or r0, r2, r2 018E : 1010_1010_0000_0000_0100_0010 582: shl 2, r2, r2 018F : 1011_0010_0010_0000_0100_0010 583: or r3, r2, r2 0190 : 1010_1010_0011_0000_0100_0010 584: 585: sra+ r2 0191 : 0011_1000_0010_0000_0000_0000 586: 587: sub r5, c3, r5 0192 : 1000_1010_0101_0110_0110_0101 588: jmp cc_gtu, loop3 0193 : 0000_0100_0000_0000_0000_1000 589: 590: ;########################################### 591: ;# 592: ;# copy event buffer data of CPU's chan 593: ;# 594: ;########################################### 595: 596: mov EBR4, r14 0194 : 1100_0111_0010_0000_0000_1110 597: mov 66, r5 0195 : 1100_0110_0000_1000_0100_0101 598: xor r3, c1, r3 0196 : 1010_0010_0011_0110_0010_0011 599: 600: loop4: lpio+ r0 0197 : 1110_1110_0000_0000_0000_0000 601: lpio+ r0 0198 : 1110_1110_0000_0000_0000_0000 602: lpio+ r1 0199 : 1110_1110_0000_0000_0000_0001 603: lpio r14, r2 019A : 1110_0010_0000_0001_1100_0010 604: 605: shl 10, r2, r2 019B : 1011_0010_1010_0000_0100_0010 606: or r1, r2, r2 019C : 1010_1010_0001_0000_0100_0010 607: shl 10, r2, r2 019D : 1011_0010_1010_0000_0100_0010 608: or r0, r2, r2 019E : 1010_1010_0000_0000_0100_0010 609: shl 2, r2, r2 019F : 1011_0010_0010_0000_0100_0010 610: or r3, r2, r2 01A0 : 1010_1010_0011_0000_0100_0010 611: 612: sra+ r2 01A1 : 0011_1000_0010_0000_0000_0000 613: 614: sub r5, c3, r5 01A2 : 1000_1010_0101_0110_0110_0101 615: jmp cc_gtu, loop4 01A3 : 0000_0100_0000_0000_0000_1000 616: 617: ;########################################### 618: ;# 619: ;# copy event buffer data of CPU's chan 620: ;# 621: ;########################################### 622: 623: #ifdef cpu3 624: mov EBR5, r14 625: mov 66, r5 626: xor r3, c1, r3 627: 628: loop5: lpio+ r0 629: lpio+ r0 630: lpio+ r1 631: lpio r14, r2 632: 633: shl 10, r2, r2 634: or r1, r2, r2 635: shl 10, r2, r2 636: or r0, r2, r2 637: shl 2, r2, r2 638: or r3, r2, r2 639: 640: sra+ r2 641: 642: sub r5, c3, r5 643: jmp cc_gtu, loop5 644: #else 645: nop 01A4 : 0000_0000_0000_0000_0000_0000 646: nop 01A5 : 0000_0000_0000_0000_0000_0000 647: nop 01A6 : 0000_0000_0000_0000_0000_0000 648: nop 01A7 : 0000_0000_0000_0000_0000_0000 649: nop 01A8 : 0000_0000_0000_0000_0000_0000 650: nop 01A9 : 0000_0000_0000_0000_0000_0000 651: nop 01AA : 0000_0000_0000_0000_0000_0000 652: nop 01AB : 0000_0000_0000_0000_0000_0000 653: nop 01AC : 0000_0000_0000_0000_0000_0000 654: nop 01AD : 0000_0000_0000_0000_0000_0000 655: nop 01AE : 0000_0000_0000_0000_0000_0000 656: nop 01AF : 0000_0000_0000_0000_0000_0000 657: nop 01B0 : 0000_0000_0000_0000_0000_0000 658: nop 01B1 : 0000_0000_0000_0000_0000_0000 659: nop 01B2 : 0000_0000_0000_0000_0000_0000 660: nop 01B3 : 0000_0000_0000_0000_0000_0000 661: #endif 662: 663: 664: ;########################################### 665: ;# 666: ;# end current state, goto clear state 667: ;# 668: ;########################################### 669: 670: 671: #ifdef cpu3 672: 673: mov 0, r0 674: jmpr cc_busy, 0 675: sgio r0, EBSIM_FAST 676: 677: mov CMD_CLEAR, r0 678: jmpr cc_busy, 0 679: sgio r0, SMCMD 680: 681: #else 682: 683: nop 01B4 : 0000_0000_0000_0000_0000_0000 684: nop 01B5 : 0000_0000_0000_0000_0000_0000 685: nop 01B6 : 0000_0000_0000_0000_0000_0000 686: 687: nop 01B7 : 0000_0000_0000_0000_0000_0000 688: nop 01B8 : 0000_0000_0000_0000_0000_0000 689: nop 01B9 : 0000_0000_0000_0000_0000_0000 690: 691: #endif 692: 693: 694: 695: ;########################################### 696: ;# 697: ;# switch off own clock after transfer 698: ;# 699: ;########################################### 700: 701: 702: clkoff: mov 0, r0 01BA : 1100_0110_0000_0000_0000_0000 703: jmpr cc_busy, 0 01BB : 0000_0100_0011_0111_0111_0111 704: 705: #ifdef cpu0 706: sgio r0, CPU0SS 01BC : 0010_1000_0000_1010_0010_0001 707: #endif 708: 709: #ifdef cpu1 710: sgio r0, CPU1SS 711: #endif 712: 713: #ifdef cpu2 714: sgio r0, CPU2SS 715: #endif 716: 717: #ifdef cpu3 718: sgio r0, CPU3SS 719: #endif 720: 721: jmp cc_uncond, clkoff 01BD : 0000_0100_0000_0000_0000_1111 722: nop 01BE : 0000_0000_0000_0000_0000_0000 723: 724: 725: 726: ;################################################### 727: ;# 728: ;# 0x0300: Interrrupt Raw Data Readout Jump Add 729: ;# 730: ;# Nothing to be done here. 731: ;# 732: ;################################################### 733: 734: 735: org 0x300 736: 737: jmp cc_uncond, clkoff 0300 : 0000_0100_0000_0000_0000_1111 738: nop 0301 : 0000_0000_0000_0000_0000_0000 739: 740: 741: 742: 743: 744: 745: 746: 747: 748: 749: 750: 751: 752: 753: 754: 755: 756: 757: Source file read, 0 error(s), 0 warning(s).