Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.7, Jul 2008 SVN Revision 2158, SVN Date 2008-07-17 Please send any comments to: angelov@kip.uni-heidelberg.de 11:43:55 / 24 Nov 2008 Source code file: SignalProcessing.asm Memory initialisation file: Log file: ../work/cpu2.log Program memory size in words: 4096 Default constants, read from /usr/share/trap/asm_mimd.inc 1 CPU2 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 107 ASM_SVN_REV = 2158 1: ;########################################################### 2: ;# 3: ;# Test Program for nonlinearity filter. 4: ;# 5: ;# Input data is taken from event buffer and stored bac 6: ;# another memory region. 7: ;# 8: ;# Marcus Gutfleisch 9: ;# Ruprecht-Karls-Universität Heidelberg, Kirchhoff-Ins 10: ;# 11: ;# Heidelberg, 18.03.2005 12: ;# 13: ;########################################################### 14: 15: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt tttt tttt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt tttt tttt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt tttt tttt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snme eeee ddd 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc cccc cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- ---- --St oam 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- ---- --St oam 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- ---- --St oam 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- ---- --St oam 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- ---- --St oam 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- ---- --St oam 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- ---- --St oam 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- ---- --St oam 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- ---- --St oam 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- ---- --St oam 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- ---- --St oam 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- ---- --St oam 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- ---- ---- --- 30: 31: #def CTGDINI=0x0B80; dddd dddd dddd dddd dddd dddd dddd dddd 32: #def CTGCTRL=0x0B81; ---- ---- ---- ---- ---S idce essb bbbb 33: #def CTGDOUT=0x0B82; DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 34: #def CTPDINI=0x0200; dddd dddd dddd dddd dddd dddd dddd dddd 35: #def CTPCTRL=0x0201; ---- ---- ---- ---- ---S idce essb bbbb 36: #def CTPDOUT=0x0202; DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 37: 38: #def PASADEL=0x3158; ---- ---- ---- ---- ---- ---- aaaa aaa 39: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- ---- --aa aaa 40: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- ---- --aa aaa 41: #def PASADAC=0x315B; ---- ---- ---- ---- ---- ---- aaaa aaa 42: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaaa aaaa aaa 43: #def PASASTL=0x315D; ---- ---- ---- ---- ---- ---- aaaa aaa 44: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- ---- ---- --- 45: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- ---- ---- --- 46: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaaa aaaa aaa 47: #def ADCINB=0x3051; ---- ---- ---- ---- ---- ---- ---- --m 48: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- ---- ---d ddd 49: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssbz hhhe app 50: #def ADCTST=0x3054; ---- ---- ---- ---- ---- ---- ---- --t 51: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- ---- ---- --- 52: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- ---- ---- --- 53: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- ---- ---- --- 54: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- ---- ---- -aa 55: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- ---- -ret aii 56: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaaa aaaa aaa 57: #def SADCEC=0x3166; ---- ---- ---- ---- ---- ---- -daa ate 58: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --AA AAAA AAA 59: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --AA AAAA AAA 60: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --AA AAAA AAA 61: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --AA AAAA AAA 62: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --AA AAAA AAA 63: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --AA AAAA AAA 64: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --AA AAAA AAA 65: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --AA AAAA AAA 66: #def SADCMC=0x3170; ---- ---- ---- ---- ---- ---- aaaa aaa 67: #def SADCOC=0x3171; ---- ---- ---- ---- ---- ---- aaaa aaa 68: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd cccc bbbb aaa 69: #def SADCTC=0x3173; ---- ---- ---- ---- ---- ---- ---- -aa 70: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -eaa aaaa aaa 71: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- ---- ---- -ee 72: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- ---- ---- -oo 73: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- ---- ---- -ii 74: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAAA AAAA AAA 75: #def TPPT0=0x3000; ---- ---- ---- ---- ---- ---- -ddd ddd 76: #def TPPAE=0x3004; ---- ---- ---- ---- ---- ---- -ddd ddd 77: #def TPPGR=0x3003; ---- ---- ---- ---- ---- ---- -ddd ddd 78: #def FLBY=0x3018; ---- ---- ---- ---- ---- ---- ---- --- 79: #def FLL=0x3100; ---- ---- ---- ---- ---- ---- --dd ddd 80: #def FPBY=0x3019; ---- ---- ---- ---- ---- ---- ---- --- 81: #def FPTC=0x3020; ---- ---- ---- ---- ---- ---- ---- --d 82: #def FPNP=0x3021; ---- ---- ---- ---- ---- ---d dddd ddd 83: #def FPCL=0x3022; ---- ---- ---- ---- ---- ---- ---- --- 84: #def FPA=0x3060; --dd dddd dddd dddd dddd dddd dddd ddd 85: #def FGBY=0x301A; ---- ---- ---- ---- ---- ---- ---- --- 86: #def FGFn=0x3080; ---- ---- ---- ---- ---- ---d dddd ddd 87: #def FGAn=0x30A0; ---- ---- ---- ---- ---- ---- --dd ddd 88: #def FGTA=0x3028; ---- ---- ---- ---- ---- dddd dddd ddd 89: #def FGTB=0x3029; ---- ---- ---- ---- ---- dddd dddd ddd 90: #def FGCL=0x302A; ---- ---- ---- ---- ---- ---- ---- --- 91: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd dddd dddd ddd 92: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd dddd dddd ddd 93: #def FTBY=0x301B; ---- ---- ---- ---- ---- ---- ---- --- 94: #def FTAL=0x3030; ---- ---- ---- ---- ---- --dd dddd ddd 95: #def FTLL=0x3031; ---- ---- ---- ---- ---- --dd dddd ddd 96: #def FTLS=0x3032; ---- ---- ---- ---- ---- --dd dddd ddd 97: #def FCBY=0x301C; ---- ---- ---- ---- ---- ---- ---- --- 98: #def FCWn=0x3038; ---- ---- ---- ---- ---- ---- dddd ddd 99: #def TPFS=0x3001; ---- ---- ---- ---- ---- ---- -ddd ddd 100: #def TPFE=0x3002; ---- ---- ---- ---- ---- ---- -ddd ddd 101: #def TPQS0=0x3005; ---- ---- ---- ---- ---- ---- -ddd ddd 102: #def TPQE0=0x3006; ---- ---- ---- ---- ---- ---- -ddd ddd 103: #def TPQS1=0x3007; ---- ---- ---- ---- ---- ---- -ddd ddd 104: #def TPQE1=0x3008; ---- ---- ---- ---- ---- ---- -ddd ddd 105: #def TPHT=0x3041; ---- ---- ---- ---- --dd dddd dddd ddd 106: #def TPVBY=0x3043; ---- ---- ---- ---- ---- ---- ---- --- 107: #def TPVT=0x3042; ---- ---- ---- ---- ---- ---- --dd ddd 108: #def TPFP=0x3040; ---- ---- ---- ---- ---- ---- --dd ddd 109: #def TPL=0x3180; ---- ---- ---- ---- ---- ---- ---d ddd 110: #def TPCL=0x3045; ---- ---- ---- ---- ---- ---- ---d ddd 111: #def TPCT=0x3044; ---- ---- ---- ---- ---- ---- ---d ddd 112: #def TPD=0x3047; ---- ---- ---- ---- ---- ---- ---- ddd 113: #def TPH=0x3140; ---- ---- ---- ---- ---- ---- ---d ddd 114: #def TPCBY=0x3046; ---- ---- ---- ---- ---- ---- ---- --- 115: #def TPCI0=0x3048; ---- ---- ---- ---- ---- ---- ---d ddd 116: #def TPCI1=0x3049; ---- ---- ---- ---- ---- ---- ---d ddd 117: #def TPCI2=0x304A; ---- ---- ---- ---- ---- ---- ---d ddd 118: #def TPCI3=0x304B; ---- ---- ---- ---- ---- ---- ---d ddd 119: #def EBD=0x3009; ---- ---- ---- ---- ---- ---- ---- -dd 120: #def EBSF=0x300C; ---- ---- ---- ---- ---- ---- ---- --- 121: #def EBAQA=0x300A; ---- ---- ---- ---- ---- ---- -ddd ddd 122: #def EBSIM=0x300D; ---- ---- ---- ---- ---- ---- ---- --- 123: #def EBSIA=0x300B; ---- ---- ---- ---- ---- ---- -ddd ddd 124: #def EBR=0x0800; ---- ---- ---- ---- ---- -pdd dddd ddd 125: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pdd dddd ddd 126: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pdd dddd ddd 127: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pdd dddd ddd 128: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pdd dddd ddd 129: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pdd dddd ddd 130: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pdd dddd ddd 131: #def EBW=0x2000; ---- ---- ---- ---- ---- --dd dddd ddd 132: #def EBPP=0x300E; ---- ---- ---- ---- ---- ---- ---- --- 133: #def EBPC=0x300F; ---- ---- ---- ---- ---- ---- ---- --- 134: #def EBP0=0x3010; ---- ---- ---- ---- ---- ---d dddd ddd 135: #def EBP1=0x3011; ---- ---- ---- ---- ---- ---d dddd ddd 136: #def EBP2=0x3012; ---- ---- ---- ---- ---- ---d dddd ddd 137: #def EBP3=0x3013; ---- ---- ---- ---- ---- ---d dddd ddd 138: #def EBIS=0x3014; ---- ---- ---- ---- ---- --dd dddd ddd 139: #def EBIT=0x3015; ---- ---- ---- ---- ---- dddd dddd ddd 140: #def EBIL=0x3016; ---- ---- ---- ---- ---- ---- dddd ddd 141: #def EBIN=0x3017; ---- ---- ---- ---- ---- ---- ---- --- 142: #def EBI=0x0980; dddd dddd dddd dddd dddd dddd dddd ddd 143: #def EBI0=0x0980; dddd dddd dddd dddd dddd dddd dddd dd 144: #def EBI1=0x0981; dddd dddd dddd dddd dddd dddd dddd dd 145: #def EBI2=0x0982; dddd dddd dddd dddd dddd dddd dddd dd 146: #def EBI3=0x0983; dddd dddd dddd dddd dddd dddd dddd dd 147: #def EBI4=0x0984; dddd dddd dddd dddd dddd dddd dddd dd 148: #def EBI5=0x0985; dddd dddd dddd dddd dddd dddd dddd dd 149: #def EBI6=0x0986; dddd dddd dddd dddd dddd dddd dddd dd 150: #def EBI7=0x0987; dddd dddd dddd dddd dddd dddd dddd dd 151: #def EBI8=0x0988; dddd dddd dddd dddd dddd dddd dddd dd 152: #def EBI9=0x0989; dddd dddd dddd dddd dddd dddd dddd dd 153: #def EBIA=0x098A; dddd dddd dddd dddd dddd dddd dddd dd 154: #def EBIB=0x098B; dddd dddd dddd dddd dddd dddd dddd dd 155: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- ---- ---- wwr 156: #def MEMRW=0xD000; ---- ---- ---- ---- ---- ---- -www wrr 157: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- ---b dddd iii 158: #def DMDELA=0xD002; ---- ---- ---- ---- ---- ---- ---- aaa 159: #def DMDELS=0xD003; ---- ---- ---- ---- ---- ---- ---- sss 160: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 161: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 162: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 163: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 164: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 165: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 166: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 167: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNN 168: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaaa aaaa aaa 169: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaaa aaaa aaa 170: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaaa aaaa aaa 171: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaaa aaaa aaa 172: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmmm mmmm mmm 173: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmmm mmmm mmm 174: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmmm mmmm mmm 175: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmmm mmmm mmm 176: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmmm mmmm mmm 177: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmmm mmmm mmm 178: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmmm mmmm mmm 179: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmmm mmmm mmm 180: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmmm mmmm mmm 181: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmmm mmmm mmm 182: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmmm mmmm mmm 183: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmmm mmmm mmm 184: #def NMOD=0x0D40; ---- ---- ---- ---- ---- ---- ---i cmm 185: #def NTRO=0x0D43; ---- ---- ---- --ii iddd cccb bbaa aff 186: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt tttt tttt ttt 187: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbbb aaaa aaa 188: #def NRRO=0x0D44; ---- ---- ---- --ii iddd cccb bbaa aff 189: #def NTP=0x0D46; pppp pppp pppp pppp pppp pppp pppp ppp 190: #def NP0=0x0D48; ---- ---- ---- ---- ---- -ppp pfff fec 191: #def NP1=0x0D49; ---- ---- ---- ---- ---- -ppp pfff fec 192: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -ppp pfff fec 193: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -ppp pfff fec 194: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLLL CCCC CCC 195: #def NED=0x0D42; ---- ---- ---- ---- orpp ppff ffcc css 196: #def NDLY=0x0D41; --jj jiii hhhg ggff feee dddc ccbb baa 197: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhhh llll lll 198: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DSS EHLZ YXW 199: #def NLE=0x00C2; ---- ---- ---- ---- ---- ---- EEEE EEE 200: #def NFE=0x0DC1; ---- ---- ---- ---- ---- ---- ---- DCB 201: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- ---- ---- --- 202: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- ---- ---S SSS 203: #def NITM0=0x0A08; ---- ---- ---- ---- --tt tttt tttt ttt 204: #def NITM1=0x0A09; ---- ---- ---- ---- --tt tttt tttt ttt 205: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt tttt tttt ttt 206: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt tttt tttt ttt 207: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd dddd dddd ddd 208: #def SMON=0x0A06; ---- ---- ---- ---- ---- dddd dddd ddd 209: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- dddd dddd ddd 210: #def NODP=0x0000; dddd dddd dddd dddd dddd dddd dddd ddd 211: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- ---- ---- 212: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- ---- ---- 213: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- ---- ---- 214: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- ---- ---- 215: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- ---- ---- 216: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- ---- ---- 217: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- ---- ---- 218: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- ---- ---- 219: #def GBUSR0=0x0300; -- readonly 220: #def GBUSR1=0x0301; -- readonly *** End of include file /usr/share/trap//conf_va.inc *** Include file ../../assembler.inc 1: ;#define MCM=1; 2: ;#define WAFER=1; 3: #define ROB=1; *** End of include file ../../assembler.inc 18: 19: 20: 21: ;################################################### 22: ;# 23: ;# defines 24: ;# 25: ;################################################### 26: 27: 28: #def EBSIM_FAST = g0 29: #def CPU_SYNC = g1 30: 31: 32: #def ERROR_CTR = c8 33: #def OFFSET_CTR = c12 34: #def ADD_CTR = c13 35: 36: #def OFFSET_ADR = 0xC04 37: #def ADD_ADR = 0xC05 38: 39: #ifdef cpu0 40: #def ERROR_ADR = 0xC00 41: #endif 42: #ifdef cpu1 43: #def ERROR_ADR = 0xC08 44: #endif 45: #ifdef cpu2 46: #def ERROR_ADR = 0xC10 47: #endif 48: #ifdef cpu3 49: #def ERROR_ADR = 0xC18 50: #endif 51: 52: 53: 54: ;################################################### 55: ;# 56: ;# 0x0000: Infinite Loop at Instruction Memory 57: ;# 58: ;################################################### 59: 60: 61: org 0x0000 62: 63: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 64: nop 0001 : 0000_0000_0000_0000_0000_0000 65: 66: 67: 68: ;################################################### 69: ;# 70: ;# 0x0010: Interrrupt Clear Jump Address 71: ;# 72: ;# CPU0: switch off all NI LVDS cells 73: ;# switch off NI clock 74: ;# switch off preprocessor cloc 75: ;# switch on filter clock 76: ;# 77: ;# CPU1: end clear state, arm state m 78: ;# 79: ;# CPU2: get tracklet end signature ( 80: ;# 81: ;# CPU3: get data end signature (???) 82: ;# 83: ;################################################### 84: 85: 86: org 0x0010 87: 88: mov 0, r12 0010 : 1100_0110_0000_0000_0000_1100 89: mov 4, r13 0011 : 1100_0110_0000_0000_1000_1101 90: 91: #ifdef cpu0 92: 93: iext EBSIM 94: mov EBSIM, EBSIM_FAST 95: mov 0, CPU_SYNC 96: 97: iext b1111_0101_0000_0000_0010_0000 98: mov b1111_0101_0000_0000_0010_0000, r0 99: jmpr cc_busy, 0 100: sgio r0, SMOFFON 101: 102: mov CMD_EXT_CLR, r0 103: mov CMD_PRETRIGG, r1 104: mov 1054, r2 105: jmpr cc_busy, 0 106: cmp r2, OFFSET_CTR 107: jmp cc_leu, end_lp 108: sgio r0, SMCMD 109: 110: nop 111: nop 112: sgio r1, SMCMD 113: 114: #else 115: 116: #ifdef MCM 117: #ifdef cpu1 118: mov 0, r0 119: iext SEBDOU 120: sgio r0, SEBDOU 121: #else 122: nop 123: nop 124: nop 125: #endif 126: #endif 127: 128: nop 0012 : 0000_0000_0000_0000_0000_0000 129: nop 0013 : 0000_0000_0000_0000_0000_0000 130: nop 0014 : 0000_0000_0000_0000_0000_0000 131: nop 0015 : 0000_0000_0000_0000_0000_0000 132: 133: nop 0016 : 0000_0000_0000_0000_0000_0000 134: nop 0017 : 0000_0000_0000_0000_0000_0000 135: nop 0018 : 0000_0000_0000_0000_0000_0000 136: nop 0019 : 0000_0000_0000_0000_0000_0000 137: nop 001A : 0000_0000_0000_0000_0000_0000 138: 139: nop 001B : 0000_0000_0000_0000_0000_0000 140: nop 001C : 0000_0000_0000_0000_0000_0000 141: nop 001D : 0000_0000_0000_0000_0000_0000 142: 143: #endif 144: 145: end_cl: jmpr cc_uncond, 0 001E : 0000_0100_0000_0011_1100_1111 146: nop 001F : 0000_0000_0000_0000_0000_0000 147: 148: end_lp: 149: #ifdef MCM 150: mov 5, r0 151: iext SEBDEN 152: sgio r0, SEBDEN 153: jmpr cc_busy, 0 154: #endif 155: 156: mov CMD_LP, r0 0020 : 1100_0110_0000_0010_0100_0000 157: sgio r0, SMCMD 0021 : 0010_1000_0000_1010_0000_0100 158: 159: jmpr cc_uncond, 0 0022 : 0000_0100_0000_0100_0100_1111 160: nop 0023 : 0000_0000_0000_0000_0000_0000 161: 162: 163: 164: ;################################################### 165: ;# 166: ;# 0x0100: Interrrupt Tracklet Processing Jump 167: ;# 168: ;# send delayed tracklet end marker 169: ;# 170: ;################################################### 171: 172: 173: org 0x0100 174: 175: #ifdef cpu0 176: nop 177: nop 178: nop 179: nop 180: #endif 181: 182: #ifdef cpu1 183: nop 184: nop 185: nop 186: nop 187: #endif 188: 189: #ifdef cpu2 190: nop 0100 : 0000_0000_0000_0000_0000_0000 191: nop 0101 : 0000_0000_0000_0000_0000_0000 192: nop 0102 : 0000_0000_0000_0000_0000_0000 193: nop 0103 : 0000_0000_0000_0000_0000_0000 194: #endif 195: 196: #ifdef cpu3 197: mov 1, r0 198: jmpr cc_busy, 0 199: sgio r0, EBSIM_FAST 200: nop 201: #endif 202: 203: 204: 205: ;########################################### 206: ;# 207: ;# check result 208: ;# 209: ;########################################### 210: 211: 212: mov EBR0, r8 ; load channel speci 0104 : 1100_0111_0000_0000_0000_1000 213: add r8, c1, r8 ; add +1 due to shif 0105 : 1000_0010_1000_0110_0010_1000 214: mov EBR1, r9 0106 : 1100_0111_0000_1000_0000_1001 215: add r9, c1, r9 0107 : 1000_0010_1001_0110_0010_1001 216: mov EBR2, r10 0108 : 1100_0111_0001_0000_0000_1010 217: add r10, c1, r10 0109 : 1000_0010_1010_0110_0010_1010 218: mov EBR3, r11 010A : 1100_0111_0001_1000_0000_1011 219: add r11, c1, r11 010B : 1000_0010_1011_0110_0010_1011 220: mov EBR4, r12 010C : 1100_0111_0010_0000_0000_1100 221: add r12, c1, r12 010D : 1000_0010_1100_0110_0010_1100 222: mov EBR5, r13 010E : 1100_0111_0010_1000_0000_1101 223: add r13, c1, r13 010F : 1000_0010_1101_0110_0010_1101 224: 225: mov 0, r0 ; r0: time bin numbe 0110 : 1100_0110_0000_0000_0000_0000 226: 227: shl -2, ADD_CTR, r1 ; r1: current FGAn e 0111 : 1011_0011_1110_0111_1010_0001 228: mov 3, r2 0112 : 1100_0110_0000_0000_0110_0010 229: and r2, ADD_CTR, r2 ; r2: current lower 0113 : 1010_0110_0010_0111_1010_0010 230: 231: loopTT: mov 0, r6 ; r6: error counter 0114 : 1100_0110_0000_0000_0000_0110 232: 233: add r0, OFFSET_CTR, r3 0115 : 1000_0010_0000_0111_1000_0011 234: cmp r3, 1023 0116 : 1100_1000_0011_0011_1111_1111 235: jmp cc_leu, TTval 0117 : 0000_0100_0000_0000_0001_1000 236: mov 1024, r4 0118 : 1100_0110_1000_0000_0000_0100 237: sub r3, r4, r3 0119 : 1000_1010_0011_0000_1000_0011 238: 239: TTval: shl 2, r3, r3 ; r3: expected input 011A : 1011_0010_0010_0000_0110_0011 240: 241: add r3, r1, r3 011B : 1000_0010_0011_0000_0010_0011 242: add r3, r2, r3 011C : 1000_0010_0011_0000_0100_0011 243: shl -2, r3, r3 011D : 1011_0011_1110_0000_0110_0011 244: cmp r3, 1023 011E : 1100_1000_0011_0011_1111_1111 245: jmp cc_leu, TTc0 011F : 0000_0100_0000_0000_0001_1000 246: mov 1023, r3 ; r3: expected value 0120 : 1100_0110_0111_1111_1110_0011 247: 248: TTc0: add r0, r8, r4 ; r4: event buffer a 0121 : 1000_0010_0000_0001_0000_0100 249: lpio r4, r5 0122 : 1110_0010_0000_0000_1000_0101 250: lpio r4, r5 ; r5: filter result 0123 : 1110_0010_0000_0000_1000_0101 251: 252: cmp r3, r5 0124 : 1000_1000_0011_0000_1010_0000 253: jmp cc_eq, TTc1 0125 : 0000_0100_0000_0000_0001_0001 254: add r6, c1, r6 0126 : 1000_0010_0110_0110_0010_0110 255: 256: TTc1: add r0, r9, r4 ; r4: event buffer a 0127 : 1000_0010_0000_0001_0010_0100 257: lpio r4, r5 0128 : 1110_0010_0000_0000_1000_0101 258: lpio r4, r5 ; r5: filter result 0129 : 1110_0010_0000_0000_1000_0101 259: 260: cmp r3, r5 012A : 1000_1000_0011_0000_1010_0000 261: jmp cc_eq, TTc2 012B : 0000_0100_0000_0000_0001_0001 262: add r6, c1, r6 012C : 1000_0010_0110_0110_0010_0110 263: 264: TTc2: add r0, r10, r4 ; r4: event buffer a 012D : 1000_0010_0000_0001_0100_0100 265: lpio r4, r5 012E : 1110_0010_0000_0000_1000_0101 266: lpio r4, r5 ; r5: filter result 012F : 1110_0010_0000_0000_1000_0101 267: 268: cmp r3, r5 0130 : 1000_1000_0011_0000_1010_0000 269: jmp cc_eq, TTc3 0131 : 0000_0100_0000_0000_0001_0001 270: add r6, c1, r6 0132 : 1000_0010_0110_0110_0010_0110 271: 272: TTc3: add r0, r11, r4 ; r4: event buffer a 0133 : 1000_0010_0000_0001_0110_0100 273: lpio r4, r5 0134 : 1110_0010_0000_0000_1000_0101 274: lpio r4, r5 ; r5: filter result 0135 : 1110_0010_0000_0000_1000_0101 275: 276: cmp r3, r5 0136 : 1000_1000_0011_0000_1010_0000 277: jmp cc_eq, TTc4 0137 : 0000_0100_0000_0000_0001_0001 278: add r6, c1, r6 0138 : 1000_0010_0110_0110_0010_0110 279: 280: TTc4: add r0, r12, r4 ; r4: event buffer a 0139 : 1000_0010_0000_0001_1000_0100 281: lpio r4, r5 013A : 1110_0010_0000_0000_1000_0101 282: lpio r4, r5 ; r5: filter result 013B : 1110_0010_0000_0000_1000_0101 283: 284: cmp r3, r5 013C : 1000_1000_0011_0000_1010_0000 285: jmp cc_eq, TTc5 013D : 0000_0100_0000_0000_0001_0001 286: add r6, c1, r6 013E : 1000_0010_0110_0110_0010_0110 287: 288: #ifdef cpu3 289: TTc5: add r0, r13, r4 ; r4: event buffer a 290: lpio r4, r5 291: lpio r4, r5 ; r5: filter result 292: 293: cmp r3, r5 294: jmp cc_eq, TTend 295: add r6, c1, r6 296: #else 297: nop 013F : 0000_0000_0000_0000_0000_0000 298: nop 0140 : 0000_0000_0000_0000_0000_0000 299: nop 0141 : 0000_0000_0000_0000_0000_0000 300: 301: nop 0142 : 0000_0000_0000_0000_0000_0000 302: nop 0143 : 0000_0000_0000_0000_0000_0000 303: TTc5: nop 0144 : 0000_0000_0000_0000_0000_0000 304: #endif 305: 306: TTend: add r6, ERROR_CTR, r6 0145 : 1000_0010_0110_0111_0000_0110 307: jmpr cc_busy, 0 0146 : 0000_0100_0010_1000_1101_0111 308: sgio r6, ERROR_ADR 0147 : 0010_1000_0110_1100_0001_0000 309: 310: add r0, c1, r0 0148 : 1000_0010_0000_0110_0010_0000 311: cmp r0, 31 0149 : 1100_1000_0000_0000_0001_1111 312: jmp cc_ltu, loopTT 014A : 0000_0100_0000_0000_0001_0000 313: nop 014B : 0000_0000_0000_0000_0000_0000 314: 315: 316: 317: 318: ;########################################### 319: ;# 320: ;# increase counters 321: ;# 322: ;########################################### 323: 324: 325: #ifdef cpu3 326: 327: mov 1, r1 328: add r1, ADD_CTR, r0 329: cmp r0, 256 330: jmp cc_ltu, ct_LUT 331: 332: mov 0, r0 333: mov 31, r1 334: add r1, OFFSET_CTR, r1 335: 336: jmpr cc_busy, 0 337: sgio r1, OFFSET_ADR 338: 339: ct_LUT: jmpr cc_busy, 0 340: sgio r0, ADD_ADR 341: 342: #else 343: 344: nop 014C : 0000_0000_0000_0000_0000_0000 345: nop 014D : 0000_0000_0000_0000_0000_0000 346: nop 014E : 0000_0000_0000_0000_0000_0000 347: nop 014F : 0000_0000_0000_0000_0000_0000 348: 349: nop 0150 : 0000_0000_0000_0000_0000_0000 350: nop 0151 : 0000_0000_0000_0000_0000_0000 351: nop 0152 : 0000_0000_0000_0000_0000_0000 352: 353: nop 0153 : 0000_0000_0000_0000_0000_0000 354: nop 0154 : 0000_0000_0000_0000_0000_0000 355: 356: nop 0155 : 0000_0000_0000_0000_0000_0000 357: nop 0156 : 0000_0000_0000_0000_0000_0000 358: 359: #endif 360: 361: jmpr cc_busy, 0 0157 : 0000_0100_0010_1010_1111_0111 362: 363: 364: 365: ;########################################### 366: ;# 367: ;# write next LUT test entries 368: ;# 369: ;########################################### 370: 371: 372: shl -2, ADD_CTR, r12 ; r12: next FGAn ent 0158 : 1011_0011_1110_0111_1010_1100 373: mov 3, r13 0159 : 1100_0110_0000_0000_0110_1101 374: and r13, ADD_CTR, r13 ; r13: next lower 2 015A : 1010_0110_1101_0111_1010_1101 375: 376: iext FGAn 015B : 0101_0000_0000_0000_0000_0011 377: mov FGAn, r0 015C : 1100_0110_0001_0100_0000_0000 378: 379: mov 0, r1 015D : 1100_0110_0000_0000_0000_0001 380: 381: loopLT: add r0, r1, r2 015E : 1000_0010_0000_0000_0010_0010 382: jmpr cc_busy, 0 015F : 0000_0100_0010_1011_1111_0111 383: sgio r12, r2 0160 : 0010_0100_1100_0000_0100_0000 384: 385: add r1, c1, r1 0161 : 1000_0010_0001_0110_0010_0001 386: cmp r1, 21 0162 : 1100_1000_0001_0000_0001_0101 387: jmp cc_ltu, loopLT 0163 : 0000_0100_0000_0000_0001_0000 388: 389: iext FPNP 0164 : 0101_0000_0000_0000_0000_0011 390: mov FPNP, r0 0165 : 1100_0110_0000_0100_0010_0000 391: 392: jmpr cc_busy, 0 0166 : 0000_0100_0010_1100_1101_0111 393: sgio r13, r0 0167 : 0010_0100_1101_0000_0000_0000 394: 395: 396: 397: ;########################################### 398: ;# 399: ;# write next test pattern into event b 400: ;# 401: ;########################################### 402: 403: 404: #ifdef cpu3 405: 406: mov 0, r0 407: cmp r0, ADD_CTR 408: jmp cc_neq, endEB 409: 410: iext EBW 411: mov EBW, r0 412: mov 32, r1 413: add r0, r1, r0 ; r0: event buffer o 414: 415: mov 0, r1 ; r1: channel number 416: mov 0, r2 ; r2: time bin numbe 417: 418: loopEB: 419: add r2, OFFSET_CTR, r4 420: shl 7, r1, r3 421: add r0, r3, r3 422: add r2, r3, r3 423: 424: jmpr cc_busy, 0 ; r3: single event b 425: sgio r4, r3 ; r4: data to write 426: 427: mov 10, r5 428: 429: waitD: sub r5, c1, r5 430: jmp cc_gts, waitD 431: 432: add r1, c1, r1 433: cmp r1, 21 434: jmp cc_ltu, loopEB 435: 436: mov 0, r1 437: add r2, c1, r2 438: cmp r2, 32 439: jmp cc_ltu, loopEB 440: nop 441: endEB: mov 1, CPU_SYNC 442: 443: #else 444: 445: nop 0168 : 0000_0000_0000_0000_0000_0000 446: 447: #endif 448: 449: 450: 451: ;########################################### 452: ;# 453: ;# wait for data writing completion 454: ;# 455: ;########################################### 456: 457: 458: wsy: mov CPU_SYNC, r0 0169 : 1100_0010_0000_0010_0010_0000 459: cmp r0, 1 016A : 1100_1000_0000_0000_0000_0001 460: jmp cc_neq, wsy 016B : 0000_0100_0000_0000_0000_0001 461: 462: 463: ;########################################### 464: ;# 465: ;# copy lower indicator words 466: ;# 467: ;########################################### 468: 469: 470: #ifdef cpu0 471: mov 0x7B8, r15 472: #endif 473: 474: #ifdef cpu1 475: mov 0x7CC, r15 476: #endif 477: 478: #ifdef cpu2 479: mov 0x7E0, r15 016C : 1100_0110_1111_1100_0000_1111 480: #endif 481: 482: #ifdef cpu3 483: mov 0x7F4, r15 484: #endif 485: 486: lpio EBI0, r0 016D : 1110_0111_0011_0000_0000_0000 487: lpio EBI0, r0 016E : 1110_0111_0011_0000_0000_0000 488: sra+ r0 016F : 0011_1000_0000_0000_0000_0000 489: 490: lpio EBI2, r0 0170 : 1110_0111_0011_0000_0100_0000 491: lpio EBI2, r0 0171 : 1110_0111_0011_0000_0100_0000 492: sra+ r0 0172 : 0011_1000_0000_0000_0000_0000 493: 494: lpio EBI4, r0 0173 : 1110_0111_0011_0000_1000_0000 495: lpio EBI4, r0 0174 : 1110_0111_0011_0000_1000_0000 496: sra+ r0 0175 : 0011_1000_0000_0000_0000_0000 497: 498: lpio EBI6, r0 0176 : 1110_0111_0011_0000_1100_0000 499: lpio EBI6, r0 0177 : 1110_0111_0011_0000_1100_0000 500: sra+ r0 0178 : 0011_1000_0000_0000_0000_0000 501: 502: lpio EBI8, r0 0179 : 1110_0111_0011_0001_0000_0000 503: lpio EBI8, r0 017A : 1110_0111_0011_0001_0000_0000 504: sra+ r0 017B : 0011_1000_0000_0000_0000_0000 505: 506: #ifdef cpu3 507: lpio EBIA, r0 508: lpio EBIA, r0 509: sra+ r0 510: #else 511: nop 017C : 0000_0000_0000_0000_0000_0000 512: nop 017D : 0000_0000_0000_0000_0000_0000 513: nop 017E : 0000_0000_0000_0000_0000_0000 514: #endif 515: 516: 517: ;########################################### 518: ;# 519: ;# DMEM address to copy event buffer da 520: ;# beware: byte address = 4 * word addr 521: ;# 522: ;########################################### 523: 524: #ifdef cpu0 525: mov 0x080, r15 526: #endif 527: 528: #ifdef cpu1 529: mov 0x238, r15 530: #endif 531: 532: #ifdef cpu2 533: mov 0x3F0, r15 017F : 1100_0110_0111_1110_0000_1111 534: #endif 535: 536: #ifdef cpu3 537: mov 0x5A8, r15 538: #endif 539: 540: ;########################################### 541: ;# 542: ;# channel check bits, absolute channel 543: ;# 544: ;########################################### 545: 546: #ifdef cpu0 547: mov 3, r3 548: #endif 549: 550: #ifdef cpu1 551: mov 2, r3 552: #endif 553: 554: #ifdef cpu2 555: mov 3, r3 0180 : 1100_0110_0000_0000_0110_0011 556: #endif 557: 558: #ifdef cpu3 559: mov 2, r3 560: #endif 561: 562: ;########################################### 563: ;# 564: ;# copy event buffer data of CPU's chan 565: ;# 566: ;########################################### 567: 568: mov EBR0, r14 0181 : 1100_0111_0000_0000_0000_1110 569: mov 66, r5 0182 : 1100_0110_0000_1000_0100_0101 570: 571: loop0: lpio+ r0 0183 : 1110_1110_0000_0000_0000_0000 572: lpio+ r0 0184 : 1110_1110_0000_0000_0000_0000 573: lpio+ r1 0185 : 1110_1110_0000_0000_0000_0001 574: lpio r14, r2 0186 : 1110_0010_0000_0001_1100_0010 575: 576: shl 10, r2, r2 0187 : 1011_0010_1010_0000_0100_0010 577: or r1, r2, r2 0188 : 1010_1010_0001_0000_0100_0010 578: shl 10, r2, r2 0189 : 1011_0010_1010_0000_0100_0010 579: or r0, r2, r2 018A : 1010_1010_0000_0000_0100_0010 580: shl 2, r2, r2 018B : 1011_0010_0010_0000_0100_0010 581: or r3, r2, r2 018C : 1010_1010_0011_0000_0100_0010 582: 583: sra+ r2 018D : 0011_1000_0010_0000_0000_0000 584: 585: sub r5, c3, r5 018E : 1000_1010_0101_0110_0110_0101 586: jmp cc_gtu, loop0 018F : 0000_0100_0000_0000_0000_1000 587: 588: ;########################################### 589: ;# 590: ;# copy event buffer data of CPU's chan 591: ;# 592: ;########################################### 593: 594: mov EBR1, r14 0190 : 1100_0111_0000_1000_0000_1110 595: mov 66, r5 0191 : 1100_0110_0000_1000_0100_0101 596: xor r3, c1, r3 0192 : 1010_0010_0011_0110_0010_0011 597: 598: loop1: lpio+ r0 0193 : 1110_1110_0000_0000_0000_0000 599: lpio+ r0 0194 : 1110_1110_0000_0000_0000_0000 600: lpio+ r1 0195 : 1110_1110_0000_0000_0000_0001 601: lpio r14, r2 0196 : 1110_0010_0000_0001_1100_0010 602: 603: shl 10, r2, r2 0197 : 1011_0010_1010_0000_0100_0010 604: or r1, r2, r2 0198 : 1010_1010_0001_0000_0100_0010 605: shl 10, r2, r2 0199 : 1011_0010_1010_0000_0100_0010 606: or r0, r2, r2 019A : 1010_1010_0000_0000_0100_0010 607: shl 2, r2, r2 019B : 1011_0010_0010_0000_0100_0010 608: or r3, r2, r2 019C : 1010_1010_0011_0000_0100_0010 609: 610: sra+ r2 019D : 0011_1000_0010_0000_0000_0000 611: 612: sub r5, c3, r5 019E : 1000_1010_0101_0110_0110_0101 613: jmp cc_gtu, loop1 019F : 0000_0100_0000_0000_0000_1000 614: 615: ;########################################### 616: ;# 617: ;# copy event buffer data of CPU's chan 618: ;# 619: ;########################################### 620: 621: mov EBR2, r14 01A0 : 1100_0111_0001_0000_0000_1110 622: mov 66, r5 01A1 : 1100_0110_0000_1000_0100_0101 623: xor r3, c1, r3 01A2 : 1010_0010_0011_0110_0010_0011 624: 625: loop2: lpio+ r0 01A3 : 1110_1110_0000_0000_0000_0000 626: lpio+ r0 01A4 : 1110_1110_0000_0000_0000_0000 627: lpio+ r1 01A5 : 1110_1110_0000_0000_0000_0001 628: lpio r14, r2 01A6 : 1110_0010_0000_0001_1100_0010 629: 630: shl 10, r2, r2 01A7 : 1011_0010_1010_0000_0100_0010 631: or r1, r2, r2 01A8 : 1010_1010_0001_0000_0100_0010 632: shl 10, r2, r2 01A9 : 1011_0010_1010_0000_0100_0010 633: or r0, r2, r2 01AA : 1010_1010_0000_0000_0100_0010 634: shl 2, r2, r2 01AB : 1011_0010_0010_0000_0100_0010 635: or r3, r2, r2 01AC : 1010_1010_0011_0000_0100_0010 636: 637: sra+ r2 01AD : 0011_1000_0010_0000_0000_0000 638: 639: sub r5, c3, r5 01AE : 1000_1010_0101_0110_0110_0101 640: jmp cc_gtu, loop2 01AF : 0000_0100_0000_0000_0000_1000 641: 642: ;########################################### 643: ;# 644: ;# copy event buffer data of CPU's chan 645: ;# 646: ;########################################### 647: 648: mov EBR3, r14 01B0 : 1100_0111_0001_1000_0000_1110 649: mov 66, r5 01B1 : 1100_0110_0000_1000_0100_0101 650: xor r3, c1, r3 01B2 : 1010_0010_0011_0110_0010_0011 651: 652: loop3: lpio+ r0 01B3 : 1110_1110_0000_0000_0000_0000 653: lpio+ r0 01B4 : 1110_1110_0000_0000_0000_0000 654: lpio+ r1 01B5 : 1110_1110_0000_0000_0000_0001 655: lpio r14, r2 01B6 : 1110_0010_0000_0001_1100_0010 656: 657: shl 10, r2, r2 01B7 : 1011_0010_1010_0000_0100_0010 658: or r1, r2, r2 01B8 : 1010_1010_0001_0000_0100_0010 659: shl 10, r2, r2 01B9 : 1011_0010_1010_0000_0100_0010 660: or r0, r2, r2 01BA : 1010_1010_0000_0000_0100_0010 661: shl 2, r2, r2 01BB : 1011_0010_0010_0000_0100_0010 662: or r3, r2, r2 01BC : 1010_1010_0011_0000_0100_0010 663: 664: sra+ r2 01BD : 0011_1000_0010_0000_0000_0000 665: 666: sub r5, c3, r5 01BE : 1000_1010_0101_0110_0110_0101 667: jmp cc_gtu, loop3 01BF : 0000_0100_0000_0000_0000_1000 668: 669: ;########################################### 670: ;# 671: ;# copy event buffer data of CPU's chan 672: ;# 673: ;########################################### 674: 675: mov EBR4, r14 01C0 : 1100_0111_0010_0000_0000_1110 676: mov 66, r5 01C1 : 1100_0110_0000_1000_0100_0101 677: xor r3, c1, r3 01C2 : 1010_0010_0011_0110_0010_0011 678: 679: loop4: lpio+ r0 01C3 : 1110_1110_0000_0000_0000_0000 680: lpio+ r0 01C4 : 1110_1110_0000_0000_0000_0000 681: lpio+ r1 01C5 : 1110_1110_0000_0000_0000_0001 682: lpio r14, r2 01C6 : 1110_0010_0000_0001_1100_0010 683: 684: shl 10, r2, r2 01C7 : 1011_0010_1010_0000_0100_0010 685: or r1, r2, r2 01C8 : 1010_1010_0001_0000_0100_0010 686: shl 10, r2, r2 01C9 : 1011_0010_1010_0000_0100_0010 687: or r0, r2, r2 01CA : 1010_1010_0000_0000_0100_0010 688: shl 2, r2, r2 01CB : 1011_0010_0010_0000_0100_0010 689: or r3, r2, r2 01CC : 1010_1010_0011_0000_0100_0010 690: 691: sra+ r2 01CD : 0011_1000_0010_0000_0000_0000 692: 693: sub r5, c3, r5 01CE : 1000_1010_0101_0110_0110_0101 694: jmp cc_gtu, loop4 01CF : 0000_0100_0000_0000_0000_1000 695: 696: ;########################################### 697: ;# 698: ;# copy event buffer data of CPU's chan 699: ;# 700: ;########################################### 701: 702: #ifdef cpu3 703: mov EBR5, r14 704: mov 66, r5 705: xor r3, c1, r3 706: 707: loop5: lpio+ r0 708: lpio+ r0 709: lpio+ r1 710: lpio r14, r2 711: 712: shl 10, r2, r2 713: or r1, r2, r2 714: shl 10, r2, r2 715: or r0, r2, r2 716: shl 2, r2, r2 717: or r3, r2, r2 718: 719: sra+ r2 720: 721: sub r5, c3, r5 722: jmp cc_gtu, loop5 723: #else 724: nop 01D0 : 0000_0000_0000_0000_0000_0000 725: nop 01D1 : 0000_0000_0000_0000_0000_0000 726: nop 01D2 : 0000_0000_0000_0000_0000_0000 727: nop 01D3 : 0000_0000_0000_0000_0000_0000 728: nop 01D4 : 0000_0000_0000_0000_0000_0000 729: nop 01D5 : 0000_0000_0000_0000_0000_0000 730: nop 01D6 : 0000_0000_0000_0000_0000_0000 731: nop 01D7 : 0000_0000_0000_0000_0000_0000 732: nop 01D8 : 0000_0000_0000_0000_0000_0000 733: nop 01D9 : 0000_0000_0000_0000_0000_0000 734: nop 01DA : 0000_0000_0000_0000_0000_0000 735: nop 01DB : 0000_0000_0000_0000_0000_0000 736: nop 01DC : 0000_0000_0000_0000_0000_0000 737: nop 01DD : 0000_0000_0000_0000_0000_0000 738: nop 01DE : 0000_0000_0000_0000_0000_0000 739: nop 01DF : 0000_0000_0000_0000_0000_0000 740: #endif 741: 742: 743: ;########################################### 744: ;# 745: ;# end current state, goto clear state 746: ;# 747: ;########################################### 748: 749: 750: #ifdef cpu3 751: 752: mov 0, r0 753: jmpr cc_busy, 0 754: sgio r0, EBSIM_FAST 755: 756: mov CMD_CLEAR, r0 757: jmpr cc_busy, 0 758: sgio r0, SMCMD 759: 760: #else 761: 762: nop 01E0 : 0000_0000_0000_0000_0000_0000 763: nop 01E1 : 0000_0000_0000_0000_0000_0000 764: nop 01E2 : 0000_0000_0000_0000_0000_0000 765: 766: nop 01E3 : 0000_0000_0000_0000_0000_0000 767: nop 01E4 : 0000_0000_0000_0000_0000_0000 768: nop 01E5 : 0000_0000_0000_0000_0000_0000 769: 770: #endif 771: 772: 773: 774: ;########################################### 775: ;# 776: ;# switch off own clock after transfer 777: ;# 778: ;########################################### 779: 780: 781: clkoff: mov 0, r0 01E6 : 1100_0110_0000_0000_0000_0000 782: jmpr cc_busy, 0 01E7 : 0000_0100_0011_1100_1111_0111 783: 784: #ifdef cpu0 785: sgio r0, CPU0SS 786: #endif 787: 788: #ifdef cpu1 789: sgio r0, CPU1SS 790: #endif 791: 792: #ifdef cpu2 793: sgio r0, CPU2SS 01E8 : 0010_1000_0000_1010_0010_0101 794: #endif 795: 796: #ifdef cpu3 797: sgio r0, CPU3SS 798: #endif 799: 800: jmp cc_uncond, clkoff 01E9 : 0000_0100_0000_0000_0000_1111 801: nop 01EA : 0000_0000_0000_0000_0000_0000 802: 803: 804: 805: ;################################################### 806: ;# 807: ;# 0x0300: Interrrupt Raw Data Readout Jump Add 808: ;# 809: ;# Nothing to be done here. 810: ;# 811: ;################################################### 812: 813: 814: org 0x300 815: 816: jmp cc_uncond, clkoff 0300 : 0000_0100_0000_0000_0000_1111 817: nop 0301 : 0000_0000_0000_0000_0000_0000 818: 819: 820: 821: 822: 823: 824: 825: 826: 827: 828: 829: 830: 831: 832: 833: 834: 835: 836: Source file read, 0 error(s), 0 warning(s).